Searched refs:timing (Results 1 - 200 of 836) sorted by relevance

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/linux-4.1.27/drivers/gpu/drm/tegra/
H A Dmipi-phy.c19 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, mipi_dphy_timing_get_default() argument
22 timing->clkmiss = 0; mipi_dphy_timing_get_default()
23 timing->clkpost = 70 + 52 * period; mipi_dphy_timing_get_default()
24 timing->clkpre = 8; mipi_dphy_timing_get_default()
25 timing->clkprepare = 65; mipi_dphy_timing_get_default()
26 timing->clksettle = 95; mipi_dphy_timing_get_default()
27 timing->clktermen = 0; mipi_dphy_timing_get_default()
28 timing->clktrail = 80; mipi_dphy_timing_get_default()
29 timing->clkzero = 260; mipi_dphy_timing_get_default()
30 timing->dtermen = 0; mipi_dphy_timing_get_default()
31 timing->eot = 0; mipi_dphy_timing_get_default()
32 timing->hsexit = 120; mipi_dphy_timing_get_default()
33 timing->hsprepare = 65 + 5 * period; mipi_dphy_timing_get_default()
34 timing->hszero = 145 + 5 * period; mipi_dphy_timing_get_default()
35 timing->hssettle = 85 + 6 * period; mipi_dphy_timing_get_default()
36 timing->hsskip = 40; mipi_dphy_timing_get_default()
49 timing->hstrail = max(4 * 8 * period, 60 + 4 * 4 * period); mipi_dphy_timing_get_default()
51 timing->init = 100000; mipi_dphy_timing_get_default()
52 timing->lpx = 60; mipi_dphy_timing_get_default()
53 timing->taget = 5 * timing->lpx; mipi_dphy_timing_get_default()
54 timing->tago = 4 * timing->lpx; mipi_dphy_timing_get_default()
55 timing->tasure = 2 * timing->lpx; mipi_dphy_timing_get_default()
56 timing->wakeup = 1000000; mipi_dphy_timing_get_default()
62 * Validate D-PHY timing according to MIPI D-PHY specification (v1.2, Section
65 int mipi_dphy_timing_validate(struct mipi_dphy_timing *timing, mipi_dphy_timing_validate() argument
68 if (timing->clkmiss > 60) mipi_dphy_timing_validate()
71 if (timing->clkpost < (60 + 52 * period)) mipi_dphy_timing_validate()
74 if (timing->clkpre < 8) mipi_dphy_timing_validate()
77 if (timing->clkprepare < 38 || timing->clkprepare > 95) mipi_dphy_timing_validate()
80 if (timing->clksettle < 95 || timing->clksettle > 300) mipi_dphy_timing_validate()
83 if (timing->clktermen > 38) mipi_dphy_timing_validate()
86 if (timing->clktrail < 60) mipi_dphy_timing_validate()
89 if (timing->clkprepare + timing->clkzero < 300) mipi_dphy_timing_validate()
92 if (timing->dtermen > 35 + 4 * period) mipi_dphy_timing_validate()
95 if (timing->eot > 105 + 12 * period) mipi_dphy_timing_validate()
98 if (timing->hsexit < 100) mipi_dphy_timing_validate()
101 if (timing->hsprepare < 40 + 4 * period || mipi_dphy_timing_validate()
102 timing->hsprepare > 85 + 6 * period) mipi_dphy_timing_validate()
105 if (timing->hsprepare + timing->hszero < 145 + 10 * period) mipi_dphy_timing_validate()
108 if ((timing->hssettle < 85 + 6 * period) || mipi_dphy_timing_validate()
109 (timing->hssettle > 145 + 10 * period)) mipi_dphy_timing_validate()
112 if (timing->hsskip < 40 || timing->hsskip > 55 + 4 * period) mipi_dphy_timing_validate()
115 if (timing->hstrail < max(8 * period, 60 + 4 * period)) mipi_dphy_timing_validate()
118 if (timing->init < 100000) mipi_dphy_timing_validate()
121 if (timing->lpx < 50) mipi_dphy_timing_validate()
124 if (timing->taget != 5 * timing->lpx) mipi_dphy_timing_validate()
127 if (timing->tago != 4 * timing->lpx) mipi_dphy_timing_validate()
130 if (timing->tasure < timing->lpx || timing->tasure > 2 * timing->lpx) mipi_dphy_timing_validate()
133 if (timing->wakeup < 1000000) mipi_dphy_timing_validate()
H A Dmipi-phy.h13 * D-PHY timing parameters
46 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
48 int mipi_dphy_timing_validate(struct mipi_dphy_timing *timing,
H A Ddsi.c34 struct mipi_dphy_timing timing; member in struct:tegra_dsi_state
367 const struct mipi_dphy_timing *timing) tegra_dsi_set_phy_timing()
371 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 | tegra_dsi_set_phy_timing()
372 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 | tegra_dsi_set_phy_timing()
373 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 | tegra_dsi_set_phy_timing()
374 DSI_TIMING_FIELD(timing->hsprepare, period, 1); tegra_dsi_set_phy_timing()
377 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 | tegra_dsi_set_phy_timing()
378 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 | tegra_dsi_set_phy_timing()
379 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 | tegra_dsi_set_phy_timing()
380 DSI_TIMING_FIELD(timing->lpx, period, 1); tegra_dsi_set_phy_timing()
383 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 | tegra_dsi_set_phy_timing()
384 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 | tegra_dsi_set_phy_timing()
388 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 | tegra_dsi_set_phy_timing()
389 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 | tegra_dsi_set_phy_timing()
390 DSI_TIMING_FIELD(timing->tago, period, 1); tegra_dsi_set_phy_timing()
394 tegra_dsi_set_phy_timing(dsi->slave, period, timing); tegra_dsi_set_phy_timing()
812 * The D-PHY timing fields are expressed in byte-clock cycles, so tegra_dsi_encoder_mode_set()
815 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing); tegra_dsi_encoder_mode_set()
919 err = mipi_dphy_timing_get_default(&state->timing, state->period); tegra_dsi_encoder_atomic_check()
923 err = mipi_dphy_timing_validate(&state->timing, state->period); tegra_dsi_encoder_atomic_check()
925 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err); tegra_dsi_encoder_atomic_check()
365 tegra_dsi_set_phy_timing(struct tegra_dsi *dsi, unsigned long period, const struct mipi_dphy_timing *timing) tegra_dsi_set_phy_timing() argument
/linux-4.1.27/drivers/gpu/drm/msm/dsi/
H A Ddsi_phy.c40 struct dsi_dphy_timing timing; member in struct:msm_dsi_phy
61 static void dsi_dphy_timing_calc_clk_zero(struct dsi_dphy_timing *timing, dsi_dphy_timing_calc_clk_zero() argument
68 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; dsi_dphy_timing_calc_clk_zero()
79 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; dsi_dphy_timing_calc_clk_zero()
80 timing->clk_zero = clk_z + 8 - temp; dsi_dphy_timing_calc_clk_zero()
83 static int dsi_dphy_timing_calc(struct dsi_dphy_timing *timing, dsi_dphy_timing_calc() argument
103 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true); dsi_dphy_timing_calc()
107 timing->hs_rqst = temp; dsi_dphy_timing_calc()
109 timing->hs_rqst = max_t(s32, 0, temp - 2); dsi_dphy_timing_calc()
112 dsi_dphy_timing_calc_clk_zero(timing, ui, coeff, pcnt2); dsi_dphy_timing_calc()
117 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, true); dsi_dphy_timing_calc()
123 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, true); dsi_dphy_timing_calc()
126 temp = ((timing->hs_prepare >> 1) + 1) * 2 * ui + 2 * ui; dsi_dphy_timing_calc()
129 timing->hs_zero = linear_inter(tmax, tmin, pcnt2, 24, true); dsi_dphy_timing_calc()
135 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, true); dsi_dphy_timing_calc()
139 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, true); dsi_dphy_timing_calc()
142 temp = ((timing->hs_exit >> 1) + 1) * 2 * ui; dsi_dphy_timing_calc()
145 timing->clk_post = linear_inter(tmax, tmin, pcnt2, 0, false); dsi_dphy_timing_calc()
148 temp = ((timing->clk_prepare >> 1) + 1) * 2 * ui; dsi_dphy_timing_calc()
149 temp += ((timing->clk_zero >> 1) + 1) * 2 * ui; dsi_dphy_timing_calc()
154 timing->clk_pre = temp >> 1; dsi_dphy_timing_calc()
157 timing->clk_pre = linear_inter(tmax, tmin, pcnt2, 0, false); dsi_dphy_timing_calc()
160 timing->ta_go = 3; dsi_dphy_timing_calc()
161 timing->ta_sure = 0; dsi_dphy_timing_calc()
162 timing->ta_get = 4; dsi_dphy_timing_calc()
165 timing->clk_pre, timing->clk_post, timing->clk_zero, dsi_dphy_timing_calc()
166 timing->clk_trail, timing->clk_prepare, timing->hs_exit, dsi_dphy_timing_calc()
167 timing->hs_zero, timing->hs_prepare, timing->hs_trail, dsi_dphy_timing_calc()
168 timing->hs_rqst); dsi_dphy_timing_calc()
195 struct dsi_dphy_timing *timing = &phy->timing; dsi_28nm_phy_enable() local
201 if (dsi_dphy_timing_calc(timing, bit_rate, esc_rate)) { dsi_28nm_phy_enable()
202 pr_err("%s: D-PHY timing calculation failed\n", __func__); dsi_28nm_phy_enable()
213 DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); dsi_28nm_phy_enable()
215 DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); dsi_28nm_phy_enable()
217 DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); dsi_28nm_phy_enable()
218 if (timing->clk_zero & BIT(8)) dsi_28nm_phy_enable()
222 DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); dsi_28nm_phy_enable()
224 DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); dsi_28nm_phy_enable()
226 DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); dsi_28nm_phy_enable()
228 DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail)); dsi_28nm_phy_enable()
230 DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst)); dsi_28nm_phy_enable()
232 DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) | dsi_28nm_phy_enable()
233 DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure)); dsi_28nm_phy_enable()
235 DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get)); dsi_28nm_phy_enable()
348 *clk_pre = phy->timing.clk_pre; msm_dsi_phy_get_clk_pre_post()
350 *clk_post = phy->timing.clk_post; msm_dsi_phy_get_clk_pre_post()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dtiming.c26 #include <subdev/bios/timing.h>
33 u16 timing = 0x0000; nvbios_timingTe() local
37 timing = nv_ro16(bios, bit_P.offset + 4); nvbios_timingTe()
40 timing = nv_ro16(bios, bit_P.offset + 8); nvbios_timingTe()
42 if (timing) { nvbios_timingTe()
43 *ver = nv_ro08(bios, timing + 0); nvbios_timingTe()
46 *hdr = nv_ro08(bios, timing + 1); nvbios_timingTe()
47 *cnt = nv_ro08(bios, timing + 2); nvbios_timingTe()
48 *len = nv_ro08(bios, timing + 3); nvbios_timingTe()
51 return timing; nvbios_timingTe()
53 *hdr = nv_ro08(bios, timing + 1); nvbios_timingTe()
54 *cnt = nv_ro08(bios, timing + 5); nvbios_timingTe()
55 *len = nv_ro08(bios, timing + 2); nvbios_timingTe()
56 *snr = nv_ro08(bios, timing + 4); nvbios_timingTe()
57 *ssz = nv_ro08(bios, timing + 3); nvbios_timingTe()
58 return timing; nvbios_timingTe()
73 u16 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz); nvbios_timingEe() local
74 if (timing && idx < *cnt) { nvbios_timingEe()
75 timing += *hdr + idx * (*len + (snr * ssz)); nvbios_timingEe()
79 return timing; nvbios_timingEe()
133 p->timing[0] = nv_ro32(bios, data + 0x00); nvbios_timingEp()
134 p->timing[1] = nv_ro32(bios, data + 0x04); nvbios_timingEp()
135 p->timing[2] = nv_ro32(bios, data + 0x08); nvbios_timingEp()
136 p->timing[3] = nv_ro32(bios, data + 0x0c); nvbios_timingEp()
137 p->timing[4] = nv_ro32(bios, data + 0x10); nvbios_timingEp()
138 p->timing[5] = nv_ro32(bios, data + 0x14); nvbios_timingEp()
139 p->timing[6] = nv_ro32(bios, data + 0x18); nvbios_timingEp()
140 p->timing[7] = nv_ro32(bios, data + 0x1c); nvbios_timingEp()
141 p->timing[8] = nv_ro32(bios, data + 0x20); nvbios_timingEp()
142 p->timing[9] = nv_ro32(bios, data + 0x24); nvbios_timingEp()
143 p->timing[10] = nv_ro32(bios, data + 0x28); nvbios_timingEp()
/linux-4.1.27/arch/avr32/mach-at32ap/
H A Dhsmc.c33 const struct smc_timing *timing) smc_set_timing()
62 if (timing->ncs_read_setup > 0) smc_set_timing()
63 config->ncs_read_setup = ns2cyc(timing->ncs_read_setup); smc_set_timing()
65 if (timing->nrd_setup > 0) smc_set_timing()
66 config->nrd_setup = ns2cyc(timing->nrd_setup); smc_set_timing()
68 if (timing->ncs_write_setup > 0) smc_set_timing()
69 config->ncs_write_setup = ns2cyc(timing->ncs_write_setup); smc_set_timing()
71 if (timing->nwe_setup > 0) smc_set_timing()
72 config->nwe_setup = ns2cyc(timing->nwe_setup); smc_set_timing()
74 if (timing->ncs_read_pulse > 0) smc_set_timing()
75 config->ncs_read_pulse = ns2cyc(timing->ncs_read_pulse); smc_set_timing()
77 if (timing->nrd_pulse > 0) smc_set_timing()
78 config->nrd_pulse = ns2cyc(timing->nrd_pulse); smc_set_timing()
80 if (timing->ncs_write_pulse > 0) smc_set_timing()
81 config->ncs_write_pulse = ns2cyc(timing->ncs_write_pulse); smc_set_timing()
83 if (timing->nwe_pulse > 0) smc_set_timing()
84 config->nwe_pulse = ns2cyc(timing->nwe_pulse); smc_set_timing()
86 if (timing->read_cycle > 0) smc_set_timing()
87 config->read_cycle = ns2cyc(timing->read_cycle); smc_set_timing()
89 if (timing->write_cycle > 0) smc_set_timing()
90 config->write_cycle = ns2cyc(timing->write_cycle); smc_set_timing()
93 if (timing->ncs_read_recover > 0) smc_set_timing()
94 recover = ns2cyc(timing->ncs_read_recover); smc_set_timing()
104 if (timing->nrd_recover > 0) smc_set_timing()
105 recover = ns2cyc(timing->nrd_recover); smc_set_timing()
115 if (timing->ncs_write_recover > 0) smc_set_timing()
116 recover = ns2cyc(timing->ncs_write_recover); smc_set_timing()
126 if (timing->nwe_recover > 0) smc_set_timing()
127 recover = ns2cyc(timing->nwe_recover); smc_set_timing()
32 smc_set_timing(struct smc_config *config, const struct smc_timing *timing) smc_set_timing() argument
/linux-4.1.27/drivers/staging/sm750fb/
H A Dddk750_mode.h16 /* Horizontal timing. */
23 /* Vertical timing. */
30 /* Refresh timing. */
H A Dddk750_display.c11 /* state != 0 means turn on both timing & plane en_bit */ setDisplayControl()
63 * wait for 1 vsync before modifying the timing enable bit. setDisplayControl()
118 * wait for 1 vsync before modifying the timing enable bit. setDisplayControl()
254 /* set primary timing and plane en_bit */ ddk750_setLogicalDispOut()
259 /* set secondary timing and plane en_bit*/ ddk750_setLogicalDispOut()
H A Dddk750_display.h15 /* primary timing & plane enable bit
44 /* secondary timing & plane enable bit
/linux-4.1.27/drivers/gpu/drm/sti/
H A Dsti_awg_utils.c119 struct awg_timing *timing) sti_awg_generate_code_data_enable_mode()
125 if (timing->trailing_lines > 0) { sti_awg_generate_code_data_enable_mode()
127 val = timing->blanking_level; sti_awg_generate_code_data_enable_mode()
131 val = timing->trailing_lines - 1; sti_awg_generate_code_data_enable_mode()
136 if (timing->trailing_pixels > 0) { sti_awg_generate_code_data_enable_mode()
138 val = timing->blanking_level; sti_awg_generate_code_data_enable_mode()
142 val = timing->trailing_pixels - 1; sti_awg_generate_code_data_enable_mode()
148 val = timing->blanking_level; sti_awg_generate_code_data_enable_mode()
150 ret |= awg_generate_instr((timing->trailing_pixels > 0) ? SET : RPLSET, sti_awg_generate_code_data_enable_mode()
153 if (timing->blanking_pixels > 0) { sti_awg_generate_code_data_enable_mode()
155 val = timing->active_pixels - 1; sti_awg_generate_code_data_enable_mode()
160 val = timing->blanking_level; sti_awg_generate_code_data_enable_mode()
166 val = timing->active_lines - 1; sti_awg_generate_code_data_enable_mode()
170 if (timing->blanking_lines > 0) { sti_awg_generate_code_data_enable_mode()
172 val = timing->blanking_level; sti_awg_generate_code_data_enable_mode()
176 val = timing->blanking_lines - 1; sti_awg_generate_code_data_enable_mode()
117 sti_awg_generate_code_data_enable_mode( struct awg_code_generation_params *fwparams, struct awg_timing *timing) sti_awg_generate_code_data_enable_mode() argument
H A Dsti_awg_utils.h33 struct awg_timing *timing);
H A Dsti_dvo.c54 struct awg_timing *timing);
113 struct awg_timing timing; dvo_awg_generate_code() local
118 timing.total_lines = mode->vtotal; dvo_awg_generate_code()
119 timing.active_lines = mode->vdisplay; dvo_awg_generate_code()
120 timing.blanking_lines = mode->vsync_start - mode->vdisplay; dvo_awg_generate_code()
121 timing.trailing_lines = mode->vtotal - mode->vsync_start; dvo_awg_generate_code()
122 timing.total_pixels = mode->htotal; dvo_awg_generate_code()
123 timing.active_pixels = mode->hdisplay; dvo_awg_generate_code()
124 timing.blanking_pixels = mode->hsync_start - mode->hdisplay; dvo_awg_generate_code()
125 timing.trailing_pixels = mode->htotal - mode->hsync_start; dvo_awg_generate_code()
126 timing.blanking_level = BLANKING_LEVEL; dvo_awg_generate_code()
128 if (config->awg_fwgen_fct(&fw_gen_params, &timing)) { dvo_awg_generate_code()
/linux-4.1.27/drivers/video/fbdev/via/
H A Dvia_modesetting.c33 void via_set_primary_timing(const struct via_display_timing *timing) via_set_primary_timing() argument
37 raw.hor_total = timing->hor_total / 8 - 5; via_set_primary_timing()
38 raw.hor_addr = timing->hor_addr / 8 - 1; via_set_primary_timing()
39 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; via_set_primary_timing()
40 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; via_set_primary_timing()
41 raw.hor_sync_start = timing->hor_sync_start / 8; via_set_primary_timing()
42 raw.hor_sync_end = timing->hor_sync_end / 8; via_set_primary_timing()
43 raw.ver_total = timing->ver_total - 2; via_set_primary_timing()
44 raw.ver_addr = timing->ver_addr - 1; via_set_primary_timing()
45 raw.ver_blank_start = timing->ver_blank_start - 1; via_set_primary_timing()
46 raw.ver_blank_end = timing->ver_blank_end - 1; via_set_primary_timing()
47 raw.ver_sync_start = timing->ver_sync_start - 1; via_set_primary_timing()
48 raw.ver_sync_end = timing->ver_sync_end - 1; via_set_primary_timing()
50 /* unlock timing registers */ via_set_primary_timing()
83 /* lock timing registers */ via_set_primary_timing()
86 /* reset timing control */ via_set_primary_timing()
91 void via_set_secondary_timing(const struct via_display_timing *timing) via_set_secondary_timing() argument
95 raw.hor_total = timing->hor_total - 1; via_set_secondary_timing()
96 raw.hor_addr = timing->hor_addr - 1; via_set_secondary_timing()
97 raw.hor_blank_start = timing->hor_blank_start - 1; via_set_secondary_timing()
98 raw.hor_blank_end = timing->hor_blank_end - 1; via_set_secondary_timing()
99 raw.hor_sync_start = timing->hor_sync_start - 1; via_set_secondary_timing()
100 raw.hor_sync_end = timing->hor_sync_end - 1; via_set_secondary_timing()
101 raw.ver_total = timing->ver_total - 1; via_set_secondary_timing()
102 raw.ver_addr = timing->ver_addr - 1; via_set_secondary_timing()
103 raw.ver_blank_start = timing->ver_blank_start - 1; via_set_secondary_timing()
104 raw.ver_blank_end = timing->ver_blank_end - 1; via_set_secondary_timing()
105 raw.ver_sync_start = timing->ver_sync_start - 1; via_set_secondary_timing()
106 raw.ver_sync_end = timing->ver_sync_end - 1; via_set_secondary_timing()
H A Dvia_modesetting.h52 void via_set_primary_timing(const struct via_display_timing *timing);
53 void via_set_secondary_timing(const struct via_display_timing *timing);
H A Dhw.c1473 struct via_display_timing timing; var_to_timing() local
1476 timing.hor_addr = cxres; var_to_timing()
1477 timing.hor_sync_start = timing.hor_addr + var->right_margin + dx; var_to_timing()
1478 timing.hor_sync_end = timing.hor_sync_start + var->hsync_len; var_to_timing()
1479 timing.hor_total = timing.hor_sync_end + var->left_margin + dx; var_to_timing()
1480 timing.hor_blank_start = timing.hor_addr + dx; var_to_timing()
1481 timing.hor_blank_end = timing.hor_total - dx; var_to_timing()
1482 timing.ver_addr = cyres; var_to_timing()
1483 timing.ver_sync_start = timing.ver_addr + var->lower_margin + dy; var_to_timing()
1484 timing.ver_sync_end = timing.ver_sync_start + var->vsync_len; var_to_timing()
1485 timing.ver_total = timing.ver_sync_end + var->upper_margin + dy; var_to_timing()
1486 timing.ver_blank_start = timing.ver_addr + dy; var_to_timing()
1487 timing.ver_blank_end = timing.ver_total - dy; var_to_timing()
1488 return timing; var_to_timing()
/linux-4.1.27/drivers/ide/
H A Dtriflex.c41 u16 timing = 0; triflex_set_mode() local
48 timing = 0x0103; triflex_set_mode()
51 timing = 0x0203; triflex_set_mode()
54 timing = 0x0808; triflex_set_mode()
59 timing = 0x0f0f; triflex_set_mode()
62 timing = 0x0202; triflex_set_mode()
65 timing = 0x0204; triflex_set_mode()
68 timing = 0x0404; triflex_set_mode()
71 timing = 0x0508; triflex_set_mode()
74 timing = 0x0808; triflex_set_mode()
79 triflex_timings |= (timing << (16 * unit)); triflex_set_mode()
H A Damd74xx.c47 * amd_set_speed() writes timing values to the chipset registers
51 struct ide_timing *timing) amd_set_speed()
56 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); amd_set_speed()
60 ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1)); amd_set_speed()
63 ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1)); amd_set_speed()
66 case ATA_UDMA2: t = timing->udma ? (0xc0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break; amd_set_speed()
67 case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 2, 10)]) : 0x03; break; amd_set_speed()
68 case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 10)]) : 0x03; break; amd_set_speed()
69 case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 15)]) : 0x03; break; amd_set_speed()
73 if (timing->udma) amd_set_speed()
78 * amd_set_drive() computes timing values and configures the chipset
50 amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask, struct ide_timing *timing) amd_set_speed() argument
H A Dht6560b.c76 * Perhaps I should explain something about these timing values:
91 * You can obtain optimized timing values by running Holtek IDESETUP.COM
92 * for DOS. DOS drivers get their timing values from command line, where
120 u8 select, timing; ht6560b_dev_select() local
125 timing = HT_TIMING(drive); ht6560b_dev_select()
135 if (select != current_select || timing != current_timing) { ht6560b_dev_select()
137 current_timing = timing; ht6560b_dev_select()
144 * Set timing for this drive: ht6560b_dev_select()
146 outb(timing, hwif->io_ports.device_addr); ht6560b_dev_select()
149 printk("ht6560b: %s: select=%#x timing=%#x\n", ht6560b_dev_select()
150 drive->name, select, timing); ht6560b_dev_select()
285 u8 timing; ht6560b_set_pio_mode() local
294 timing = ht_pio2timings(drive, pio); ht6560b_set_pio_mode()
299 config |= timing; ht6560b_set_pio_mode()
304 printk("ht6560b: drive %s tuned to pio mode %#x timing=%#x\n", drive->name, pio, timing); ht6560b_set_pio_mode()
H A Dvia82cxxx.c117 * via_set_speed - write timing registers
120 * @timing: IDE timing data to use
122 * via_set_speed writes timing values to the chipset registers
125 static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing) via_set_speed() argument
134 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); via_set_speed()
139 ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1)); via_set_speed()
142 ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1)); via_set_speed()
145 case ATA_UDMA2: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break; via_set_speed()
146 case ATA_UDMA4: t = timing->udma ? (0xe8 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break; via_set_speed()
147 case ATA_UDMA5: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; via_set_speed()
148 case ATA_UDMA6: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; via_set_speed()
160 if (timing->udma) { via_set_speed()
175 * via_set_drive() computes timing values configures the chipset to
H A Dide-timings.c95 cycle = 0; /* use standard timing */ ide_pio_cycle_time()
97 /* Use the standard timing for the CF specific modes too */ ide_pio_cycle_time()
158 * Copy the timing from the table. ide_timing_compute()
164 * PIO/MWDMA cycle timing. ide_timing_compute()
182 * Convert the timing to bus clock counts. ide_timing_compute()
189 * DMA cycle timing is slower/equal than the current PIO timing. ide_timing_compute()
H A Dit821x.c37 * timing and policy set up. Each HDD in raid mode also has a serial
80 The high byte is the 66Mhz timing */
106 * @timing: timing info
108 * Program the PIO/MWDMA timing for this channel according to the
112 static void it821x_program(ide_drive_t *drive, u16 timing) it821x_program() argument
120 /* Program PIO/MWDMA timing bits */ it821x_program()
122 conf = timing >> 8; it821x_program()
124 conf = timing & 0xFF; it821x_program()
132 * @timing: timing info
134 * Program the UDMA timing for this drive according to the
138 static void it821x_program_udma(ide_drive_t *drive, u16 timing) it821x_program_udma() argument
146 /* Program UDMA timing bits */ it821x_program_udma()
148 conf = timing >> 8; it821x_program_udma()
150 conf = timing & 0xFF; it821x_program_udma()
275 * Load the timing settings for this device mode into the
278 * the shared MWDMA/PIO timing register.
314 * Load the timing settings for this device mode into the
352 * The IT821x has a single timing register for MWDMA and for PIO
355 * timing value is loaded into the master and slave UDMA clock
378 * The IT821x has a single timing register for MWDMA and for PIO
H A Dcs5520.c66 /* 8bit CAT/CRT - 8bit command timing for channel */ cs5520_set_pio_mode()
74 /* Data read timing */ cs5520_set_pio_mode()
78 /* Write command timing */ cs5520_set_pio_mode()
86 printk(KERN_ERR "cs55x0: bad ide timing.\n"); cs5520_set_dma_mode()
H A Dqd65xx.c84 static int timings[4]={-1,-1,-1,-1}; /* stores current timing for each timer */
106 * computes the timing value where
147 * tries to find timing from dos driver's table
177 * records the timing
180 static void qd_set_timing (ide_drive_t *drive, u8 timing) qd_set_timing() argument
185 data |= timing; qd_set_timing()
188 printk(KERN_DEBUG "%s: %#x\n", drive->name, timing); qd_set_timing()
H A Dali14xx.c71 /* timing parameter registers for each drive */
109 * This function computes timing parameters
122 /* calculate timing, according to PIO mode */ ali14xx_set_pio_mode()
134 /* stuff timing parameters into controller registers */ ali14xx_set_pio_mode()
H A Dsc1200.c99 * set the appropriate timing bits on the fly, but that might be
150 * The correct timing depends on the fast PCI clock freq. sc1200_set_dma_mode()
243 * save timing registers sc1200_suspend()
267 * restore timing registers sc1200_resume()
H A Dopti621.c23 #define READ_REG 0 /* index of Read cycle timing register */
24 #define WRITE_REG 1 /* index of Write cycle timing register */
H A Dcs5536.c22 * The IDE timing registers for the CS5536 live in the Geode Machine
127 * cs5536_set_pio_mode - PIO timing setup
175 * cs5536_set_dma_mode - DMA timing setup
H A Dcmd640.c50 * Version 0.05 Major rewrite of interface timing code.
173 * Current cmd640 timing values for each drive.
466 * Set up address setup count and drive read/write timing registers. program_drive_counts()
467 * Primary interface has individual count/timing registers for program_drive_counts()
469 * so we merge the timings, using the slowest value for each timing. program_drive_counts()
589 printk("%s: %sabled cmd640 fast host timing (devsel)\n", cmd640_set_pio_mode()
616 * Reset timing to the slowest speed and turn off prefetch. cmd640_init_dev()
H A Dpmac.c19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
131 * appears to be an evolution of keylargo ATA4 with a timing register
225 * types and instead, built tables based on timing values
413 * timing register when selecting that unit. This version is for
414 * ASICs with a single timing register
430 * timing register when selecting that unit. This version is for
431 * ASICs with a dual timing register (Kauai)
449 * Force an update of controller timing values for a given drive
569 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n", pmac_ide_set_pio_mode()
598 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n", set_timings_udma_ata4()
671 /* Get the proper timing array for this controller */ set_timings_mdma()
773 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n", set_timings_mdma()
817 * Blast some well known "safe" values to the timing registers at init or
1090 * (timing related ?). Until I can put my hand on one of these pmac_ide_setup_device()
H A Dcmd64x.c92 * The primary channel has individual address setup timing registers cmd64x_program_timings()
93 * for each drive and the hardware selects the slowest timing itself. cmd64x_program_timings()
95 * the slowest address setup timing ourselves. cmd64x_program_timings()
H A Dqd65xx.h51 /* Drive specific timing taken from DOS driver v3.7 */
/linux-4.1.27/drivers/video/fbdev/
H A Dgbefb.c40 struct gbe_timing_info timing; member in struct:gbefb_par
420 static void gbefb_setup_flatpanel(struct gbe_timing_info *timing) gbefb_setup_flatpanel() argument
426 (timing->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1); gbefb_setup_flatpanel()
428 (timing->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1); gbefb_setup_flatpanel()
436 timing->pll_m = 4; gbefb_setup_flatpanel()
437 timing->pll_n = 1; gbefb_setup_flatpanel()
438 timing->pll_p = 0; gbefb_setup_flatpanel()
465 struct gbe_timing_info *timing) compute_gbe_timing()
476 /* Determine valid resolution and timing compute_gbe_timing()
512 /* set video timing information */ compute_gbe_timing()
513 if (timing) { compute_gbe_timing()
514 timing->width = var->xres; compute_gbe_timing()
515 timing->height = var->yres; compute_gbe_timing()
516 timing->pll_m = best_m; compute_gbe_timing()
517 timing->pll_n = best_n; compute_gbe_timing()
518 timing->pll_p = best_p; compute_gbe_timing()
519 timing->cfreq = gbe_pll->clock_rate * 1000 * timing->pll_m / compute_gbe_timing()
520 (timing->pll_n << timing->pll_p); compute_gbe_timing()
521 timing->htotal = var->left_margin + var->xres + compute_gbe_timing()
523 timing->vtotal = var->upper_margin + var->yres + compute_gbe_timing()
525 timing->fields_sec = 1000 * timing->cfreq / timing->htotal * compute_gbe_timing()
526 1000 / timing->vtotal; compute_gbe_timing()
527 timing->hblank_start = var->xres; compute_gbe_timing()
528 timing->vblank_start = var->yres; compute_gbe_timing()
529 timing->hblank_end = timing->htotal; compute_gbe_timing()
530 timing->hsync_start = var->xres + var->right_margin + 1; compute_gbe_timing()
531 timing->hsync_end = timing->hsync_start + var->hsync_len; compute_gbe_timing()
532 timing->vblank_end = timing->vtotal; compute_gbe_timing()
533 timing->vsync_start = var->yres + var->lower_margin + 1; compute_gbe_timing()
534 timing->vsync_end = timing->vsync_start + var->vsync_len; compute_gbe_timing()
540 static void gbe_set_timing_info(struct gbe_timing_info *timing) gbe_set_timing_info() argument
547 SET_GBE_FIELD(DOTCLK, M, val, timing->pll_m - 1); gbe_set_timing_info()
548 SET_GBE_FIELD(DOTCLK, N, val, timing->pll_n - 1); gbe_set_timing_info()
549 SET_GBE_FIELD(DOTCLK, P, val, timing->pll_p); gbe_set_timing_info()
556 SET_GBE_FIELD(VT_XYMAX, MAXX, val, timing->htotal); gbe_set_timing_info()
557 SET_GBE_FIELD(VT_XYMAX, MAXY, val, timing->vtotal); gbe_set_timing_info()
560 /* setup video timing signals */ gbe_set_timing_info()
562 SET_GBE_FIELD(VT_VSYNC, VSYNC_ON, val, timing->vsync_start); gbe_set_timing_info()
563 SET_GBE_FIELD(VT_VSYNC, VSYNC_OFF, val, timing->vsync_end); gbe_set_timing_info()
566 SET_GBE_FIELD(VT_HSYNC, HSYNC_ON, val, timing->hsync_start); gbe_set_timing_info()
567 SET_GBE_FIELD(VT_HSYNC, HSYNC_OFF, val, timing->hsync_end); gbe_set_timing_info()
570 SET_GBE_FIELD(VT_VBLANK, VBLANK_ON, val, timing->vblank_start); gbe_set_timing_info()
571 SET_GBE_FIELD(VT_VBLANK, VBLANK_OFF, val, timing->vblank_end); gbe_set_timing_info()
575 timing->hblank_start - 5); gbe_set_timing_info()
577 timing->hblank_end - 3); gbe_set_timing_info()
580 /* setup internal timing signals */ gbe_set_timing_info()
582 SET_GBE_FIELD(VT_VCMAP, VCMAP_ON, val, timing->vblank_start); gbe_set_timing_info()
583 SET_GBE_FIELD(VT_VCMAP, VCMAP_OFF, val, timing->vblank_end); gbe_set_timing_info()
586 SET_GBE_FIELD(VT_HCMAP, HCMAP_ON, val, timing->hblank_start); gbe_set_timing_info()
587 SET_GBE_FIELD(VT_HCMAP, HCMAP_OFF, val, timing->hblank_end); gbe_set_timing_info()
591 temp = timing->vblank_start - timing->vblank_end - 1; gbe_set_timing_info()
596 gbefb_setup_flatpanel(timing); gbe_set_timing_info()
599 if (timing->hblank_end >= 20) gbe_set_timing_info()
601 timing->hblank_end - 20); gbe_set_timing_info()
604 timing->htotal - (20 - timing->hblank_end)); gbe_set_timing_info()
609 if (timing->hblank_end >= GBE_CRS_MAGIC) gbe_set_timing_info()
611 timing->hblank_end - GBE_CRS_MAGIC); gbe_set_timing_info()
614 timing->htotal - (GBE_CRS_MAGIC - gbe_set_timing_info()
615 timing->hblank_end)); gbe_set_timing_info()
620 SET_GBE_FIELD(VC_START_XY, VC_STARTX, val, timing->hblank_end - 4); gbe_set_timing_info()
624 temp = timing->hblank_end - GBE_PIXEN_MAGIC_ON; gbe_set_timing_info()
626 temp += timing->htotal; /* allow blank to wrap around */ gbe_set_timing_info()
630 ((temp + timing->width - gbe_set_timing_info()
631 GBE_PIXEN_MAGIC_OFF) % timing->htotal)); gbe_set_timing_info()
635 SET_GBE_FIELD(VT_VPIXEN, VPIXEN_ON, val, timing->vblank_end); gbe_set_timing_info()
636 SET_GBE_FIELD(VT_VPIXEN, VPIXEN_OFF, val, timing->vblank_start); gbe_set_timing_info()
659 compute_gbe_timing(&info->var, &par->timing); gbefb_set_par()
663 xpmax = par->timing.width; gbefb_set_par()
664 ypmax = par->timing.height; gbefb_set_par()
669 /* set timing info */ gbefb_set_par()
670 gbe_set_timing_info(&par->timing); gbefb_set_par()
912 struct gbe_timing_info timing; gbefb_check_var() local
932 ret = compute_gbe_timing(var, &timing); gbefb_check_var()
994 var->left_margin = timing.htotal - timing.hsync_end; gbefb_check_var()
995 var->right_margin = timing.hsync_start - timing.width; gbefb_check_var()
996 var->upper_margin = timing.vtotal - timing.vsync_end; gbefb_check_var()
997 var->lower_margin = timing.vsync_start - timing.height; gbefb_check_var()
998 var->hsync_len = timing.hsync_end - timing.hsync_start; gbefb_check_var()
999 var->vsync_len = timing.vsync_end - timing.vsync_start; gbefb_check_var()
464 compute_gbe_timing(struct fb_var_screeninfo *var, struct gbe_timing_info *timing) compute_gbe_timing() argument
/linux-4.1.27/drivers/char/
H A Dbfin-otp.c84 * bfin_otp_init_timing - setup OTP timing parameters
90 u32 tp1, tp2, tp3, timing; bfin_otp_init_timing() local
95 timing = tp1 | tp2 | tp3; bfin_otp_init_timing()
96 if (bfrom_OtpCommand(OTP_INIT, timing)) bfin_otp_init_timing()
99 return timing; bfin_otp_init_timing()
107 static void bfin_otp_deinit_timing(u32 timing) bfin_otp_deinit_timing() argument
111 bfrom_OtpCommand(OTP_INIT, timing & ~(-1 << 15)); bfin_otp_deinit_timing()
123 u32 timing, page, base_flags, flags, ret; bfin_otp_write() local
137 timing = bfin_otp_init_timing(); bfin_otp_write()
138 if (timing == 0) { bfin_otp_write()
167 bfin_otp_deinit_timing(timing); bfin_otp_write()
180 u32 timing; bfin_otp_ioctl() local
189 timing = bfin_otp_init_timing(); bfin_otp_ioctl()
190 if (timing) { bfin_otp_ioctl()
196 bfin_otp_deinit_timing(timing); bfin_otp_ioctl()
/linux-4.1.27/drivers/media/rc/img-ir/
H A Dimg-ir-hw.h57 * struct img_ir_timing_range - range of timing values
58 * @min: Minimum timing value
59 * @max: Maximum timing value (if < @min, this will be set to @min during
69 * struct img_ir_symbol_timing - timing data for a symbol
79 * struct img_ir_free_timing - timing data for free time symbol
93 * @ldr: Leader symbol timing data
94 * @s00: Zero symbol timing data for primary decoder
95 * @s01: One symbol timing data for primary decoder
96 * @s10: Zero symbol timing data for secondary (no leader symbol) decoder
97 * @s11: One symbol timing data for secondary (no leader symbol) decoder
98 * @ft: Free time symbol timing data
120 * struct img_ir_timing_regvals - Calculated timing register values.
121 * @ldr: Leader symbol timing register value
122 * @s00: Zero symbol timing register value for primary decoder
123 * @s01: One symbol timing register value for primary decoder
124 * @s10: Zero symbol timing register value for secondary decoder
125 * @s11: One symbol timing register value for secondary decoder
126 * @ft: Free time symbol timing register value
H A Dimg-ir-hw.c81 static void img_ir_symbol_timing_preprocess(struct img_ir_symbol_timing *timing, img_ir_symbol_timing_preprocess() argument
84 img_ir_timing_preprocess(&timing->pulse, unit); img_ir_symbol_timing_preprocess()
85 img_ir_timing_preprocess(&timing->space, unit); img_ir_symbol_timing_preprocess()
113 static void img_ir_symbol_timing_defaults(struct img_ir_symbol_timing *timing, img_ir_symbol_timing_defaults() argument
116 img_ir_timing_defaults(&timing->pulse, &defaults->pulse); img_ir_symbol_timing_defaults()
117 img_ir_timing_defaults(&timing->space, &defaults->space); img_ir_symbol_timing_defaults()
168 * @out: Output timing range in clock cycles with a shift.
169 * @in: Input timing range in microseconds.
198 * img_ir_symbol_timing() - Convert symbol timing struct to register value.
199 * @timing: Symbol timing data
205 * Returns: Symbol timing register value based on arguments.
207 static u32 img_ir_symbol_timing(const struct img_ir_symbol_timing *timing, img_ir_symbol_timing() argument
215 hw_period.min = timing->pulse.min + timing->space.min; img_ir_symbol_timing()
216 hw_period.max = timing->pulse.max + timing->space.max; img_ir_symbol_timing()
219 img_ir_timing_range_convert(&hw_pulse, &timing->pulse, img_ir_symbol_timing()
229 * img_ir_free_timing() - Convert free time timing struct to register value.
230 * @timing: Free symbol timing data
233 * Returns: Free symbol timing register value.
235 static u32 img_ir_free_timing(const struct img_ir_free_timing *timing, img_ir_free_timing() argument
240 if (timing->minlen < 30) img_ir_free_timing()
241 minlen = timing->minlen & -2; img_ir_free_timing()
245 if (timing->maxlen < 48) img_ir_free_timing()
246 maxlen = (timing->maxlen + 1) & -2; img_ir_free_timing()
250 ft_min = (timing->ft_min*clock_hz + 999999) / 1000000; img_ir_free_timing()
289 * @regs: Output timing register values
290 * @timings: Input timing data
318 * Ensures that the symbol timing ranges are valid with respect to ordering, and
345 * Fills out the repeat timings and timing register values for a specific clock
372 * Write timing register values @regs to the hardware, taking into account the
/linux-4.1.27/drivers/video/
H A Ddisplay_timing.c2 * generic display timing functions
H A Dof_display_timing.c47 pr_err("%s: illegal timing specification in %s\n", parse_timing_property()
99 pr_err("%s: error reading timing properties\n", of_parse_display_timing()
109 * @np: device_node with the timing subnode
110 * @name: name of the timing node
166 pr_err("%s: no timing specifications given\n", of_get_display_timings()
171 pr_debug("%s: using %s as default timing\n", of_get_display_timings()
211 pr_err("%s: error in timing %d\n", for_each_child_of_node()
229 pr_debug("%s: got %d timings. Using timing #%d as default\n",
249 * @np: device_node with the timing
H A Dvideomode.c2 * generic display timing functions
/linux-4.1.27/drivers/media/i2c/
H A Dbt819.c73 struct timing { struct
83 static struct timing timing_data[] = {
188 struct timing *timing = &timing_data[(decoder->norm & V4L2_STD_525_60) ? 1 : 0]; bt819_init() local
191 (((timing->vdelay >> 8) & 0x03) << 6) | bt819_init()
192 (((timing->vactive >> 8) & 0x03) << 4) | bt819_init()
193 (((timing->hdelay >> 8) & 0x03) << 2) | bt819_init()
194 ((timing->hactive >> 8) & 0x03); bt819_init()
195 init[0x04 * 2 - 1] = timing->vdelay & 0xff; bt819_init()
196 init[0x05 * 2 - 1] = timing->vactive & 0xff; bt819_init()
197 init[0x06 * 2 - 1] = timing->hdelay & 0xff; bt819_init()
198 init[0x07 * 2 - 1] = timing->hactive & 0xff; bt819_init()
199 init[0x08 * 2 - 1] = timing->hscale >> 8; bt819_init()
200 init[0x09 * 2 - 1] = timing->hscale & 0xff; bt819_init()
251 struct timing *timing = NULL; bt819_s_std() local
266 timing = &timing_data[1]; bt819_s_std()
275 timing = &timing_data[0]; bt819_s_std()
282 (((timing->vdelay >> 8) & 0x03) << 6) | bt819_s_std()
283 (((timing->vactive >> 8) & 0x03) << 4) | bt819_s_std()
284 (((timing->hdelay >> 8) & 0x03) << 2) | bt819_s_std()
285 ((timing->hactive >> 8) & 0x03)); bt819_s_std()
286 bt819_write(decoder, 0x04, timing->vdelay & 0xff); bt819_s_std()
287 bt819_write(decoder, 0x05, timing->vactive & 0xff); bt819_s_std()
288 bt819_write(decoder, 0x06, timing->hdelay & 0xff); bt819_s_std()
289 bt819_write(decoder, 0x07, timing->hactive & 0xff); bt819_s_std()
290 bt819_write(decoder, 0x08, (timing->hscale >> 8) & 0xff); bt819_s_std()
291 bt819_write(decoder, 0x09, timing->hscale & 0xff); bt819_s_std()
H A Dsmiapp-pll.c150 * divisor. Begin with the operational timing and continue to video
151 * timing once operational timing has been verified.
273 * on video timing side. __smiapp_pll_calculate()
/linux-4.1.27/drivers/ata/
H A Dpata_triflex.c74 * triflex_load_timing - timing configuration
88 u32 timing = 0; triflex_load_timing() local
100 timing = 0x0103;break; triflex_load_timing()
102 timing = 0x0203;break; triflex_load_timing()
104 timing = 0x0808;break; triflex_load_timing()
108 timing = 0x0F0F;break; triflex_load_timing()
110 timing = 0x0202;break; triflex_load_timing()
112 timing = 0x0204;break; triflex_load_timing()
114 timing = 0x0404;break; triflex_load_timing()
116 timing = 0x0508;break; triflex_load_timing()
118 timing = 0x0808;break; triflex_load_timing()
123 triflex_timing |= (timing << (16 * is_slave)); triflex_load_timing()
134 * Use the timing loader to set up the PIO mode. We have to do this
147 * Usually drivers set the DMA timing at the point the set_dmamode call
151 * the PIO timing when the DMA is finished.
H A Dpata_at32.c89 * Setup SMC for the given ATA timing.
96 struct smc_timing timing; pata_at32_setup_timing() local
101 memset(&timing, 0, sizeof(struct smc_timing)); pata_at32_setup_timing()
104 timing.read_cycle = ata->cyc8b; pata_at32_setup_timing()
107 timing.nrd_setup = ata->setup; pata_at32_setup_timing()
108 timing.nrd_pulse = ata->act8b; pata_at32_setup_timing()
109 timing.nrd_recover = ata->rec8b; pata_at32_setup_timing()
111 /* Convert nanosecond timing to clock cycles */ pata_at32_setup_timing()
112 smc_set_timing(smc, &timing); pata_at32_setup_timing()
152 struct ata_timing timing; pata_at32_set_piomode() local
157 /* Compute ATA timing */ pata_at32_set_piomode()
158 ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0); pata_at32_set_piomode()
160 dev_warn(ap->dev, "Failed to compute ATA timing %d\n", ret); pata_at32_set_piomode()
164 /* Setup SMC to ATA timing */ pata_at32_set_piomode()
165 ret = pata_at32_setup_timing(ap->dev, info, &timing); pata_at32_set_piomode()
167 dev_warn(ap->dev, "Failed to setup ATA timing %d\n", ret); pata_at32_set_piomode()
319 /* Setup non-timing elements of SMC */ pata_at32_probe()
328 /* Setup SMC to ATA timing */ pata_at32_probe()
H A Dpata_cmd640.c53 struct cmd640_reg *timing = ap->private_data; cmd640_set_piomode() local
67 /* The second channel has shared timings and the setup timing is cmd640_set_piomode()
99 /* Load setup timing */ cmd640_set_piomode()
115 timing->reg58[adev->devno] = (t.active << 4) | t.recover; cmd640_set_piomode()
133 struct cmd640_reg *timing = ap->private_data; cmd640_qc_issue() local
135 if (ap->port_no != 0 && adev->devno != timing->last) { cmd640_qc_issue()
136 pci_write_config_byte(pdev, DRWTIM23, timing->reg58[adev->devno]); cmd640_qc_issue()
137 timing->last = adev->devno; cmd640_qc_issue()
153 struct cmd640_reg *timing; cmd640_port_start() local
155 timing = devm_kzalloc(&pdev->dev, sizeof(struct cmd640_reg), GFP_KERNEL); cmd640_port_start()
156 if (timing == NULL) cmd640_port_start()
158 timing->last = -1; /* Force a load */ cmd640_port_start()
159 ap->private_data = timing; cmd640_port_start()
H A Dpata_cs5530.c68 /* Now load the right timing register */ cs5530_set_piomode()
76 * cs5530_set_dmamode - DMA timing setup
88 u32 tuning, timing = 0; cs5530_set_dmamode() local
96 timing = 0x00921250;break; cs5530_set_dmamode()
98 timing = 0x00911140;break; cs5530_set_dmamode()
100 timing = 0x00911030;break; cs5530_set_dmamode()
102 timing = 0x00077771;break; cs5530_set_dmamode()
104 timing = 0x00012121;break; cs5530_set_dmamode()
106 timing = 0x00002020;break; cs5530_set_dmamode()
111 timing |= (tuning & 0x80000000UL); cs5530_set_dmamode()
113 iowrite32(timing, base + 0x04); cs5530_set_dmamode()
115 if (timing & 0x00100000) cs5530_set_dmamode()
120 iowrite32(timing, base + 0x0C); cs5530_set_dmamode()
H A Dpata_legacy.c99 unsigned long timing; member in struct:legacy_data
366 /* Get the timing data in cycles. For now play safe at 50Mhz */ ht6560a_set_piomode()
400 /* Get the timing data in cycles. For now play safe at 50Mhz */ ht6560b_set_piomode()
476 /* Get the timing data in cycles */ opti82c611a_set_piomode()
479 /* Setup timing is shared */ opti82c611a_set_piomode()
491 /* Select the right timing bank for write timing */ opti82c611a_set_piomode()
511 /* Ensure the timing register mode is right */ opti82c611a_set_piomode()
555 /* Get the timing data in cycles */ opti82c46x_set_piomode()
558 /* Setup timing is shared */ opti82c46x_set_piomode()
570 /* Select the right timing bank for write timing */ opti82c46x_set_piomode()
590 /* Ensure the timing register mode is right */ opti82c46x_set_piomode()
609 * MVB has a single set of timing registers and these are shared
644 * avoid the requirement to clock switch. We also have to load the timing
656 u8 timing; qdi65x0_set_piomode() local
658 /* Get the timing data in cycles */ qdi65x0_set_piomode()
668 timing = (recovery << 4) | active | 0x08; qdi65x0_set_piomode()
669 ld_qdi->clock[adev->devno] = timing; qdi65x0_set_piomode()
672 outb(timing, ld_qdi->timing + 2 * adev->devno); qdi65x0_set_piomode()
674 outb(timing, ld_qdi->timing + 2 * ap->port_no); qdi65x0_set_piomode()
678 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3); qdi65x0_set_piomode()
698 outb(ld_qdi->clock[adev->devno], ld_qdi->timing + qdi_qc_issue()
738 ld->timing = lp->private; qdi_port()
792 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); winbond_set_piomode() local
794 reg = winbond_readcfg(ld_winbond->timing, 0x81); winbond_set_piomode()
796 /* Get the timing data in cycles */ winbond_set_piomode()
804 timing = (active << 4) | recovery; winbond_set_piomode()
805 winbond_writecfg(ld_winbond->timing, timing, reg); winbond_set_piomode()
807 /* Load the setup timing */ winbond_set_piomode()
815 winbond_writecfg(ld_winbond->timing, timing + 1, reg); winbond_set_piomode()
823 ld->timing = lp->private; winbond_port()
881 reg |= 0xF0; /* programmable timing */ probe_chip_type()
H A Dpata_sl82c105.c16 * timing parameters.
67 * sl82c105_configure_piomode - set chip PIO timing
72 * Called to do the PIO mode setup. Our timing registers are shared
84 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); sl82c105_configure_piomode() local
86 pci_write_config_word(pdev, timing, pio_timing[pio]); sl82c105_configure_piomode()
88 pci_read_config_word(pdev, timing, &dummy); sl82c105_configure_piomode()
96 * Called to do the PIO mode setup. Our timing registers are shared
97 * but we want to set the PIO timing by default.
121 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); sl82c105_configure_dmamode() local
124 pci_write_config_word(pdev, timing, dma_timing[dma]); sl82c105_configure_dmamode()
126 pci_read_config_word(pdev, timing, &dummy); sl82c105_configure_dmamode()
H A Dpata_oldpiix.c9 * SITRE and the slave timing registers. This means that you have to
10 * set timing per channel, or be clever. Libata tells us whenever it
72 * See Intel Document 298600-004 for the timing programing rules oldpiix_set_piomode()
74 * timing port at 0x44. oldpiix_set_piomode()
97 * Clear the other drive's timing bits. oldpiix_set_piomode()
141 * been set when the PIO timing was set. oldpiix_set_dmamode()
162 /* Enable DMA timing only */ oldpiix_set_dmamode()
165 /* Mask out the relevant control and timing bits we will load. Also oldpiix_set_dmamode()
H A Dpata_sis.c314 t1 &= 0xC0C00FFF; /* Mask out timing */ sis_133_set_piomode()
341 u16 timing; sis_old_set_dmamode() local
346 pci_read_config_word(pdev, drive_pci, &timing); sis_old_set_dmamode()
349 /* bits 3-0 hold recovery timing bits 8-10 active timing and sis_old_set_dmamode()
351 timing &= ~0x870F; sis_old_set_dmamode()
352 timing |= mwdma_bits[speed]; sis_old_set_dmamode()
356 timing &= ~0x6000; sis_old_set_dmamode()
357 timing |= udma_bits[speed]; sis_old_set_dmamode()
359 pci_write_config_word(pdev, drive_pci, timing); sis_old_set_dmamode()
380 u16 timing; sis_66_set_dmamode() local
386 pci_read_config_word(pdev, drive_pci, &timing); sis_66_set_dmamode()
389 /* bits 3-0 hold recovery timing bits 8-10 active timing and sis_66_set_dmamode()
391 timing &= ~0x870F; sis_66_set_dmamode()
392 timing |= mwdma_bits[speed]; sis_66_set_dmamode()
396 timing &= ~0xF000; sis_66_set_dmamode()
397 timing |= udma_bits[speed]; sis_66_set_dmamode()
399 pci_write_config_word(pdev, drive_pci, timing); sis_66_set_dmamode()
419 u8 timing; sis_100_set_dmamode() local
423 pci_read_config_byte(pdev, drive_pci + 1, &timing); sis_100_set_dmamode()
430 timing &= ~0x8F; sis_100_set_dmamode()
431 timing |= udma_bits[speed]; sis_100_set_dmamode()
433 pci_write_config_byte(pdev, drive_pci + 1, timing); sis_100_set_dmamode()
453 u8 timing; sis_133_early_set_dmamode() local
454 /* Low 4 bits are timing */ sis_133_early_set_dmamode()
457 pci_read_config_byte(pdev, drive_pci + 1, &timing); sis_133_early_set_dmamode()
464 timing &= ~0x8F; sis_133_early_set_dmamode()
465 timing |= udma_bits[speed]; sis_133_early_set_dmamode()
467 pci_write_config_byte(pdev, drive_pci + 1, timing); sis_133_early_set_dmamode()
H A Dpata_it8213.c4 * The IT8213 is a very Intel ICH like device for timing purposes, having
83 * See Intel Document 298600-004 for the timing programing rules it8213_set_piomode()
116 /* Slave timing in separate register */ it8213_set_piomode()
189 * been set when the PIO timing was set. it8213_set_dmamode()
205 /* Enable DMA timing only */ it8213_set_dmamode()
213 /* Load the matching timing */ it8213_set_dmamode()
218 and master timing bits */ it8213_set_dmamode()
H A Dpata_ninja32.c9 * timing parameters.
34 * Base + 0x1F timing register
54 * Called to do the PIO mode setup. Our timing registers are shared
55 * but we want to set the PIO timing by default.
H A Dpata_artop.c33 * The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
102 const u16 timing[2][5] = { artop6210_load_piomode() local
107 /* Load the PIO timing active/recovery bits */ artop6210_load_piomode()
108 pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]); artop6210_load_piomode()
146 * ARTOP6260 and relatives store the timing data differently.
156 const u8 timing[2][5] = { artop6260_load_piomode() local
161 /* Load the PIO timing active/recovery bits */ artop6260_load_piomode()
162 pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]); artop6260_load_piomode()
215 /* Load the PIO timing active/recovery bits */ artop6210_set_dmamode()
237 * ARTOP6260 and relatives store the timing data differently.
254 /* Load the PIO timing active/recovery bits */ artop6260_set_dmamode()
H A Dpata_efar.c94 * See Intel Document 298600-004 for the timing programing rules efar_set_piomode()
130 /* Slave timing in separate register */ efar_set_piomode()
194 * been set when the PIO timing was set. efar_set_dmamode()
210 /* Enable DMA timing only */ efar_set_dmamode()
218 /* Load the matching timing */ efar_set_dmamode()
223 and master timing bits */ efar_set_dmamode()
H A Dpata_at91.c265 struct ata_timing timing; pata_at91_set_piomode() local
268 /* Compute ATA timing and set it to SMC */ pata_at91_set_piomode()
269 ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0); pata_at91_set_piomode()
271 dev_warn(ap->dev, "Failed to compute ATA timing %d, " pata_at91_set_piomode()
272 "set PIO_0 timing\n", ret); pata_at91_set_piomode()
273 timing = *ata_timing_find_mode(XFER_PIO_0); pata_at91_set_piomode()
275 set_smc_timing(ap->dev, adev, info, &timing); pata_at91_set_piomode()
H A Dpata_ns87415.c7 * as it requires timing reloads on PIO/DMA transitions but it is otherwise
21 * 8bit shared timing.
56 int timing = 0x44 + 2 * unit; ns87415_set_mode() local
63 /* Timing register format is 17 - low nybble read timing with ns87415_set_mode()
70 /* Use the same timing for read and write bytes */ ns87415_set_mode()
72 pci_write_config_word(dev, timing, clocking); ns87415_set_mode()
92 /* TODO: Set byte 54 command timing to the best 8bit ns87415_set_mode()
H A Dpata_octeon_cf.c72 * boot bus timing register, based on timing multiple
124 * timing requirements of the PIO mode.
134 struct ata_timing timing; octeon_cf_set_piomode() local
140 /* These names are timing parameters from the ATA spec */ octeon_cf_set_piomode()
146 * A divisor value of four will overflow the timing fields at octeon_cf_set_piomode()
155 if (ata_timing_compute(dev, dev->pio_mode, &timing, T, T)) octeon_cf_set_piomode()
158 t1 = timing.setup; octeon_cf_set_piomode()
161 t2 = timing.active; octeon_cf_set_piomode()
164 t2i = timing.act8b; octeon_cf_set_piomode()
172 pause = (int)timing.cycle - (int)timing.active - octeon_cf_set_piomode()
173 (int)timing.setup - trh; octeon_cf_set_piomode()
190 /* Enable dynamic timing */ octeon_cf_set_piomode()
215 /* Program the bootbus region timing for the data port chip select. */ octeon_cf_set_piomode()
237 const struct ata_timing *timing; octeon_cf_set_dmamode() local
239 timing = ata_timing_find_mode(dev->dma_mode); octeon_cf_set_dmamode()
240 T0 = timing->cycle; octeon_cf_set_dmamode()
241 Td = timing->active; octeon_cf_set_dmamode()
242 Tkr = timing->recover; octeon_cf_set_dmamode()
243 dma_ackh = timing->dmack_hold; octeon_cf_set_dmamode()
H A Dpata_mpc52xx.c271 struct mpc52xx_ata_timings *timing = &priv->timings[dev]; mpc52xx_ata_compute_pio_timings() local
286 timing->pio1 = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8) | (t2i); mpc52xx_ata_compute_pio_timings()
287 timing->pio2 = (t4 << 24) | (t1 << 16) | (ta << 8); mpc52xx_ata_compute_pio_timings()
333 struct mpc52xx_ata_timings *timing = &priv->timings[device]; mpc52xx_ata_apply_timings() local
335 out_be32(&regs->pio1, timing->pio1); mpc52xx_ata_apply_timings()
336 out_be32(&regs->pio2, timing->pio2); mpc52xx_ata_apply_timings()
337 out_be32(&regs->mdma1, timing->mdma1); mpc52xx_ata_apply_timings()
338 out_be32(&regs->mdma2, timing->mdma2); mpc52xx_ata_apply_timings()
339 out_be32(&regs->udma1, timing->udma1); mpc52xx_ata_apply_timings()
340 out_be32(&regs->udma2, timing->udma2); mpc52xx_ata_apply_timings()
341 out_be32(&regs->udma3, timing->udma3); mpc52xx_ata_apply_timings()
342 out_be32(&regs->udma4, timing->udma4); mpc52xx_ata_apply_timings()
343 out_be32(&regs->udma5, timing->udma5); mpc52xx_ata_apply_timings()
H A Dpata_cs5535.c111 /* Command timing has to be for the lowest of the pair of devices */ cs5535_set_piomode()
115 /* Write the other drive timing register if it changed */ cs5535_set_piomode()
120 /* Write the drive timing register */ cs5535_set_piomode()
124 /* Set the PIO "format 1" bit in the DMA timing register */ cs5535_set_piomode()
130 * cs5535_set_dmamode - DMA timing setup
H A Dpata_radisys.c47 * See Intel Document 298600-004 for the timing programing rules radisys_set_piomode()
49 * timing port at 0x44. The Radisys is a relative of the PIIX radisys_set_piomode()
68 drive timing bits */ radisys_set_piomode()
125 /* Mask out the relevant control and timing bits we will load. Also radisys_set_dmamode()
173 /* UDMA timing is not shared */ radisys_qc_issue()
H A Dpata_hpt366.c32 u32 timing; member in struct:hpt_clock
114 * hpt36x_find_mode - find the hpt36x timing
128 return clocks->timing; hpt36x_find_mode()
238 /* determine timing mask and find matching clock entry */ hpt366_set_mode()
272 * hpt366_set_dmamode - DMA timing setup
372 /* PCI clocking determines the ATA timing values to use */ hpt36x_init_one()
H A Dpata_rdc.c139 /* Enable SITRE (separate slave timing register) */ rdc_set_piomode()
145 /* Load the timing nibble for this slave */ rdc_set_piomode()
243 * been set when the PIO timing was set. rdc_set_dmamode()
259 /* Enable DMA timing only */ rdc_set_dmamode()
267 /* Load the matching timing */ rdc_set_dmamode()
272 and master timing bits */ rdc_set_dmamode()
H A Dpata_hpt37x.c32 u32 timing; member in struct:hpt_clock
216 return clocks->timing; hpt37x_find_mode()
415 u32 reg, timing, mask; hpt370_set_mode() local
427 /* Determine timing mask and find matching mode entry */ hpt370_set_mode()
435 timing = hpt37x_find_mode(ap, mode); hpt370_set_mode()
438 reg = (reg & ~mask) | (timing & mask); hpt370_set_mode()
455 * hpt370_set_dmamode - DMA timing setup
509 u32 reg, timing, mask; hpt372_set_mode() local
520 /* Determine timing mask and find matching mode entry */ hpt372_set_mode()
528 timing = hpt37x_find_mode(ap, mode); hpt372_set_mode()
531 reg = (reg & ~mask) | (timing & mask); hpt372_set_mode()
549 * hpt372_set_dmamode - DMA timing setup
649 * hpt37x_clock_slot - Turn timing to PC clock entry
650 * @freq: Reported frequency timing
651 * @base: Base timing
653 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
956 pr_warn("BIOS has not set timing clocks\n"); hpt37x_init_one()
969 * Turn the frequency check into a band and then find a timing hpt37x_init_one()
H A Dpata_hpt3x2n.c39 u32 timing; member in struct:hpt_clock
109 return clocks->timing; hpt3x2n_find_mode()
186 u32 reg, timing, mask; hpt3x2n_set_mode() local
197 /* Determine timing mask and find matching mode entry */ hpt3x2n_set_mode()
205 timing = hpt3x2n_find_mode(ap, mode); hpt3x2n_set_mode()
208 reg = (reg & ~mask) | (timing & mask); hpt3x2n_set_mode()
226 * hpt3x2n_set_dmamode - DMA timing setup
596 * the MISC. register to stretch the UltraDMA Tss timing. hpt3x2n_init_one()
H A Dpata_it821x.c48 * timing and policy set up. Each HDD in raid mode also has a serial
92 The high byte is the 66Mhz timing */
119 * @timing: Timing value (66Mhz in top 8bits, 50 in the low 8)
121 * Program the PIO/MWDMA timing for this channel according to the
126 static void it821x_program(struct ata_port *ap, struct ata_device *adev, u16 timing) it821x_program() argument
133 /* Program PIO/MWDMA timing bits */ it821x_program()
135 conf = timing >> 8; it821x_program()
137 conf = timing & 0xFF; it821x_program()
146 * @timing: Timing bits. Top 8 are for 66Mhz bottom for 50Mhz
148 * Program the UDMA timing for this drive according to the
154 static void it821x_program_udma(struct ata_port *ap, struct ata_device *adev, u16 timing) it821x_program_udma() argument
162 /* Program UDMA timing bits */ it821x_program_udma()
164 conf = timing >> 8; it821x_program_udma()
166 conf = timing & 0xFF; it821x_program_udma()
280 * timing register is private and we need only consider the clock. If
340 * Usually drivers set the DMA timing at the point the set_dmamode call
406 * perform out own device selection timing loads before the
443 * perform out own device selection timing loads before the
H A Data_generic.c115 * devices. IDE-R devices have no timing registers and are in
120 * it non zero. All Intel ATA has 0x40 writable (timing), but it is
137 but they will have a sane timing register */ is_intel_ider()
141 /* Finally check if the timing register is writable so that is_intel_ider()
H A Dpata_mpiix.c69 * This would get very ugly because we can only program timing for one
96 control |= FTIM; /* This drive is on the fast timing bank */ mpiix_set_piomode()
98 /* Mask out timing and clear both TIME bank selects */ mpiix_set_piomode()
107 loaded for timing */ mpiix_set_piomode()
H A Dpata_optidma.c6 * and indeed the VLB ones. The main differences are that the timing
37 READ_REG = 0, /* index of Read cycle timing register */
38 WRITE_REG = 1, /* index of Write cycle timing register */
164 /* First we load the device number into the timing select */ optidma_mode_setup()
177 /* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */ optidma_mode_setup()
383 /* Check the ATA arbitration/timing is suitable */ optiplus_with_udma()
H A Dpata_ali.c161 * @adev: Device the timing is for
162 * @t: timing data
163 * @ultra: UDMA timing or zero for off
165 * Loads the timing registers for cmd/data and disable UDMA if
167 * timing but do not touch the command/data timing.
173 int cas = 0x58 + 4 * ap->port_no; /* Command timing */ ali_program_modes()
174 int cbt = 0x59 + 4 * ap->port_no; /* Command timing */ ali_program_modes()
175 int drwt = 0x5A + 4 * ap->port_no + adev->devno; /* R/W timing */ ali_program_modes()
176 int udmat = 0x56 + ap->port_no; /* UDMA timing */ ali_program_modes()
H A Dpata_via.c237 * Program the VIA registers for DMA and PIO modes. Uses the ata timing
265 /* Calculate the timing values we require */ via_do_set_mode()
268 /* We share 8bit timing so we must merge the constraints */ via_do_set_mode()
513 u32 timing; via_fixup() local
520 pci_read_config_dword(pdev, 0x50, &timing); via_fixup()
521 timing |= 0x80008; via_fixup()
522 pci_write_config_dword(pdev, 0x50, timing); via_fixup()
526 pci_read_config_dword(pdev, 0x50, &timing); via_fixup()
527 timing &= ~0x80008; via_fixup()
528 pci_write_config_dword(pdev, 0x50, timing); via_fixup()
H A Dpata_cmd64x.c85 * cmd64x_set_timing - set PIO and MWDMA timing
158 /* Load setup timing */ cmd64x_set_timing()
210 /* DMA timing bits */ cmd64x_set_dmamode()
214 /* Merge the timing value */ cmd64x_set_dmamode()
218 if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */ cmd64x_set_dmamode()
H A Dpata_amd.c29 * timing_setup - shared timing computation and load
36 * Perform the actual timing set up for Nvidia or AMD PATA devices.
83 /* Configure the address set up timing */ timing_setup()
88 /* Configure the 8bit I/O timing */ timing_setup()
92 /* Drive timing */ timing_setup()
117 /* UDMA timing */ timing_setup()
H A Dpata_ns87410.c59 * Program timing data. This is kept per channel not per device,
101 loaded for timing */ ns87410_set_piomode()
H A Dpata_opti.c38 READ_REG = 0, /* index of Read cycle timing register */
39 WRITE_REG = 1, /* index of Write cycle timing register */
H A Dpata_pdc202xx_old.c68 * pdc202xx_configure_piomode - set chip PIO timing
73 * Called to do the PIO mode setup. Our timing registers are shared
107 * Called to do the PIO mode setup. Our timing registers are shared
108 * but we want to set the PIO timing by default.
H A Dpata_atiixp.c98 * timing values into the controller.
128 * as the DMA setup must also adjust the PIO timing information.
144 * Called to do the DMA mode setup. We use timing tables for most
H A Dpata_cs5520.c76 /* Channel command timing */ cs5520_set_timings()
81 /* Read command timing */ cs5520_set_timings()
85 /* Write command timing */ cs5520_set_timings()
H A Dpata_hpt3x3.c45 /* Load the PIO timing number */ hpt3x3_set_piomode()
56 * hpt3x3_set_dmamode - DMA timing setup
76 /* Load the timing number */ hpt3x3_set_dmamode()
H A Dpata_pdc2027x.c81 * set the timing registers automatically when "set feature" command
310 /* Set the PIO timing registers using value table for 133MHz */ pdc2027x_set_piomode()
346 /* Set the UDMA timing registers with value table for 133MHz */ pdc2027x_set_dmamode()
374 /* Set the MDMA timing registers with value table for 133MHz */ pdc2027x_set_dmamode()
394 * pdc2027x_set_mode - Set the timing registers back to correct values.
398 * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
660 * The pdc20275 controller employs PLL circuit to help correct timing registers setting. pdc_hardware_init()
H A Dpata_bf54x.c190 * Register transfer timing table
201 * PIO timing table
216 * Multiword DMA timing table
238 * Ultra DMA timing table
261 * calculate number of SCLK cycles to meet minimum timing
298 /* the most restrictive timing value is t6 and tc, the DIOW - data hold bfin_set_piomode()
305 /* calculate the timing values for register transfers. */ bfin_set_piomode()
320 /* calculate the timing values for pio transfers. */ bfin_set_piomode()
381 /* the most restrictive timing value is t6 and tc, bfin_set_dmamode()
391 /* calculate the timing values for Ultra DMA. */ bfin_set_dmamode()
402 /* Mow assign the values required for the timing bfin_set_dmamode()
430 /* the most restrictive timing value is tf, the DMACK to bfin_set_dmamode()
440 /* calculate the timing values for Multi-word DMA. */ bfin_set_dmamode()
/linux-4.1.27/include/linux/mfd/syscon/
H A Datmel-smc.h74 * This function converts a setup timing expressed in nanoseconds into an
82 * where setup length is the timing expressed in cycles.
104 * This function converts a pulse timing expressed in nanoseconds into an
112 * where pulse length is the timing expressed in cycles.
134 * This function converts a cycle timing expressed in nanoseconds into an
142 * where cycle length is the timing expressed in cycles.
/linux-4.1.27/drivers/mmc/host/
H A Ddw_mmc-exynos.c130 static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) dw_mci_exynos_set_clksel_timing() argument
141 clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing; dw_mci_exynos_set_clksel_timing()
225 static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing) dw_mci_exynos_config_hs400() argument
240 if (timing == MMC_TIMING_MMC_HS400) { dw_mci_exynos_config_hs400()
287 u32 timing = ios->timing, clksel; dw_mci_exynos_set_ios() local
289 switch (timing) { dw_mci_exynos_set_ios()
291 /* Update tuned sample timing */ dw_mci_exynos_set_ios()
306 /* Set clock timing for the requested speed mode*/ dw_mci_exynos_set_ios()
310 dw_mci_exynos_config_hs400(host, timing); dw_mci_exynos_set_ios()
320 u32 timing[2]; dw_mci_exynos_parse_dt() local
344 "samsung,dw-mshc-sdr-timing", timing, 2); dw_mci_exynos_parse_dt()
348 priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); dw_mci_exynos_parse_dt()
351 "samsung,dw-mshc-ddr-timing", timing, 2); dw_mci_exynos_parse_dt()
355 priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); dw_mci_exynos_parse_dt()
358 "samsung,dw-mshc-hs400-timing", timing, 2); dw_mci_exynos_parse_dt()
364 priv->hs400_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], dw_mci_exynos_parse_dt()
H A Dsdhci.c1151 switch (host->timing) { sdhci_get_preset_value()
1472 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) sdhci_set_uhs_signaling() argument
1479 if ((timing == MMC_TIMING_MMC_HS200) || sdhci_set_uhs_signaling()
1480 (timing == MMC_TIMING_UHS_SDR104)) sdhci_set_uhs_signaling()
1482 else if (timing == MMC_TIMING_UHS_SDR12) sdhci_set_uhs_signaling()
1484 else if (timing == MMC_TIMING_UHS_SDR25) sdhci_set_uhs_signaling()
1486 else if (timing == MMC_TIMING_UHS_SDR50) sdhci_set_uhs_signaling()
1488 else if ((timing == MMC_TIMING_UHS_DDR50) || sdhci_set_uhs_signaling()
1489 (timing == MMC_TIMING_MMC_DDR52)) sdhci_set_uhs_signaling()
1491 else if (timing == MMC_TIMING_MMC_HS400) sdhci_set_uhs_signaling()
1553 if ((ios->timing == MMC_TIMING_SD_HS || sdhci_do_set_ios()
1554 ios->timing == MMC_TIMING_MMC_HS) sdhci_do_set_ios()
1564 if ((ios->timing == MMC_TIMING_MMC_HS400) || sdhci_do_set_ios()
1565 (ios->timing == MMC_TIMING_MMC_HS200) || sdhci_do_set_ios()
1566 (ios->timing == MMC_TIMING_MMC_DDR52) || sdhci_do_set_ios()
1567 (ios->timing == MMC_TIMING_UHS_SDR50) || sdhci_do_set_ios()
1568 (ios->timing == MMC_TIMING_UHS_SDR104) || sdhci_do_set_ios()
1569 (ios->timing == MMC_TIMING_UHS_DDR50) || sdhci_do_set_ios()
1570 (ios->timing == MMC_TIMING_UHS_SDR25)) sdhci_do_set_ios()
1611 host->ops->set_uhs_signaling(host, ios->timing); sdhci_do_set_ios()
1612 host->timing = ios->timing; sdhci_do_set_ios()
1615 ((ios->timing == MMC_TIMING_UHS_SDR12) || sdhci_do_set_ios()
1616 (ios->timing == MMC_TIMING_UHS_SDR25) || sdhci_do_set_ios()
1617 (ios->timing == MMC_TIMING_UHS_SDR50) || sdhci_do_set_ios()
1618 (ios->timing == MMC_TIMING_UHS_SDR104) || sdhci_do_set_ios()
1619 (ios->timing == MMC_TIMING_UHS_DDR50) || sdhci_do_set_ios()
1620 (ios->timing == MMC_TIMING_MMC_DDR52))) { sdhci_do_set_ios()
1936 switch (host->timing) { sdhci_execute_tuning()
H A Ddw_mmc-rockchip.c54 ios->timing == MMC_TIMING_MMC_DDR52) dw_mci_rk3288_set_ios()
H A Dsdhci-msm.c151 * timing mode) or for eMMC4.5 card read operation (in HS200
152 * timing mode).
359 !((ios.timing == MMC_TIMING_MMC_HS200) || sdhci_msm_execute_tuning()
360 (ios.timing == MMC_TIMING_UHS_SDR104))) sdhci_msm_execute_tuning()
/linux-4.1.27/include/video/
H A Dvideomode.h36 * videomode_from_timing - convert display timing to videomode
48 * @disp: structure with all possible timing entries
H A Ddisplay_timing.h77 * This describes all timing settings a display provides.
/linux-4.1.27/drivers/gpu/drm/rcar-du/
H A Drcar_du_lvdscon.c94 struct display_timing timing; rcar_du_lvds_connector_init() local
101 ret = of_get_display_timing(np, "panel-timing", &timing); rcar_du_lvds_connector_init()
105 videomode_from_timing(&timing, &lvdscon->panel.mode); rcar_du_lvds_connector_init()
/linux-4.1.27/drivers/cpufreq/
H A Dcris-etraxfs-cpufreq.c80 reg_bif_core_rw_sdram_timing timing = cris_sdram_freq_notifier() local
82 timing.cpd = (freqs->new == 200000 ? 0 : 1); cris_sdram_freq_notifier()
86 REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing); cris_sdram_freq_notifier()
H A Dcris-artpec3-cpufreq.c86 REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing); cris_sdram_freq_notifier()
H A Ds3c24xx-cpufreq-debugfs.c135 seq_printf(seq, "no code to show bank timing\n"); io_show()
185 dbgfs_file_io = debugfs_create_file("io-timing", S_IRUGO, dbgfs_root, s3c_freq_debugfs_init()
/linux-4.1.27/drivers/video/backlight/
H A Dtdo24m.c95 CMD1(0xd1, 0x01), /* CKV timing control on/off */
96 CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
97 CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
98 CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */
99 CMD1(0xd5, 0x14), /* ASW timing control (2) */
108 CMD1(0xd8, 0x01), /* CKV timing control on/off */
109 CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */
110 CMD2(0xde, 0x05, 0x0a), /* OEV timing control */
111 CMD2(0xdf, 0x0a, 0x19), /* ASW timing control (1) */
112 CMD1(0xe0, 0x0a), /* ASW timing control (2) */
137 CMD1(0xd1, 0x01), /* CKV timing control on/off */
138 CMD2(0xd2, 0x00, 0x1e), /* CKV 1,2 timing control */
139 CMD2(0xd3, 0x14, 0x28), /* OEV timing control */
140 CMD2(0xd4, 0x28, 0x64), /* ASW timing control (1) */
141 CMD1(0xd5, 0x28), /* ASW timing control (2) */
/linux-4.1.27/arch/arm/mach-s3c24xx/
H A Diotiming-s3c2410.c6 * S3C24XX CPU Frequency scaling - IO timing for S3C2410/S3C2440/S3C2442
31 * s3c2410_print_timing - print bank timing data for debug purposes
33 * @timings: The timing inforamtion to print.
209 * s3c2410_calc_bank - calculate bank timing infromation
211 * @bt: The bank timing information.
214 * setting for the @cfg timing. This updates the timing information
266 * @val: The bank timing register value, shifed down.
278 * @val: The bank timing register value, shifed down.
290 * @bt: The bank timing to fill in (uses cached BANKCON)
293 * in @cfg, update the cycle timing information.
309 * s3c2410_iotiming_debugfs - debugfs show io bank timing information
353 * s3c2410_iotiming_calc - Calculate bank timing for frequency change.
355 * @iot: The IO timing information to fill out.
359 * to update the timing when necessary.
397 * @iot: The IO timing information to use.
399 * Set all the currently used IO bank timing information generated
421 * s3c2410_iotiming_get - Get the timing information from current registers.
423 * @timings: The IO timing information to fill out.
425 * Calculate the @timings timing information from the current frequency
H A Diotiming-s3c2412.c6 * S3C2412/S3C2443 (PL093 based) IO timing support
38 * s3c2412_print_timing - print timing infromation via printk.
40 * @iot: The IO timing information
74 * calc_timing - calculate timing divisor value and check in range.
75 * @hwtm: The hardware timing in 10ths of nanoseconds.
93 * @bt: The bank timing.
112 * s3c2412_iotiming_debugfs - debugfs show io bank timing information
137 * @iot: The bank timing information.
139 * Calculate the timing information for all the banks that are
168 * s3c2412_iotiming_set - set the timing information
170 * @iot: The bank timing information.
H A Dmach-mini2440.c107 /* LCD timing and setup */
136 240, 21, 38, 6, /* x timing */
137 320, 4, 4, 2, /* y timing */
148 800, 40, 40, 48, /* x timing */
149 480, 29, 3, 3, /* y timing */
165 1024, 1, 2, 2, /* y timing */
166 768, 200, 16, 16, /* x timing */
/linux-4.1.27/drivers/pcmcia/
H A Dsa11xx_base.c81 struct soc_pcmcia_timing timing; sa1100_pcmcia_set_mecr() local
86 soc_common_pcmcia_get_timing(skt, &timing); sa1100_pcmcia_set_mecr()
88 bs_io = skt->ops->get_timing(skt, cpu_clock, timing.io); sa1100_pcmcia_set_mecr()
89 bs_mem = skt->ops->get_timing(skt, cpu_clock, timing.mem); sa1100_pcmcia_set_mecr()
90 bs_attr = skt->ops->get_timing(skt, cpu_clock, timing.attr); sa1100_pcmcia_set_mecr()
146 struct soc_pcmcia_timing timing; sa1100_pcmcia_show_timing() local
151 soc_common_pcmcia_get_timing(skt, &timing); sa1100_pcmcia_show_timing()
153 p+=sprintf(p, "I/O : %u (%u)\n", timing.io, sa1100_pcmcia_show_timing()
156 p+=sprintf(p, "attribute: %u (%u)\n", timing.attr, sa1100_pcmcia_show_timing()
159 p+=sprintf(p, "common : %u (%u)\n", timing.mem, sa1100_pcmcia_show_timing()
208 /* Provide our SA11x0 specific timing routines. */ sa11xx_drv_pcmcia_ops()
H A Dpxa2xx_base.c167 struct soc_pcmcia_timing timing; pxa2xx_pcmcia_set_mcxx() local
170 soc_common_pcmcia_get_timing(skt, &timing); pxa2xx_pcmcia_set_mcxx()
172 pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk); pxa2xx_pcmcia_set_mcxx()
173 pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk); pxa2xx_pcmcia_set_mcxx()
174 pxa2xx_pcmcia_set_mcio(sock, timing.io, clk); pxa2xx_pcmcia_set_mcxx()
271 /* Provide our PXA2xx specific timing routines. */ pxa2xx_drv_pcmcia_ops()
H A Dcistpl.c946 static u_char *parse_timing(u_char *p, u_char *q, cistpl_timing_t *timing) parse_timing() argument
956 timing->wait = SPEED_CVT(*p); parse_timing()
957 timing->waitscale = exponent[scale & 3]; parse_timing()
959 timing->wait = 0; parse_timing()
964 timing->ready = SPEED_CVT(*p); parse_timing()
965 timing->rdyscale = exponent[scale & 7]; parse_timing()
967 timing->ready = 0; parse_timing()
972 timing->reserved = SPEED_CVT(*p); parse_timing()
973 timing->rsvscale = exponent[scale]; parse_timing()
975 timing->reserved = 0; parse_timing()
1134 p = parse_timing(p, q, &entry->timing); parse_cftable_entry()
1138 entry->timing.wait = 0; parse_cftable_entry()
1139 entry->timing.ready = 0; parse_cftable_entry()
1140 entry->timing.reserved = 0; parse_cftable_entry()
H A Dsoc_common.h112 * Hardware specific timing routines.
159 * common and attribute memory write timing) says that twWE has a
/linux-4.1.27/arch/arm/mach-davinci/
H A Daemif.c59 * aemif_calc_rate - calculate timing data.
64 * On success, returns the calculated timing value minus 1 for easy
65 * programming into AEMIF timing registers, else negative errno.
75 /* It is generally OK to have a more relaxed timing than requested... */ aemif_calc_rate()
87 * davinci_aemif_setup_timing - setup timing values for a given AEMIF interface
88 * @t: timing values to be progammed
90 * @cs: chip-select to program the timing values for
93 * This function programs the given timing values (in real clock) into the
205 if (pdata->timing) davinci_aemif_setup()
206 ret = davinci_aemif_setup_timing(pdata->timing, base, pdev->id, davinci_aemif_setup()
210 dev_dbg(&pdev->dev, "NAND timing values setup fail\n"); davinci_aemif_setup()
/linux-4.1.27/drivers/iio/humidity/
H A Ddht11.c51 /* Data transmission timing (nano seconds) */
76 static unsigned char dht11_decode_byte(int *timing, int threshold) dht11_decode_byte() argument
83 if (timing[i] >= threshold) dht11_decode_byte()
92 int i, t, timing[DHT11_BITS_PER_READ], threshold, dht11_decode() local
117 timing[i] = t / timeres; dht11_decode()
120 hum_int = dht11_decode_byte(timing, threshold); dht11_decode()
121 hum_dec = dht11_decode_byte(&timing[8], threshold); dht11_decode()
122 temp_int = dht11_decode_byte(&timing[16], threshold); dht11_decode()
123 temp_dec = dht11_decode_byte(&timing[24], threshold); dht11_decode()
124 checksum = dht11_decode_byte(&timing[32], threshold); dht11_decode()
/linux-4.1.27/drivers/mtd/nand/
H A Dcafe_nand.c90 static int timing[3]; variable
91 module_param_array(timing, int, &numtimings, 0644);
642 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings); cafe_nand_probe()
647 timing[0], timing[1], timing[2]); cafe_nand_probe()
649 timing[0] = cafe_readl(cafe, NAND_TIMING1); cafe_nand_probe()
650 timing[1] = cafe_readl(cafe, NAND_TIMING2); cafe_nand_probe()
651 timing[2] = cafe_readl(cafe, NAND_TIMING3); cafe_nand_probe()
653 if (timing[0] | timing[1] | timing[2]) { cafe_nand_probe()
655 timing[0], timing[1], timing[2]); cafe_nand_probe()
658 timing[0] = timing[1] = timing[2] = 0xffffffff; cafe_nand_probe()
666 cafe_writel(cafe, timing[0], NAND_TIMING1); cafe_nand_probe()
667 cafe_writel(cafe, timing[1], NAND_TIMING2); cafe_nand_probe()
668 cafe_writel(cafe, timing[2], NAND_TIMING3); cafe_nand_probe()
829 /* Restore timing configuration */ cafe_nand_resume()
830 cafe_writel(cafe, timing[0], NAND_TIMING1); cafe_nand_resume()
831 cafe_writel(cafe, timing[1], NAND_TIMING2); cafe_nand_resume()
832 cafe_writel(cafe, timing[2], NAND_TIMING3); cafe_nand_resume()
H A Dnand_timings.c243 * timings according to the given ONFI timing mode
244 * @mode: ONFI timing mode
H A Dpxa3xx_nand.c246 static struct pxa3xx_nand_timing timing[] = { variable in typeref:struct:pxa3xx_nand_timing
254 { "DEFAULT FLASH", 0, 0, 2048, 8, 8, 0, &timing[0] },
255 { "64MiB 16-bit", 0x46ec, 32, 512, 16, 16, 4096, &timing[1] },
256 { "256MiB 8-bit", 0xdaec, 64, 2048, 8, 8, 2048, &timing[1] },
257 { "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] },
258 { "128MiB 8-bit", 0xa12c, 64, 2048, 8, 8, 1024, &timing[2] },
259 { "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, 1024, &timing[2] },
260 { "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, 4096, &timing[2] },
261 { "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, 4096, &timing[2] },
262 { "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, &timing[3] },
981 * chip select has been changed, if yes, reset the timing nand_cmdfunc()
1029 * chip select has been changed, if yes, reset the timing nand_cmdfunc_extended()
1275 pxa3xx_nand_set_timing(host, f->timing); pxa3xx_nand_config_flash()
1379 /* use the common timing to make a try */ pxa3xx_nand_sensing()
1495 "Read out ID 0, potential timing set wrong!!\n"); pxa3xx_nand_scan()
1905 * then the driver would reset the timing according pxa3xx_nand_resume()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramnv50.c32 #include <subdev/bios/timing.h>
71 } ramcfg, timing; nv50_ram_calc() local
100 timing.data = nvbios_timingEe(bios, strap, &ver, &hdr, nv50_ram_calc()
102 if (!timing.data || ver != 0x10 || hdr < 0x12) { nv50_ram_calc()
103 nv_error(pfb, "invalid/missing timing entry " nv50_ram_calc()
105 strap, timing.data, ver, hdr); nv50_ram_calc()
109 timing.data = 0; nv50_ram_calc()
173 ram_mask(hwsq, timing[3], 0x00000000, 0x00000000); /*XXX*/ nv50_ram_calc()
174 ram_mask(hwsq, timing[1], 0x00000000, 0x00000000); /*XXX*/ nv50_ram_calc()
175 ram_mask(hwsq, timing[6], 0x00000000, 0x00000000); /*XXX*/ nv50_ram_calc()
176 ram_mask(hwsq, timing[7], 0x00000000, 0x00000000); /*XXX*/ nv50_ram_calc()
177 ram_mask(hwsq, timing[8], 0x00000000, 0x00000000); /*XXX*/ nv50_ram_calc()
178 ram_mask(hwsq, timing[0], 0x00000000, 0x00000000); /*XXX*/ nv50_ram_calc()
179 ram_mask(hwsq, timing[2], 0x00000000, 0x00000000); /*XXX*/ nv50_ram_calc()
180 ram_mask(hwsq, timing[4], 0x00000000, 0x00000000); /*XXX*/ nv50_ram_calc()
181 ram_mask(hwsq, timing[5], 0x00000000, 0x00000000); /*XXX*/ nv50_ram_calc()
183 ram_mask(hwsq, timing[0], 0x00000000, 0x00000000); /*XXX*/ nv50_ram_calc()
H A Dsddr3.c76 /* XXX: NV50: Get CWL from the timing register */ nvkm_sddr3_calc()
86 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; nvkm_sddr3_calc()
87 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; nvkm_sddr3_calc()
88 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; nvkm_sddr3_calc()
H A Dramgt215.c34 #include <subdev/bios/timing.h>
350 gt215_ram_timing_calc(struct nvkm_fb *pfb, u32 *timing) gt215_ram_timing_calc() argument
375 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); gt215_ram_timing_calc()
376 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | gt215_ram_timing_calc()
380 timing[2] = (T(CWL) - 1) << 24 | gt215_ram_timing_calc()
384 timing[3] = (cur3 & 0x00ff0000) | gt215_ram_timing_calc()
388 timing[4] = T(20) << 24 | gt215_ram_timing_calc()
392 timing[5] = T(RFC) << 24 | gt215_ram_timing_calc()
396 timing[6] = (0x5a + T(CL)) << 16 | gt215_ram_timing_calc()
399 timing[7] = (cur7 & 0xff000000) | gt215_ram_timing_calc()
402 timing[8] = cur8 & 0xffffff00; gt215_ram_timing_calc()
409 timing[8] |= T(CL); gt215_ram_timing_calc()
416 timing[0], timing[1], timing[2], timing[3]); gt215_ram_timing_calc()
418 timing[4], timing[5], timing[6], timing[7]); gt215_ram_timing_calc()
419 nv_debug(pfb, " 240: %08x\n", timing[8]); gt215_ram_timing_calc()
503 u32 timing[9]; gt215_ram_calc() local
542 nv_error(pfb, "invalid/missing timing entry\n"); gt215_ram_calc()
553 gt215_ram_timing_calc(pfb, timing); gt215_ram_calc()
734 ram_wr32(fuc, 0x100220[3], timing[3]); gt215_ram_calc()
735 ram_wr32(fuc, 0x100220[1], timing[1]); gt215_ram_calc()
736 ram_wr32(fuc, 0x100220[6], timing[6]); gt215_ram_calc()
737 ram_wr32(fuc, 0x100220[7], timing[7]); gt215_ram_calc()
738 ram_wr32(fuc, 0x100220[2], timing[2]); gt215_ram_calc()
739 ram_wr32(fuc, 0x100220[4], timing[4]); gt215_ram_calc()
740 ram_wr32(fuc, 0x100220[5], timing[5]); gt215_ram_calc()
741 ram_wr32(fuc, 0x100220[0], timing[0]); gt215_ram_calc()
742 ram_wr32(fuc, 0x100220[8], timing[8]); gt215_ram_calc()
H A Dgddr3.c84 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; nvkm_gddr3_calc()
85 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; nvkm_gddr3_calc()
86 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; nvkm_gddr3_calc()
H A Dgddr5.c27 * for any configuration (combination of rammap+ramcfg+timing) that
57 WL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; nvkm_gddr5_calc()
58 CL = (ram->next->bios.timing[1] & 0x0000001f); nvkm_gddr5_calc()
59 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; nvkm_gddr5_calc()
H A Dsddr2.c72 CL = (ram->next->bios.timing[1] & 0x0000001f); nvkm_sddr2_calc()
73 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; nvkm_sddr2_calc()
H A Dramgk104.c35 #include <subdev/bios/timing.h>
458 /* PFB timing */ gk104_ram_calc_gddr5()
459 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]); gk104_ram_calc_gddr5()
460 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]); gk104_ram_calc_gddr5()
461 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]); gk104_ram_calc_gddr5()
462 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]); gk104_ram_calc_gddr5()
463 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]); gk104_ram_calc_gddr5()
464 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]); gk104_ram_calc_gddr5()
465 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]); gk104_ram_calc_gddr5()
466 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]); gk104_ram_calc_gddr5()
467 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]); gk104_ram_calc_gddr5()
468 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]); gk104_ram_calc_gddr5()
469 ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]); gk104_ram_calc_gddr5()
564 data = (next->bios.timing[10] & 0x7f000000) >> 24; gk104_ram_calc_gddr5()
826 /* PFB timing */ gk104_ram_calc_sddr3()
827 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]); gk104_ram_calc_sddr3()
828 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]); gk104_ram_calc_sddr3()
829 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]); gk104_ram_calc_sddr3()
830 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]); gk104_ram_calc_sddr3()
831 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]); gk104_ram_calc_sddr3()
832 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]); gk104_ram_calc_sddr3()
833 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]); gk104_ram_calc_sddr3()
834 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]); gk104_ram_calc_sddr3()
835 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]); gk104_ram_calc_sddr3()
836 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]); gk104_ram_calc_sddr3()
837 ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]); gk104_ram_calc_sddr3()
868 data = (next->bios.timing[10] & 0x7f000000) >> 24; gk104_ram_calc_sddr3()
H A Dramgf100.c32 #include <subdev/bios/timing.h>
138 } rammap, ramcfg, timing; gf100_ram_calc() local
168 timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size, gf100_ram_calc()
170 if (!timing.data || ver != 0x10 || timing.size < 0x19) { gf100_ram_calc()
171 nv_error(pfb, "invalid/missing timing entry\n"); gf100_ram_calc()
175 timing.data = 0; gf100_ram_calc()
/linux-4.1.27/drivers/net/wireless/ath/ath5k/
H A Dani.h69 * @ofdm_errors: OFDM timing error count
70 * @cck_errors: CCK timing error count
73 * @last_ofdm_errors: OFDM timing error count from previous run (for tats)
74 * @last_cck_errors: CCK timing error count from previous run (for stats)
75 * @sum_ofdm_errors: Sum of OFDM timing errors (for stats)
76 * @sum_cck_errors: Sum of all CCK timing errors (for stats)
/linux-4.1.27/include/linux/platform_data/
H A Dmtd-nand-pxa3xx.h28 struct pxa3xx_nand_timing *timing; /* NAND Flash timing */ member in struct:pxa3xx_nand_flash
39 * and timing requirement make the keep configuration impossible.
H A Dvideo_s3c.h34 * @vtiming: Video timing when connected to a RGB type panel.
H A Demif_plat.h48 * timing parameters
108 * @min_tck: Minimum value of some timing parameters in terms
H A Dmtd-davinci.h87 struct davinci_aemif_timing *timing; member in struct:davinci_nand_pdata
H A Dmtd-nand-s3c2410.h47 /* timing information for controller, all times in nanoseconds */
/linux-4.1.27/arch/avr32/mach-at32ap/include/mach/
H A Dsmc.h16 * All timing parameters are in nanoseconds.
43 * All timing parameters are in clock cycles.
108 const struct smc_timing *timing);
/linux-4.1.27/drivers/gpu/drm/exynos/
H A Dexynos_mixer.h17 /* This function returns 0 if the given timing is valid for the mixer */
/linux-4.1.27/arch/blackfin/include/asm/
H A Dnand.h33 /* RD/WR strobe delay timing information, all times in SCLK cycles */
/linux-4.1.27/drivers/usb/chipidea/
H A Dotg_fsm.h17 * A-DEVICE timing constants
47 * B-device timing constants
/linux-4.1.27/arch/avr32/boards/merisc/
H A Dflash.c125 printk(KERN_ERR "Merisc: failed to set NOR flash timing #0\n"); merisc_flash_init()
131 printk(KERN_ERR "Merisc: failed to set NOR flash timing #1\n"); merisc_flash_init()
/linux-4.1.27/lib/
H A Djedec_ddr_data.c2 * DDR addressing details and AC timing parameters from JEDEC specs
32 /* LPDDR2 AC timing parameters from JESD209-2 section 12 */
/linux-4.1.27/sound/pci/
H A Dsis7019.c62 /* There are three timing modes for the voices.
95 struct voice *timing; member in struct:voice
138 * buffer for a timing channel.
344 if (!voice->timing) sis_interrupt()
406 if (voice->timing) { sis_free_voice()
408 voice->timing->flags &= ~(VOICE_IN_USE | VOICE_SSO_TIMING | sis_free_voice()
410 voice->timing = NULL; sis_free_voice()
458 * timing voice, as we can use the capture channel's interrupts sis_alloc_timing_voice()
466 if (needed && !voice->timing) { sis_alloc_timing_voice()
468 voice->timing = __sis_alloc_playback_voice(sis); sis_alloc_timing_voice()
469 if (voice->timing) sis_alloc_timing_voice()
472 if (!voice->timing) sis_alloc_timing_voice()
474 voice->timing->substream = substream; sis_alloc_timing_voice()
475 } else if (!needed && voice->timing) { sis_alloc_timing_voice()
477 voice->timing = NULL; sis_alloc_timing_voice()
631 voice = voice->timing; snd_pcm_group_for_each_entry()
635 * doesn't have an external timing channel. snd_pcm_group_for_each_entry()
732 struct voice *timing = voice->timing; sis_prepare_timing_voice() local
733 void __iomem *play_base = timing->ctrl_base; sis_prepare_timing_voice()
734 void __iomem *wave_base = timing->wave_base; sis_prepare_timing_voice()
782 /* The interrupt handler implements the timing synchronization, so sis_prepare_timing_voice()
785 timing->flags |= VOICE_SYNC_TIMING; sis_prepare_timing_voice()
786 timing->sync_base = voice->ctrl_base; sis_prepare_timing_voice()
787 timing->sync_cso = runtime->period_size; sis_prepare_timing_voice()
788 timing->sync_period_size = runtime->period_size; sis_prepare_timing_voice()
789 timing->sync_buffer_size = runtime->buffer_size; sis_prepare_timing_voice()
790 timing->period_size = period_size; sis_prepare_timing_voice()
791 timing->buffer_size = buffer_size; sis_prepare_timing_voice()
792 timing->sso = sso; sis_prepare_timing_voice()
793 timing->vperiod = vperiod; sis_prepare_timing_voice()
797 * So ignore unsigned vs signed -- it doesn't change the timing. sis_prepare_timing_voice()
805 control = timing->buffer_size - 1; sis_prepare_timing_voice()
807 sso_eso = timing->buffer_size - 1; sis_prepare_timing_voice()
808 sso_eso |= timing->sso << 16; sis_prepare_timing_voice()
854 * use a timing voice to clock out the periods. Otherwise, we can sis_pcm_capture_prepare()
857 if (voice->timing) { sis_pcm_capture_prepare()
/linux-4.1.27/drivers/iio/light/
H A Dtcs3414.c59 u8 timing; member in struct:tcs3414_data
158 *val2 = tcs3414_times[data->timing & TCS3414_INTEG_MASK] * 1000; tcs3414_read_raw()
189 data->timing &= ~TCS3414_INTEG_MASK; tcs3414_write_raw()
190 data->timing |= i; tcs3414_write_raw()
193 data->timing); tcs3414_write_raw()
321 data->timing = TCS3414_INTEG_12MS; /* free running */ tcs3414_probe()
323 data->timing); tcs3414_probe()
H A Dtsl2563.c241 * timing and gain settings.
243 static int adc_shiftbits(u8 timing) adc_shiftbits() argument
247 switch (timing & TSL2563_TIMING_MASK) { adc_shiftbits()
259 if (!(timing & TSL2563_TIMING_GAIN16)) adc_shiftbits()
266 static u32 normalize_adc(u16 adc, u8 timing) normalize_adc() argument
268 return adc << adc_shiftbits(timing); normalize_adc()
/linux-4.1.27/include/uapi/linux/can/
H A Dnetlink.h24 * CAN bit-timing parameters
42 * CAN harware-dependent bit-timing constant
44 * Used for calculating and checking bit-timing parameters
/linux-4.1.27/drivers/bus/
H A Dimx-weim.c111 /* Parse and set the timing for this device. */ weim_timing_setup()
126 ret = of_property_read_u32_array(np, "fsl,weim-cs-timing", weim_timing_setup()
131 /* set the timing for WEIM */ weim_timing_setup()
159 dev_warn(&pdev->dev, "%s set timing failed.\n", weim_parse_dt()
/linux-4.1.27/include/uapi/linux/
H A Dprctl.h46 /* Get/set whether we use statistical process timing or accurate timestamp
47 * based process timing */
51 statistical process timing */
53 process timing */
/linux-4.1.27/arch/arm/plat-samsung/include/plat/
H A Dcpu-freq.h103 * @auto_io: Set if the IO timing settings should be generated from the
106 * lines that will require the hardware timing registers to be
113 * timing information.
122 unsigned int need_io:1; /* set if needs io timing support. */
/linux-4.1.27/include/linux/mmc/
H A Dhost.h53 unsigned char timing; /* timing specification used */ member in struct:mmc_ios
238 #define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */
239 #define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */
491 return card->host->ios.timing == MMC_TIMING_SD_HS || mmc_card_hs()
492 card->host->ios.timing == MMC_TIMING_MMC_HS; mmc_card_hs()
497 return card->host->ios.timing >= MMC_TIMING_UHS_SDR12 && mmc_card_uhs()
498 card->host->ios.timing <= MMC_TIMING_UHS_DDR50; mmc_card_uhs()
503 return card->host->ios.timing == MMC_TIMING_MMC_HS200; mmc_card_hs200()
508 return card->host->ios.timing == MMC_TIMING_MMC_DDR52; mmc_card_ddr52()
513 return card->host->ios.timing == MMC_TIMING_MMC_HS400; mmc_card_hs400()
/linux-4.1.27/arch/avr32/boards/mimc200/
H A Dflash.c129 printk(KERN_ERR "mimc200: failed to set 'System' NOR flash timing\n"); mimc200_flash_init()
134 printk(KERN_ERR "mimc200: failed to set 'Data' NOR flash timing\n"); mimc200_flash_init()
/linux-4.1.27/drivers/media/platform/omap3isp/
H A Dispcsi2.c354 * csi2_timing_config - CSI2 timing configuration.
355 * @timing: csi2_timing_cfg structure
359 struct isp_csi2_timing_cfg *timing) csi2_timing_config()
365 if (timing->force_rx_mode) csi2_timing_config()
366 reg |= ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum); csi2_timing_config()
368 reg &= ~ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum); csi2_timing_config()
370 if (timing->stop_state_16x) csi2_timing_config()
371 reg |= ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum); csi2_timing_config()
373 reg &= ~ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum); csi2_timing_config()
375 if (timing->stop_state_4x) csi2_timing_config()
376 reg |= ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum); csi2_timing_config()
378 reg &= ~ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum); csi2_timing_config()
380 reg &= ~ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(timing->ionum); csi2_timing_config()
381 reg |= timing->stop_state_counter << csi2_timing_config()
382 ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(timing->ionum); csi2_timing_config()
554 struct isp_csi2_timing_cfg *timing = &csi2->timing[0]; csi2_configure() local
583 timing->ionum = 1; csi2_configure()
584 timing->force_rx_mode = 1; csi2_configure()
585 timing->stop_state_16x = 1; csi2_configure()
586 timing->stop_state_4x = 1; csi2_configure()
587 timing->stop_state_counter = 0x1FF; csi2_configure()
622 csi2_timing_config(isp, csi2, timing); csi2_configure()
357 csi2_timing_config(struct isp_device *isp, struct isp_csi2_device *csi2, struct isp_csi2_timing_cfg *timing) csi2_timing_config() argument
H A Dispcsi2.h141 struct isp_csi2_timing_cfg timing[2]; member in struct:isp_csi2_device
/linux-4.1.27/Documentation/EDID/
H A Dedid.S36 /* Provide defaults for the timing bits */
113 Bit 1 Preferred timing mode specified in descriptor block 1.
169 /* Standard timing */
242 descriptor2: .byte 0,0 /* Not a detailed timing descriptor */
249 descriptor3: .byte 0,0 /* Not a detailed timing descriptor */
261 .byte 0 /* No extended timing information type */
264 descriptor4: .byte 0,0 /* Not a detailed timing descriptor */
/linux-4.1.27/drivers/video/fbdev/omap2/displays-new/
H A Dpanel-dpi.c208 struct display_timing timing; panel_dpi_probe_of() local
227 r = of_get_display_timing(node, "panel-timing", &timing); panel_dpi_probe_of()
229 dev_err(&pdev->dev, "failed to get video timing\n"); panel_dpi_probe_of()
233 videomode_from_timing(&timing, &vm); panel_dpi_probe_of()
/linux-4.1.27/drivers/video/fbdev/exynos/
H A Dexynos_mipi_dsi_common.c715 struct fb_videomode *timing; exynos_mipi_dsi_set_display_mode() local
718 timing = (struct fb_videomode *)dsim_pd->lcd_panel_info; exynos_mipi_dsi_set_display_mode()
725 timing->lower_margin, exynos_mipi_dsi_set_display_mode()
726 timing->upper_margin); exynos_mipi_dsi_set_display_mode()
728 timing->right_margin, exynos_mipi_dsi_set_display_mode()
729 timing->left_margin); exynos_mipi_dsi_set_display_mode()
731 timing->vsync_len, exynos_mipi_dsi_set_display_mode()
732 timing->hsync_len); exynos_mipi_dsi_set_display_mode()
736 exynos_mipi_dsi_set_main_disp_resol(dsim, timing->xres, exynos_mipi_dsi_set_display_mode()
737 timing->yres); exynos_mipi_dsi_set_display_mode()
742 timing->xres, timing->yres); exynos_mipi_dsi_set_display_mode()
/linux-4.1.27/include/media/davinci/
H A Dvpbe_types.h51 * Structure holding timing and resolution information of a standard.
52 * Used by vpbe_device to set required non-standard timing in the
/linux-4.1.27/arch/mips/pnx833x/stb22x/
H A Dboard.c102 /* Setup MIU CS0 & CS1 timing */ pnx833x_board_setup()
124 /* Setup MIU CS0 & CS1 timing */ pnx833x_board_setup()
/linux-4.1.27/arch/arm/mach-omap2/
H A Dsdrc.c75 * These parameters control various timing delays in the SDRAM controller
79 * Supports 2 different timing parameters for both chip selects.
H A Dsdrc2xxx.c4 * SDRAM timing related functions for OMAP2xxx
35 /* Memory timing, DLL mode flags */
H A Dclkt34xx_dpll3m2.c96 pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", omap3_core_dpll_m2_set_rate()
100 pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", omap3_core_dpll_m2_set_rate()
/linux-4.1.27/drivers/gpu/drm/
H A Ddrm_edid.c60 /* Detail timing is in cm not mm */
62 /* Detailed timing descriptors have bogus size values, so just take the
1493 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1619 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1650 * @t: standard timing params
1652 * Take the standard timing params (in this case width, aspect, and refresh)
1806 * drm_mode_detailed - create a new mode from an EDID detailed timing section
1809 * @timing: EDID detailed timing info
1812 * An EDID detailed timing block contains enough info for us to create and
1817 struct detailed_timing *timing, drm_mode_detailed()
1821 struct detailed_pixel_timing *pt = &timing->data.pixel_data; drm_mode_detailed()
1845 DRM_DEBUG_KMS("Incorrect Detailed timing. " drm_mode_detailed()
1863 timing->pixel_clock = cpu_to_le16(1088); drm_mode_detailed()
1865 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; drm_mode_detailed()
1966 struct detailed_timing *timing) mode_in_range()
1969 u8 *t = (u8 *)timing; mode_in_range()
2012 struct detailed_timing *timing) drm_dmt_modes_for_range()
2019 if (mode_in_range(drm_dmt_modes + i, edid, timing) && drm_dmt_modes_for_range()
2047 struct detailed_timing *timing) drm_gtf_modes_for_range()
2060 if (!mode_in_range(newmode, edid, timing) || drm_gtf_modes_for_range()
2075 struct detailed_timing *timing) drm_cvt_modes_for_range()
2089 if (!mode_in_range(newmode, edid, timing) || drm_cvt_modes_for_range()
2103 do_inferred_modes(struct detailed_timing *timing, void *c) do_inferred_modes() argument
2106 struct detailed_non_pixel *data = &timing->data.other_data; do_inferred_modes()
2114 timing); do_inferred_modes()
2124 timing); do_inferred_modes()
2132 timing); do_inferred_modes()
2156 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) drm_est3_modes() argument
2160 u8 *est = ((u8 *)timing) + 5; drm_est3_modes()
2185 do_established_modes(struct detailed_timing *timing, void *c) do_established_modes() argument
2188 struct detailed_non_pixel *data = &timing->data.other_data; do_established_modes()
2191 closure->modes += drm_est3_modes(closure->connector, timing); do_established_modes()
2234 do_standard_modes(struct detailed_timing *timing, void *c) do_standard_modes() argument
2237 struct detailed_non_pixel *data = &timing->data.other_data; do_standard_modes()
2295 struct detailed_timing *timing) drm_cvt_modes()
2306 cvt = &(timing->data.other_data.data.cvt[i]); drm_cvt_modes()
2344 do_cvt_mode(struct detailed_timing *timing, void *c) do_cvt_mode() argument
2347 struct detailed_non_pixel *data = &timing->data.other_data; do_cvt_mode()
2350 closure->modes += drm_cvt_modes(closure->connector, timing); do_cvt_mode()
2370 do_detailed_mode(struct detailed_timing *timing, void *c) do_detailed_mode() argument
2375 if (timing->pixel_clock) { do_detailed_mode()
2377 closure->edid, timing, do_detailed_mode()
3703 * - standard timing codes drm_add_edid_modes()
3704 * - established timing codes drm_add_edid_modes()
1815 drm_mode_detailed(struct drm_device *dev, struct edid *edid, struct detailed_timing *timing, u32 quirks) drm_mode_detailed() argument
1965 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, struct detailed_timing *timing) mode_in_range() argument
2011 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, struct detailed_timing *timing) drm_dmt_modes_for_range() argument
2046 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, struct detailed_timing *timing) drm_gtf_modes_for_range() argument
2074 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, struct detailed_timing *timing) drm_cvt_modes_for_range() argument
2294 drm_cvt_modes(struct drm_connector *connector, struct detailed_timing *timing) drm_cvt_modes() argument
/linux-4.1.27/drivers/net/wireless/iwlwifi/dvm/
H A Drxon.c304 memset(&ctx->timing, 0, sizeof(struct iwl_rxon_time_cmd)); iwl_send_rxon_timing()
306 ctx->timing.timestamp = cpu_to_le64(priv->timestamp); iwl_send_rxon_timing()
307 ctx->timing.listen_interval = cpu_to_le16(conf->listen_interval); iwl_send_rxon_timing()
315 ctx->timing.atim_window = 0; iwl_send_rxon_timing()
322 ctx->timing.beacon_interval = iwl_send_rxon_timing()
323 priv->contexts[IWL_RXON_CTX_BSS].timing.beacon_interval; iwl_send_rxon_timing()
324 beacon_int = le16_to_cpu(ctx->timing.beacon_interval); iwl_send_rxon_timing()
331 ctx->timing.beacon_interval = iwl_send_rxon_timing()
332 priv->contexts[IWL_RXON_CTX_PAN].timing.beacon_interval; iwl_send_rxon_timing()
333 beacon_int = le16_to_cpu(ctx->timing.beacon_interval); iwl_send_rxon_timing()
337 ctx->timing.beacon_interval = cpu_to_le16(beacon_int); iwl_send_rxon_timing()
345 ctx->timing.beacon_init_val = cpu_to_le32(interval_tm - rem); iwl_send_rxon_timing()
347 ctx->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ?: 1) : 1; iwl_send_rxon_timing()
351 le16_to_cpu(ctx->timing.beacon_interval), iwl_send_rxon_timing()
352 le32_to_cpu(ctx->timing.beacon_init_val), iwl_send_rxon_timing()
353 le16_to_cpu(ctx->timing.atim_window)); iwl_send_rxon_timing()
356 0, sizeof(ctx->timing), &ctx->timing); iwl_send_rxon_timing()
374 IWL_ERR(priv, "Failed to send timing (%d)!\n", ret); iwlagn_rxon_disconn()
465 /* RXON timing must be before associated RXON */ iwlagn_rxon_connect()
469 IWL_ERR(priv, "Failed to send timing (%d)!\n", ret); iwlagn_rxon_connect()
/linux-4.1.27/drivers/memory/
H A Dmvebu-devbus.c304 * we need this in order to convert timing mvebu_devbus_probe()
310 dev_dbg(devbus->dev, "Setting timing parameter, tick is %lu ps\n", mvebu_devbus_probe()
319 /* Set the new timing parameters */ mvebu_devbus_probe()
328 * guarantee that the child will be probed after the timing mvebu_devbus_probe()
H A Dti-aemif.c132 * aemif_calc_rate - calculate timing data.
138 * On success, returns the calculated timing value minus 1 for easy
139 * programming into AEMIF timing registers, else negative errno.
151 /* It is generally OK to have a more relaxed timing than requested... */ aemif_calc_rate()
167 * This function programs the given timing values (in real clock) into the
230 * the timing values. Required for get/set commands and also for
388 * guarantee that the child will be probed after the AEMIF timing
H A Dof_memory.c21 * of_get_min_tck() - extract min timing values for ddr
23 * @device: device requesting for min timing values
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
H A Dramcfg.h92 unsigned timing[11]; member in struct:nvbios_ramcfg
/linux-4.1.27/drivers/watchdog/
H A Dintel_scu_watchdog.h42 /* Ajustment to clock tick frequency to make timing come out right */
/linux-4.1.27/include/media/
H A Dv4l2-dv-timings.h41 * @fnc: callback to check if this timing is OK. May be NULL.
56 * @fnc: callback to check if this timing is OK. May be NULL.
63 * If a valid timing for the given index is found, it will fill in @t and
74 * @pclock_delta: maximum delta between t->pixelclock and the timing struct
/linux-4.1.27/arch/powerpc/platforms/chrp/
H A Dgg2.h46 #define GG2_PCI_ROM_TIME 0x74 /* ROM timing */
/linux-4.1.27/arch/s390/include/asm/
H A Dnmi.h21 __u32 cd : 1; /* 04 timing-facility damage */
/linux-4.1.27/arch/sh/boards/mach-kfr2r09/
H A Dlcd_wqvga.c159 /* timing (normal) */ display_on()
163 /* timing (partial) */ display_on()
167 /* timing (idle) */ display_on()
171 /* timing (source/VCOM/gate driving) */ display_on()
/linux-4.1.27/arch/powerpc/kvm/
H A DMakefile19 obj-$(CONFIG_KVM_EXIT_TIMING) += timing.o
/linux-4.1.27/arch/avr32/boards/atngw100/
H A Dflash.c90 printk(KERN_ERR "atngw100: failed to set NOR flash timing\n"); atngw100_flash_init()
/linux-4.1.27/arch/avr32/boards/atstk1000/
H A Dflash.c90 printk(KERN_ERR "atstk1000: failed to set NOR flash timing\n"); atstk1000_flash_init()
/linux-4.1.27/arch/avr32/boards/favr-32/
H A Dflash.c90 printk(KERN_ERR "Favr-32: failed to set NOR flash timing\n"); favr32_flash_init()
/linux-4.1.27/arch/avr32/boards/hammerhead/
H A Dflash.c107 /* We use conservative timing settings, as the minimal settings aren't
187 "hammerhead: failed to set ISP1160 USBH timing\n"); hammerhead_usbh_init()
356 printk(KERN_ERR "hammerhead: failed to set NOR flash timing\n"); hammerhead_flash_init()
374 printk(KERN_ERR "hammerhead: failed to set FPGA timing\n"); hammerhead_flash_init()
/linux-4.1.27/arch/c6x/kernel/
H A Dvectors.S12 ; At RESET the processor sets up the DRAM timing parameters and
/linux-4.1.27/arch/arm/mach-imx/
H A Dcpuidle-imx6sx.c95 * set ARM power up/down timing to the fastest, imx6sx_cpuidle_init()
/linux-4.1.27/net/netfilter/
H A Dnf_conntrack_netbios_ns.c14 * timing out) matching all reply connections from the
/linux-4.1.27/drivers/net/wireless/prism54/
H A Disl_oid.h189 /* Support for 802.11 slot timing (time between packets).
191 * Long uses 802.11a slot timing (9 usec ?)
192 * Short uses 802.11b slot timing (20 use ?) */
195 /* Allows *only* long 802.11b slot timing */
197 /* Allows *only* long 802.11a slot timing */
/linux-4.1.27/drivers/net/can/
H A Dbfin_can.c88 __BFP(timing); /* offset 0x84 */
152 * bfin can timing parameters
164 * apply to the bit timing configuration when BRP is less than 4.
176 u16 clk, timing; bfin_can_set_bittiming() local
179 timing = ((bt->sjw - 1) << 8) | (bt->prop_seg + bt->phase_seg1 - 1) | bfin_can_set_bittiming()
187 timing |= SAM; bfin_can_set_bittiming()
190 writew(timing, &reg->timing); bfin_can_set_bittiming()
192 netdev_info(dev, "setting CLOCK=0x%04x TIMING=0x%04x\n", clk, timing); bfin_can_set_bittiming()
H A Ddev.c74 * Bit-timing calculation derived from:
81 * Calculates proper bit-timing parameters for a specified bit-rate
82 * and sample-point, which can then be used to set the bit-timing
206 netdev_err(dev, "bit-timing calculation not available\n"); can_calc_bittiming()
212 * Checks the validity of the specified bit-timing parameters prop_seg,
256 /* Check if the CAN device has bit-timing parameters */ can_get_bittiming()
262 * timing parameters are calculated based on the provided bitrate OR can_get_bittiming()
263 * alternatively the CAN timing parameters (tq, prop_seg, etc.) are can_get_bittiming()
735 netdev_err(dev, "bit-timing not yet defined\n"); open_candev()
743 netdev_err(dev, "incorrect/missing data bit-timing\n"); open_candev()
842 /* Finally, set the bit-timing registers */ can_changelink()
914 /* Finally, set the bit-timing registers */ can_changelink()
/linux-4.1.27/drivers/staging/media/omap4iss/
H A Diss_csi2.c363 * csi2_timing_config - CSI2 timing configuration.
364 * @timing: csi2_timing_cfg structure
367 struct iss_csi2_timing_cfg *timing) csi2_timing_config()
373 if (timing->force_rx_mode) csi2_timing_config()
378 if (timing->stop_state_16x) csi2_timing_config()
383 if (timing->stop_state_4x) csi2_timing_config()
389 reg |= timing->stop_state_counter << csi2_timing_config()
532 struct iss_csi2_timing_cfg *timing = &csi2->timing[0]; csi2_configure() local
556 timing->force_rx_mode = 1; csi2_configure()
557 timing->stop_state_16x = 1; csi2_configure()
558 timing->stop_state_4x = 1; csi2_configure()
559 timing->stop_state_counter = 0x1ff; csi2_configure()
594 csi2_timing_config(csi2, timing); csi2_configure()
366 csi2_timing_config(struct iss_csi2_device *csi2, struct iss_csi2_timing_cfg *timing) csi2_timing_config() argument
H A Diss_csi2.h144 struct iss_csi2_timing_cfg timing[2]; member in struct:iss_csi2_device
/linux-4.1.27/drivers/ssb/
H A Ddriver_extif.c93 /* Set timing for the flash */ ssb_extif_timing_init()
99 /* Set programmable interface timing for external uart */ ssb_extif_timing_init()
/linux-4.1.27/drivers/video/fbdev/geode/
H A Ddisplay_gx.c74 /* Disable the timing generator. */ gx_set_mode()
129 /* Enable timing generator. */ gx_set_mode()
/linux-4.1.27/drivers/video/fbdev/mbx/
H A Dreg_bits.h432 /* DHT01 - Display horizontal timing register 01 */
438 /* DHT02 - Display horizontal timing register 02 */
444 /* DHT03 - Display horizontal timing register 03 */
450 /* DVT01 - Display vertical timing register 01 */
456 /* DVT02 - Display vertical timing register 02 */
462 /* DVT03 - Display vertical timing register 03 */
474 /* DHDET - display horizontal DE timing register */
480 /* DVDET - display vertical DE timing register */
/linux-4.1.27/include/net/
H A Dcfg802154.h82 * We do not provide timing-related variables, as they
99 /* lifs and sifs periods timing */
/linux-4.1.27/sound/core/seq/
H A Dseq_system.c49 * synchronisation and timing information. In this case we would ideally have
50 * a list of subscribers for each type of sync (time, tick), for each timing
/linux-4.1.27/drivers/media/platform/omap/
H A Domap_vout.c449 struct omap_video_timings *timing; omapvid_init() local
462 timing = &dssdev->panel.timings; omapvid_init()
474 posy = (timing->y_res - win->w.width) - win->w.left; omapvid_init()
479 posx = (timing->x_res - win->w.width) - win->w.left; omapvid_init()
480 posy = (timing->y_res - win->w.height) - win->w.top; omapvid_init()
488 posx = (timing->x_res - win->w.height) - win->w.top; omapvid_init()
1095 struct omap_video_timings *timing; vidioc_try_fmt_vid_out() local
1107 timing = &dssdev->panel.timings; vidioc_try_fmt_vid_out()
1109 vout->fbuf.fmt.height = timing->y_res; vidioc_try_fmt_vid_out()
1110 vout->fbuf.fmt.width = timing->x_res; vidioc_try_fmt_vid_out()
1122 struct omap_video_timings *timing; vidioc_s_fmt_vid_out() local
1140 timing = &dssdev->panel.timings; vidioc_s_fmt_vid_out()
1153 vout->fbuf.fmt.height = timing->x_res; vidioc_s_fmt_vid_out()
1154 vout->fbuf.fmt.width = timing->y_res; vidioc_s_fmt_vid_out()
1156 vout->fbuf.fmt.height = timing->y_res; vidioc_s_fmt_vid_out()
1157 vout->fbuf.fmt.width = timing->x_res; vidioc_s_fmt_vid_out()
1296 struct omap_video_timings *timing; vidioc_s_crop() local
1313 timing = &dssdev->panel.timings; vidioc_s_crop()
1316 vout->fbuf.fmt.height = timing->x_res; vidioc_s_crop()
1317 vout->fbuf.fmt.width = timing->y_res; vidioc_s_crop()
1319 vout->fbuf.fmt.height = timing->y_res; vidioc_s_crop()
1320 vout->fbuf.fmt.width = timing->x_res; vidioc_s_crop()
/linux-4.1.27/drivers/mmc/core/
H A Dcore.h51 void mmc_set_timing(struct mmc_host *host, unsigned int timing);
H A Ddebugfs.c119 switch (ios->timing) { mmc_ios_show()
151 seq_printf(s, "timing spec:\t%u (%s)\n", ios->timing, str); mmc_ios_show()
H A Dsd.c487 unsigned int timing = 0; sd_set_bus_speed_mode() local
491 timing = MMC_TIMING_UHS_SDR104; sd_set_bus_speed_mode()
495 timing = MMC_TIMING_UHS_DDR50; sd_set_bus_speed_mode()
499 timing = MMC_TIMING_UHS_SDR50; sd_set_bus_speed_mode()
503 timing = MMC_TIMING_UHS_SDR25; sd_set_bus_speed_mode()
507 timing = MMC_TIMING_UHS_SDR12; sd_set_bus_speed_mode()
522 mmc_set_timing(card->host, timing); sd_set_bus_speed_mode()
664 (card->host->ios.timing == MMC_TIMING_UHS_SDR50 || mmc_sd_init_uhs_card()
665 card->host->ios.timing == MMC_TIMING_UHS_DDR50 || mmc_sd_init_uhs_card()
666 card->host->ios.timing == MMC_TIMING_UHS_SDR104)) { mmc_sd_init_uhs_card()
676 if (err && card->host->ios.timing == MMC_TIMING_UHS_DDR50) { mmc_sd_init_uhs_card()
H A Dsdio.c473 unsigned int bus_speed, timing; sdio_set_bus_speed_mode() local
485 timing = MMC_TIMING_UHS_SDR12; sdio_set_bus_speed_mode()
489 timing = MMC_TIMING_UHS_SDR104; sdio_set_bus_speed_mode()
495 timing = MMC_TIMING_UHS_DDR50; sdio_set_bus_speed_mode()
502 timing = MMC_TIMING_UHS_SDR50; sdio_set_bus_speed_mode()
509 timing = MMC_TIMING_UHS_SDR25; sdio_set_bus_speed_mode()
517 timing = MMC_TIMING_UHS_SDR12; sdio_set_bus_speed_mode()
533 mmc_set_timing(card->host, timing); sdio_set_bus_speed_mode()
569 ((card->host->ios.timing == MMC_TIMING_UHS_SDR50) || mmc_sdio_init_uhs_card()
570 (card->host->ios.timing == MMC_TIMING_UHS_SDR104))) mmc_sdio_init_uhs_card()
/linux-4.1.27/drivers/mtd/nand/gpmi-nand/
H A Dgpmi-nand.h90 * struct nand_timing - Fundamental timing attributes for NAND.
100 * @gpmi_sample_delay_in_ns: A GPMI-specific timing parameter. A negative value
150 struct nand_timing timing; member in struct:gpmi_nand_data
206 * struct gpmi_nfc_hardware_timing - GPMI hardware timing parameters.
H A Dgpmi-lib.c326 /* Apply timing to current hardware conditions. */ gpmi_nfc_compute_hardware_timing()
333 struct nand_timing target = this->timing; gpmi_nfc_compute_hardware_timing()
364 /* Check if improved timing information is available. */ gpmi_nfc_compute_hardware_timing()
377 * Here, we quantize the setup and hold timing parameters to the gpmi_nfc_compute_hardware_timing()
483 * Check if improved timing information is available. If not, we have to gpmi_nfc_compute_hardware_timing()
537 * If control arrives here, we have more detailed timing information, gpmi_nfc_compute_hardware_timing()
793 * the nand EDO(extended Data Out) timing could be applied.
795 * The feedback read strobe can be delayed to support the nand EDO timing
940 /* [2] send GET FEATURE command to double-check the timing mode */ enable_edo_mode()
953 /* Let the gpmi_begin() re-compute the timing again. */ enable_edo_mode()
977 /* We only support the timing mode 4 and mode 5. */ gpmi_extra_init()
1008 /* Only initialize the timing once */ gpmi_begin()
/linux-4.1.27/drivers/staging/mt29f_spinand/
H A Dmt29f_spinand.h43 #define REG_STATUS 0xc0/* timing */
/linux-4.1.27/drivers/gpu/drm/ast/
H A Dast_dram_tables.h4 /* DRAM timing tables */
/linux-4.1.27/arch/x86/lib/
H A Ddelay.c10 * jump magic is needed to get the timing stable on all the CPU's
/linux-4.1.27/arch/sh/mm/
H A Dtlb-sh4.c47 * the PTEA timing control and space attribute bits __update_tlb()
/linux-4.1.27/arch/mips/bcm63xx/
H A Dcs.c63 * configure chipselect timing (ns)
/linux-4.1.27/arch/mips/include/asm/mach-rc32434/
H A Drb.h65 u32 timing; member in struct:dev_reg
/linux-4.1.27/drivers/media/dvb-frontends/
H A Ds5h1409.h55 /* MPEG signal timing */
H A Ds5h1411.h43 /* MPEG signal timing */
H A Ds5h1432.h49 /* MPEG signal timing */
H A Dstb0899_algo.c171 * check for timing lock
179 s8 timing; stb0899_check_tmg() local
186 timing = stb0899_read_reg(state, STB0899_RTF); stb0899_check_tmg()
189 if ((lock > 48) && (abs(timing) >= 110)) { stb0899_check_tmg()
205 * perform a fs/2 zig-zag to find timing
218 /* timing loop computation & symbol rate optimisation */ stb0899_search_tmg()
498 * Search for a signal, timing, carrier and data for a
553 dprintk(state->verbose, FE_DEBUG, 1, "Set the timing loop to acquisition"); stb0899_dvbs_algo()
554 /* Set the timing loop to acquisition */ stb0899_dvbs_algo()
614 msleep(internal->t_agc1 + internal->t_agc2 + internal->t_derot); /* AGC1, AGC2 and timing loop */ stb0899_dvbs_algo()
669 /* Set the timing loop to tracking */ stb0899_dvbs_algo()
901 * set bit timing loop bandwidth as a percentage of the symbol rate
978 * Initialize DVBS2 UWP, CSM, carrier and timing loops
1024 * initialize the timing loop
1312 * Search for signal, timing, carrier and data for a given
/linux-4.1.27/arch/powerpc/include/asm/
H A Ddelay.h27 * longer (eg 10ms). With the right timing these errors can add up.
/linux-4.1.27/arch/cris/arch-v32/mach-a3/
H A Ddram_init.S73 ; Set timing
/linux-4.1.27/arch/arm/mach-sa1100/
H A Dpleb.c124 * Fix expansion memory timing for network card pleb_map_io()
/linux-4.1.27/include/drm/
H A Dexynos_drm.h23 * @timing: default video mode for initializing
H A Ddrm_edid.h64 /* If detailed data is pixel timing */
84 /* If it's not pixel timing, it'll be one of the below */
138 fb=color point data, fa=standard timing data,
/linux-4.1.27/drivers/mtd/maps/
H A Dintel_vr_nor.c16 * and disable boot acceleration. The timing parameters in the register are
18 * timing parameters are maximally conservative (slow), so access to the flash
19 * will be slower than it should be if the BIOS has not initialized the timing
/linux-4.1.27/drivers/staging/fbtft/
H A Dfb_ili9325.c120 write_reg(par, 0x00E3, 0x3008); /* Set internal timing */ init_display()
121 write_reg(par, 0x00E7, 0x0012); /* Set internal timing */ init_display()
122 write_reg(par, 0x00EF, 0x1231); /* Set internal timing */ init_display()
/linux-4.1.27/drivers/scsi/
H A Dqlogicpti.h479 /* RISC processor memory timing register */
480 #define RISC_MTREG_P1DFLT 0x1200 /* Default read/write timing, pg1 */
481 #define RISC_MTREG_P0DFLT 0x0012 /* Default read/write timing, pg0 */
482 #define RISC_MTREG_P1ULTRA 0x2300 /* Ultra-mode rw timing, pg1 */
483 #define RISC_MTREG_P0ULTRA 0x0023 /* Ultra-mode rw timing, pg0 */
/linux-4.1.27/drivers/gpu/drm/radeon/
H A Dradeon_legacy_tv.c23 * Indexes in h. code timing table for horizontal line position adjustment
170 { /* NTSC timing for 27 Mhz ref clk */
185 { /* PAL timing for 27 Mhz ref clk */
200 { /* NTSC timing for 14 Mhz ref clk */
215 { /* PAL timing for 14 Mhz ref clk */
457 /* adjust positions 1&2 in hor. cod timing table */ radeon_legacy_tv_init_restarts()
/linux-4.1.27/drivers/i2c/busses/
H A Di2c-img-scb.c16 * interrupt can be used for timing).
249 /* Fixed timing values */
1106 struct img_i2c_timings timing; img_i2c_init() local
1132 timing = timings[0]; img_i2c_init()
1135 timing = timings[i]; img_i2c_init()
1186 tckh = timing.tckh / clk_period; img_i2c_init()
1187 if (timing.tckh % clk_period) img_i2c_init()
1208 tsdh = timing.tsdh / clk_period; img_i2c_init()
1209 if (timing.tsdh % clk_period) img_i2c_init()
1222 data = timing.tpl / clk_period; img_i2c_init()
1228 data = timing.tph / clk_period; img_i2c_init()
1237 data = timing.tp2s / clk_period; img_i2c_init()
/linux-4.1.27/drivers/media/pci/zoran/
H A Dzoran.h48 #define BUZ_MAX_WIDTH (zr->timing->Wa)
49 #define BUZ_MAX_HEIGHT (zr->timing->Ha)
289 struct tvnorm *timing; member in struct:zoran
/linux-4.1.27/arch/x86/kernel/
H A Dioport.c36 * IO bitmap up. ioperm() is much less timing critical than clone(), sys_ioperm()
/linux-4.1.27/arch/mips/include/asm/
H A Dmc146818-time.h16 * For check timing call set_rtc_mmss() 500ms; used in timer interrupt.

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