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Searched refs:timing (Results 1 – 200 of 335) sorted by relevance

12

/linux-4.1.27/drivers/gpu/drm/tegra/
Dmipi-phy.c19 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
22 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
23 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
24 timing->clkpre = 8; in mipi_dphy_timing_get_default()
25 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
26 timing->clksettle = 95; in mipi_dphy_timing_get_default()
27 timing->clktermen = 0; in mipi_dphy_timing_get_default()
28 timing->clktrail = 80; in mipi_dphy_timing_get_default()
29 timing->clkzero = 260; in mipi_dphy_timing_get_default()
30 timing->dtermen = 0; in mipi_dphy_timing_get_default()
[all …]
Dmipi-phy.h46 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
48 int mipi_dphy_timing_validate(struct mipi_dphy_timing *timing,
Ddsi.c34 struct mipi_dphy_timing timing; member
367 const struct mipi_dphy_timing *timing) in tegra_dsi_set_phy_timing() argument
371 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 | in tegra_dsi_set_phy_timing()
372 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 | in tegra_dsi_set_phy_timing()
373 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 | in tegra_dsi_set_phy_timing()
374 DSI_TIMING_FIELD(timing->hsprepare, period, 1); in tegra_dsi_set_phy_timing()
377 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 | in tegra_dsi_set_phy_timing()
378 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 | in tegra_dsi_set_phy_timing()
379 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 | in tegra_dsi_set_phy_timing()
380 DSI_TIMING_FIELD(timing->lpx, period, 1); in tegra_dsi_set_phy_timing()
[all …]
/linux-4.1.27/drivers/gpu/drm/msm/dsi/
Ddsi_phy.c40 struct dsi_dphy_timing timing; member
61 static void dsi_dphy_timing_calc_clk_zero(struct dsi_dphy_timing *timing, in dsi_dphy_timing_calc_clk_zero() argument
68 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
79 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; in dsi_dphy_timing_calc_clk_zero()
80 timing->clk_zero = clk_z + 8 - temp; in dsi_dphy_timing_calc_clk_zero()
83 static int dsi_dphy_timing_calc(struct dsi_dphy_timing *timing, in dsi_dphy_timing_calc() argument
103 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true); in dsi_dphy_timing_calc()
107 timing->hs_rqst = temp; in dsi_dphy_timing_calc()
109 timing->hs_rqst = max_t(s32, 0, temp - 2); in dsi_dphy_timing_calc()
112 dsi_dphy_timing_calc_clk_zero(timing, ui, coeff, pcnt2); in dsi_dphy_timing_calc()
[all …]
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
Dtiming.c33 u16 timing = 0x0000; in nvbios_timingTe() local
37 timing = nv_ro16(bios, bit_P.offset + 4); in nvbios_timingTe()
40 timing = nv_ro16(bios, bit_P.offset + 8); in nvbios_timingTe()
42 if (timing) { in nvbios_timingTe()
43 *ver = nv_ro08(bios, timing + 0); in nvbios_timingTe()
46 *hdr = nv_ro08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nv_ro08(bios, timing + 2); in nvbios_timingTe()
48 *len = nv_ro08(bios, timing + 3); in nvbios_timingTe()
51 return timing; in nvbios_timingTe()
53 *hdr = nv_ro08(bios, timing + 1); in nvbios_timingTe()
[all …]
DKbuild29 nvkm-y += nvkm/subdev/bios/timing.o
/linux-4.1.27/arch/avr32/mach-at32ap/
Dhsmc.c33 const struct smc_timing *timing) in smc_set_timing() argument
62 if (timing->ncs_read_setup > 0) in smc_set_timing()
63 config->ncs_read_setup = ns2cyc(timing->ncs_read_setup); in smc_set_timing()
65 if (timing->nrd_setup > 0) in smc_set_timing()
66 config->nrd_setup = ns2cyc(timing->nrd_setup); in smc_set_timing()
68 if (timing->ncs_write_setup > 0) in smc_set_timing()
69 config->ncs_write_setup = ns2cyc(timing->ncs_write_setup); in smc_set_timing()
71 if (timing->nwe_setup > 0) in smc_set_timing()
72 config->nwe_setup = ns2cyc(timing->nwe_setup); in smc_set_timing()
74 if (timing->ncs_read_pulse > 0) in smc_set_timing()
[all …]
/linux-4.1.27/drivers/video/fbdev/via/
Dvia_modesetting.c33 void via_set_primary_timing(const struct via_display_timing *timing) in via_set_primary_timing() argument
37 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
38 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
39 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
40 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
41 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
42 raw.hor_sync_end = timing->hor_sync_end / 8; in via_set_primary_timing()
43 raw.ver_total = timing->ver_total - 2; in via_set_primary_timing()
44 raw.ver_addr = timing->ver_addr - 1; in via_set_primary_timing()
45 raw.ver_blank_start = timing->ver_blank_start - 1; in via_set_primary_timing()
[all …]
Dhw.c1473 struct via_display_timing timing; in var_to_timing() local
1476 timing.hor_addr = cxres; in var_to_timing()
1477 timing.hor_sync_start = timing.hor_addr + var->right_margin + dx; in var_to_timing()
1478 timing.hor_sync_end = timing.hor_sync_start + var->hsync_len; in var_to_timing()
1479 timing.hor_total = timing.hor_sync_end + var->left_margin + dx; in var_to_timing()
1480 timing.hor_blank_start = timing.hor_addr + dx; in var_to_timing()
1481 timing.hor_blank_end = timing.hor_total - dx; in var_to_timing()
1482 timing.ver_addr = cyres; in var_to_timing()
1483 timing.ver_sync_start = timing.ver_addr + var->lower_margin + dy; in var_to_timing()
1484 timing.ver_sync_end = timing.ver_sync_start + var->vsync_len; in var_to_timing()
[all …]
Dvia_modesetting.h52 void via_set_primary_timing(const struct via_display_timing *timing);
53 void via_set_secondary_timing(const struct via_display_timing *timing);
Dlcd.c552 struct via_display_timing timing; in viafb_lcd_set_mode() local
570 timing = var_to_timing(&panel_var, panel_hres, panel_vres); in viafb_lcd_set_mode()
573 timing = var_to_timing(&panel_var, set_hres, set_vres); in viafb_lcd_set_mode()
581 via_set_primary_timing(&timing); in viafb_lcd_set_mode()
583 via_set_secondary_timing(&timing); in viafb_lcd_set_mode()
/linux-4.1.27/drivers/video/fbdev/
Dgbefb.c40 struct gbe_timing_info timing; member
420 static void gbefb_setup_flatpanel(struct gbe_timing_info *timing) in gbefb_setup_flatpanel() argument
426 (timing->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
428 (timing->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
436 timing->pll_m = 4; in gbefb_setup_flatpanel()
437 timing->pll_n = 1; in gbefb_setup_flatpanel()
438 timing->pll_p = 0; in gbefb_setup_flatpanel()
465 struct gbe_timing_info *timing) in compute_gbe_timing() argument
513 if (timing) { in compute_gbe_timing()
514 timing->width = var->xres; in compute_gbe_timing()
[all …]
Dpm2fb.c238 static u32 to3264(u32 timing, int bpp, int is64) in to3264() argument
242 timing *= 3; in to3264()
244 timing >>= 1; in to3264()
246 timing >>= 1; in to3264()
251 timing >>= 1; in to3264()
252 return timing; in to3264()
Damba-clcd.c558 struct display_timing timing; in clcdfb_of_get_dpi_panel_mode() local
561 err = of_get_display_timing(node, "panel-timing", &timing); in clcdfb_of_get_dpi_panel_mode()
565 videomode_from_timing(&timing, &video); in clcdfb_of_get_dpi_panel_mode()
/linux-4.1.27/drivers/gpu/drm/sti/
Dsti_awg_utils.c119 struct awg_timing *timing) in sti_awg_generate_code_data_enable_mode() argument
125 if (timing->trailing_lines > 0) { in sti_awg_generate_code_data_enable_mode()
127 val = timing->blanking_level; in sti_awg_generate_code_data_enable_mode()
131 val = timing->trailing_lines - 1; in sti_awg_generate_code_data_enable_mode()
136 if (timing->trailing_pixels > 0) { in sti_awg_generate_code_data_enable_mode()
138 val = timing->blanking_level; in sti_awg_generate_code_data_enable_mode()
142 val = timing->trailing_pixels - 1; in sti_awg_generate_code_data_enable_mode()
148 val = timing->blanking_level; in sti_awg_generate_code_data_enable_mode()
150 ret |= awg_generate_instr((timing->trailing_pixels > 0) ? SET : RPLSET, in sti_awg_generate_code_data_enable_mode()
153 if (timing->blanking_pixels > 0) { in sti_awg_generate_code_data_enable_mode()
[all …]
Dsti_dvo.c54 struct awg_timing *timing);
113 struct awg_timing timing; in dvo_awg_generate_code() local
118 timing.total_lines = mode->vtotal; in dvo_awg_generate_code()
119 timing.active_lines = mode->vdisplay; in dvo_awg_generate_code()
120 timing.blanking_lines = mode->vsync_start - mode->vdisplay; in dvo_awg_generate_code()
121 timing.trailing_lines = mode->vtotal - mode->vsync_start; in dvo_awg_generate_code()
122 timing.total_pixels = mode->htotal; in dvo_awg_generate_code()
123 timing.active_pixels = mode->hdisplay; in dvo_awg_generate_code()
124 timing.blanking_pixels = mode->hsync_start - mode->hdisplay; in dvo_awg_generate_code()
125 timing.trailing_pixels = mode->htotal - mode->hsync_start; in dvo_awg_generate_code()
[all …]
Dsti_awg_utils.h33 struct awg_timing *timing);
/linux-4.1.27/drivers/ide/
Dtriflex.c41 u16 timing = 0; in triflex_set_mode() local
48 timing = 0x0103; in triflex_set_mode()
51 timing = 0x0203; in triflex_set_mode()
54 timing = 0x0808; in triflex_set_mode()
59 timing = 0x0f0f; in triflex_set_mode()
62 timing = 0x0202; in triflex_set_mode()
65 timing = 0x0204; in triflex_set_mode()
68 timing = 0x0404; in triflex_set_mode()
71 timing = 0x0508; in triflex_set_mode()
74 timing = 0x0808; in triflex_set_mode()
[all …]
Damd74xx.c51 struct ide_timing *timing) in amd_set_speed() argument
56 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); in amd_set_speed()
60 ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1)); in amd_set_speed()
63 ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1)); in amd_set_speed()
66 case ATA_UDMA2: t = timing->udma ? (0xc0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break; in amd_set_speed()
67 …case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 2, 10)]) : 0x03; b… in amd_set_speed()
68 …case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 10)]) : 0x03; b… in amd_set_speed()
69 …case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 15)]) : 0x03; b… in amd_set_speed()
73 if (timing->udma) in amd_set_speed()
Dht6560b.c120 u8 select, timing; in ht6560b_dev_select() local
125 timing = HT_TIMING(drive); in ht6560b_dev_select()
135 if (select != current_select || timing != current_timing) { in ht6560b_dev_select()
137 current_timing = timing; in ht6560b_dev_select()
146 outb(timing, hwif->io_ports.device_addr); in ht6560b_dev_select()
150 drive->name, select, timing); in ht6560b_dev_select()
285 u8 timing; in ht6560b_set_pio_mode() local
294 timing = ht_pio2timings(drive, pio); in ht6560b_set_pio_mode()
299 config |= timing; in ht6560b_set_pio_mode()
304 printk("ht6560b: drive %s tuned to pio mode %#x timing=%#x\n", drive->name, pio, timing); in ht6560b_set_pio_mode()
Dvia82cxxx.c125 static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing) in via_set_speed() argument
134 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); in via_set_speed()
139 ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1)); in via_set_speed()
142 ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1)); in via_set_speed()
145 case ATA_UDMA2: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break; in via_set_speed()
146 case ATA_UDMA4: t = timing->udma ? (0xe8 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break; in via_set_speed()
147 case ATA_UDMA5: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; in via_set_speed()
148 case ATA_UDMA6: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; in via_set_speed()
160 if (timing->udma) { in via_set_speed()
Dit821x.c112 static void it821x_program(ide_drive_t *drive, u16 timing) in it821x_program() argument
122 conf = timing >> 8; in it821x_program()
124 conf = timing & 0xFF; in it821x_program()
138 static void it821x_program_udma(ide_drive_t *drive, u16 timing) in it821x_program_udma() argument
148 conf = timing >> 8; in it821x_program_udma()
150 conf = timing & 0xFF; in it821x_program_udma()
Dqd65xx.c180 static void qd_set_timing (ide_drive_t *drive, u8 timing) in qd_set_timing() argument
185 data |= timing; in qd_set_timing()
188 printk(KERN_DEBUG "%s: %#x\n", drive->name, timing); in qd_set_timing()
/linux-4.1.27/drivers/media/i2c/
Dbt819.c73 struct timing { struct
83 static struct timing timing_data[] = { argument
188 struct timing *timing = &timing_data[(decoder->norm & V4L2_STD_525_60) ? 1 : 0]; in bt819_init() local
191 (((timing->vdelay >> 8) & 0x03) << 6) | in bt819_init()
192 (((timing->vactive >> 8) & 0x03) << 4) | in bt819_init()
193 (((timing->hdelay >> 8) & 0x03) << 2) | in bt819_init()
194 ((timing->hactive >> 8) & 0x03); in bt819_init()
195 init[0x04 * 2 - 1] = timing->vdelay & 0xff; in bt819_init()
196 init[0x05 * 2 - 1] = timing->vactive & 0xff; in bt819_init()
197 init[0x06 * 2 - 1] = timing->hdelay & 0xff; in bt819_init()
[all …]
/linux-4.1.27/drivers/char/
Dbfin-otp.c90 u32 tp1, tp2, tp3, timing; in bfin_otp_init_timing() local
95 timing = tp1 | tp2 | tp3; in bfin_otp_init_timing()
96 if (bfrom_OtpCommand(OTP_INIT, timing)) in bfin_otp_init_timing()
99 return timing; in bfin_otp_init_timing()
107 static void bfin_otp_deinit_timing(u32 timing) in bfin_otp_deinit_timing() argument
111 bfrom_OtpCommand(OTP_INIT, timing & ~(-1 << 15)); in bfin_otp_deinit_timing()
123 u32 timing, page, base_flags, flags, ret; in bfin_otp_write() local
137 timing = bfin_otp_init_timing(); in bfin_otp_write()
138 if (timing == 0) { in bfin_otp_write()
167 bfin_otp_deinit_timing(timing); in bfin_otp_write()
[all …]
/linux-4.1.27/drivers/ata/
Dpata_triflex.c88 u32 timing = 0; in triflex_load_timing() local
100 timing = 0x0103;break; in triflex_load_timing()
102 timing = 0x0203;break; in triflex_load_timing()
104 timing = 0x0808;break; in triflex_load_timing()
108 timing = 0x0F0F;break; in triflex_load_timing()
110 timing = 0x0202;break; in triflex_load_timing()
112 timing = 0x0204;break; in triflex_load_timing()
114 timing = 0x0404;break; in triflex_load_timing()
116 timing = 0x0508;break; in triflex_load_timing()
118 timing = 0x0808;break; in triflex_load_timing()
[all …]
Dpata_cs5530.c88 u32 tuning, timing = 0; in cs5530_set_dmamode() local
96 timing = 0x00921250;break; in cs5530_set_dmamode()
98 timing = 0x00911140;break; in cs5530_set_dmamode()
100 timing = 0x00911030;break; in cs5530_set_dmamode()
102 timing = 0x00077771;break; in cs5530_set_dmamode()
104 timing = 0x00012121;break; in cs5530_set_dmamode()
106 timing = 0x00002020;break; in cs5530_set_dmamode()
111 timing |= (tuning & 0x80000000UL); in cs5530_set_dmamode()
113 iowrite32(timing, base + 0x04); in cs5530_set_dmamode()
115 if (timing & 0x00100000) in cs5530_set_dmamode()
[all …]
Dpata_sis.c341 u16 timing; in sis_old_set_dmamode() local
346 pci_read_config_word(pdev, drive_pci, &timing); in sis_old_set_dmamode()
351 timing &= ~0x870F; in sis_old_set_dmamode()
352 timing |= mwdma_bits[speed]; in sis_old_set_dmamode()
356 timing &= ~0x6000; in sis_old_set_dmamode()
357 timing |= udma_bits[speed]; in sis_old_set_dmamode()
359 pci_write_config_word(pdev, drive_pci, timing); in sis_old_set_dmamode()
380 u16 timing; in sis_66_set_dmamode() local
386 pci_read_config_word(pdev, drive_pci, &timing); in sis_66_set_dmamode()
391 timing &= ~0x870F; in sis_66_set_dmamode()
[all …]
Dpata_cmd640.c53 struct cmd640_reg *timing = ap->private_data; in cmd640_set_piomode() local
115 timing->reg58[adev->devno] = (t.active << 4) | t.recover; in cmd640_set_piomode()
133 struct cmd640_reg *timing = ap->private_data; in cmd640_qc_issue() local
135 if (ap->port_no != 0 && adev->devno != timing->last) { in cmd640_qc_issue()
136 pci_write_config_byte(pdev, DRWTIM23, timing->reg58[adev->devno]); in cmd640_qc_issue()
137 timing->last = adev->devno; in cmd640_qc_issue()
153 struct cmd640_reg *timing; in cmd640_port_start() local
155 timing = devm_kzalloc(&pdev->dev, sizeof(struct cmd640_reg), GFP_KERNEL); in cmd640_port_start()
156 if (timing == NULL) in cmd640_port_start()
158 timing->last = -1; /* Force a load */ in cmd640_port_start()
[all …]
Dpata_at32.c96 struct smc_timing timing; in pata_at32_setup_timing() local
101 memset(&timing, 0, sizeof(struct smc_timing)); in pata_at32_setup_timing()
104 timing.read_cycle = ata->cyc8b; in pata_at32_setup_timing()
107 timing.nrd_setup = ata->setup; in pata_at32_setup_timing()
108 timing.nrd_pulse = ata->act8b; in pata_at32_setup_timing()
109 timing.nrd_recover = ata->rec8b; in pata_at32_setup_timing()
112 smc_set_timing(smc, &timing); in pata_at32_setup_timing()
152 struct ata_timing timing; in pata_at32_set_piomode() local
158 ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0); in pata_at32_set_piomode()
165 ret = pata_at32_setup_timing(ap->dev, info, &timing); in pata_at32_set_piomode()
Dpata_sl82c105.c84 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); in sl82c105_configure_piomode() local
86 pci_write_config_word(pdev, timing, pio_timing[pio]); in sl82c105_configure_piomode()
88 pci_read_config_word(pdev, timing, &dummy); in sl82c105_configure_piomode()
121 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); in sl82c105_configure_dmamode() local
124 pci_write_config_word(pdev, timing, dma_timing[dma]); in sl82c105_configure_dmamode()
126 pci_read_config_word(pdev, timing, &dummy); in sl82c105_configure_dmamode()
Dpata_legacy.c99 unsigned long timing; member
656 u8 timing; in qdi65x0_set_piomode() local
668 timing = (recovery << 4) | active | 0x08; in qdi65x0_set_piomode()
669 ld_qdi->clock[adev->devno] = timing; in qdi65x0_set_piomode()
672 outb(timing, ld_qdi->timing + 2 * adev->devno); in qdi65x0_set_piomode()
674 outb(timing, ld_qdi->timing + 2 * ap->port_no); in qdi65x0_set_piomode()
678 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3); in qdi65x0_set_piomode()
698 outb(ld_qdi->clock[adev->devno], ld_qdi->timing + in qdi_qc_issue()
738 ld->timing = lp->private; in qdi_port()
792 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); in winbond_set_piomode() local
[all …]
Dpata_octeon_cf.c134 struct ata_timing timing; in octeon_cf_set_piomode() local
155 if (ata_timing_compute(dev, dev->pio_mode, &timing, T, T)) in octeon_cf_set_piomode()
158 t1 = timing.setup; in octeon_cf_set_piomode()
161 t2 = timing.active; in octeon_cf_set_piomode()
164 t2i = timing.act8b; in octeon_cf_set_piomode()
172 pause = (int)timing.cycle - (int)timing.active - in octeon_cf_set_piomode()
173 (int)timing.setup - trh; in octeon_cf_set_piomode()
237 const struct ata_timing *timing; in octeon_cf_set_dmamode() local
239 timing = ata_timing_find_mode(dev->dma_mode); in octeon_cf_set_dmamode()
240 T0 = timing->cycle; in octeon_cf_set_dmamode()
[all …]
Dpata_mpc52xx.c271 struct mpc52xx_ata_timings *timing = &priv->timings[dev]; in mpc52xx_ata_compute_pio_timings() local
286 timing->pio1 = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8) | (t2i); in mpc52xx_ata_compute_pio_timings()
287 timing->pio2 = (t4 << 24) | (t1 << 16) | (ta << 8); in mpc52xx_ata_compute_pio_timings()
333 struct mpc52xx_ata_timings *timing = &priv->timings[device]; in mpc52xx_ata_apply_timings() local
335 out_be32(&regs->pio1, timing->pio1); in mpc52xx_ata_apply_timings()
336 out_be32(&regs->pio2, timing->pio2); in mpc52xx_ata_apply_timings()
337 out_be32(&regs->mdma1, timing->mdma1); in mpc52xx_ata_apply_timings()
338 out_be32(&regs->mdma2, timing->mdma2); in mpc52xx_ata_apply_timings()
339 out_be32(&regs->udma1, timing->udma1); in mpc52xx_ata_apply_timings()
340 out_be32(&regs->udma2, timing->udma2); in mpc52xx_ata_apply_timings()
[all …]
Dpata_hpt37x.c32 u32 timing; member
216 return clocks->timing; in hpt37x_find_mode()
415 u32 reg, timing, mask; in hpt370_set_mode() local
435 timing = hpt37x_find_mode(ap, mode); in hpt370_set_mode()
438 reg = (reg & ~mask) | (timing & mask); in hpt370_set_mode()
509 u32 reg, timing, mask; in hpt372_set_mode() local
528 timing = hpt37x_find_mode(ap, mode); in hpt372_set_mode()
531 reg = (reg & ~mask) | (timing & mask); in hpt372_set_mode()
Dpata_hpt3x2n.c39 u32 timing; member
109 return clocks->timing; in hpt3x2n_find_mode()
186 u32 reg, timing, mask; in hpt3x2n_set_mode() local
205 timing = hpt3x2n_find_mode(ap, mode); in hpt3x2n_set_mode()
208 reg = (reg & ~mask) | (timing & mask); in hpt3x2n_set_mode()
Dpata_via.c513 u32 timing; in via_fixup() local
520 pci_read_config_dword(pdev, 0x50, &timing); in via_fixup()
521 timing |= 0x80008; in via_fixup()
522 pci_write_config_dword(pdev, 0x50, timing); in via_fixup()
526 pci_read_config_dword(pdev, 0x50, &timing); in via_fixup()
527 timing &= ~0x80008; in via_fixup()
528 pci_write_config_dword(pdev, 0x50, timing); in via_fixup()
Dpata_artop.c102 const u16 timing[2][5] = { in artop6210_load_piomode() local
108 pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]); in artop6210_load_piomode()
156 const u8 timing[2][5] = { in artop6260_load_piomode() local
162 pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]); in artop6260_load_piomode()
Dpata_at91.c265 struct ata_timing timing; in pata_at91_set_piomode() local
269 ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0); in pata_at91_set_piomode()
273 timing = *ata_timing_find_mode(XFER_PIO_0); in pata_at91_set_piomode()
275 set_smc_timing(ap->dev, adev, info, &timing); in pata_at91_set_piomode()
Dpata_it821x.c126 static void it821x_program(struct ata_port *ap, struct ata_device *adev, u16 timing) in it821x_program() argument
135 conf = timing >> 8; in it821x_program()
137 conf = timing & 0xFF; in it821x_program()
154 static void it821x_program_udma(struct ata_port *ap, struct ata_device *adev, u16 timing) in it821x_program_udma() argument
164 conf = timing >> 8; in it821x_program_udma()
166 conf = timing & 0xFF; in it821x_program_udma()
Dpata_hpt366.c32 u32 timing; member
128 return clocks->timing; in hpt36x_find_mode()
Dpata_ns87415.c56 int timing = 0x44 + 2 * unit; in ns87415_set_mode() local
72 pci_write_config_word(dev, timing, clocking); in ns87415_set_mode()
Dpata_samsung_cf.c108 struct ata_timing timing; in pata_s3c_set_piomode() local
121 ata_timing_compute(adev, adev->pio_mode, &timing, in pata_s3c_set_piomode()
124 piotime = pata_s3c_setup_timing(info, &timing); in pata_s3c_set_piomode()
Dahci_xgene.c360 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); in xgene_ahci_do_hardreset() local
377 rc = sata_link_hardreset(link, timing, deadline, online, in xgene_ahci_do_hardreset()
Dsata_highbank.c402 static const unsigned long timing[] = { 5, 100, 500}; in ahci_highbank_hardreset() local
422 rc = sata_link_hardreset(link, timing, deadline, &online, NULL); in ahci_highbank_hardreset()
/linux-4.1.27/drivers/mmc/host/
Ddw_mmc-exynos.c130 static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) in dw_mci_exynos_set_clksel_timing() argument
141 clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing; in dw_mci_exynos_set_clksel_timing()
225 static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing) in dw_mci_exynos_config_hs400() argument
240 if (timing == MMC_TIMING_MMC_HS400) { in dw_mci_exynos_config_hs400()
287 u32 timing = ios->timing, clksel; in dw_mci_exynos_set_ios() local
289 switch (timing) { in dw_mci_exynos_set_ios()
310 dw_mci_exynos_config_hs400(host, timing); in dw_mci_exynos_set_ios()
320 u32 timing[2]; in dw_mci_exynos_parse_dt() local
344 "samsung,dw-mshc-sdr-timing", timing, 2); in dw_mci_exynos_parse_dt()
348 priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); in dw_mci_exynos_parse_dt()
[all …]
Dsdhci.c1151 switch (host->timing) { in sdhci_get_preset_value()
1472 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) in sdhci_set_uhs_signaling() argument
1479 if ((timing == MMC_TIMING_MMC_HS200) || in sdhci_set_uhs_signaling()
1480 (timing == MMC_TIMING_UHS_SDR104)) in sdhci_set_uhs_signaling()
1482 else if (timing == MMC_TIMING_UHS_SDR12) in sdhci_set_uhs_signaling()
1484 else if (timing == MMC_TIMING_UHS_SDR25) in sdhci_set_uhs_signaling()
1486 else if (timing == MMC_TIMING_UHS_SDR50) in sdhci_set_uhs_signaling()
1488 else if ((timing == MMC_TIMING_UHS_DDR50) || in sdhci_set_uhs_signaling()
1489 (timing == MMC_TIMING_MMC_DDR52)) in sdhci_set_uhs_signaling()
1491 else if (timing == MMC_TIMING_MMC_HS400) in sdhci_set_uhs_signaling()
[all …]
Drtsx_pci_sdmmc.c978 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) in sd_set_timing() argument
985 switch (timing) { in sd_set_timing()
1067 sd_set_timing(host, ios->timing); in sdmmc_set_ios()
1072 switch (ios->timing) { in sdmmc_set_ios()
1291 switch (mmc->ios.timing) { in sdmmc_execute_tuning()
1312 if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) || in sdmmc_execute_tuning()
1313 (mmc->ios.timing == MMC_TIMING_UHS_SDR50)) in sdmmc_execute_tuning()
1315 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) in sdmmc_execute_tuning()
Ddw_mmc-rockchip.c54 ios->timing == MMC_TIMING_MMC_DDR52) in dw_mci_rk3288_set_ios()
Dsdhci.h495 unsigned timing; /* Current timing */ member
653 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
Dsdhci-msm.c359 !((ios.timing == MMC_TIMING_MMC_HS200) || in sdhci_msm_execute_tuning()
360 (ios.timing == MMC_TIMING_UHS_SDR104))) in sdhci_msm_execute_tuning()
Drtsx_usb_sdmmc.c1070 unsigned char timing, bool *ddr_mode) in sd_set_timing() argument
1079 switch (timing) { in sd_set_timing()
1148 sd_set_timing(host, ios->timing, &host->ddr_mode); in sdmmc_set_ios()
1153 switch (ios->timing) { in sdmmc_set_ios()
Dsdhci-esdhc-imx.c779 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) in esdhc_set_uhs_signaling() argument
785 switch (timing) { in esdhc_set_uhs_signaling()
810 esdhc_change_pinstate(host, timing); in esdhc_set_uhs_signaling()
/linux-4.1.27/drivers/pcmcia/
Dsa11xx_base.c81 struct soc_pcmcia_timing timing; in sa1100_pcmcia_set_mecr() local
86 soc_common_pcmcia_get_timing(skt, &timing); in sa1100_pcmcia_set_mecr()
88 bs_io = skt->ops->get_timing(skt, cpu_clock, timing.io); in sa1100_pcmcia_set_mecr()
89 bs_mem = skt->ops->get_timing(skt, cpu_clock, timing.mem); in sa1100_pcmcia_set_mecr()
90 bs_attr = skt->ops->get_timing(skt, cpu_clock, timing.attr); in sa1100_pcmcia_set_mecr()
146 struct soc_pcmcia_timing timing; in sa1100_pcmcia_show_timing() local
151 soc_common_pcmcia_get_timing(skt, &timing); in sa1100_pcmcia_show_timing()
153 p+=sprintf(p, "I/O : %u (%u)\n", timing.io, in sa1100_pcmcia_show_timing()
156 p+=sprintf(p, "attribute: %u (%u)\n", timing.attr, in sa1100_pcmcia_show_timing()
159 p+=sprintf(p, "common : %u (%u)\n", timing.mem, in sa1100_pcmcia_show_timing()
Dpxa2xx_base.c167 struct soc_pcmcia_timing timing; in pxa2xx_pcmcia_set_mcxx() local
170 soc_common_pcmcia_get_timing(skt, &timing); in pxa2xx_pcmcia_set_mcxx()
172 pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk); in pxa2xx_pcmcia_set_mcxx()
173 pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk); in pxa2xx_pcmcia_set_mcxx()
174 pxa2xx_pcmcia_set_mcio(sock, timing.io, clk); in pxa2xx_pcmcia_set_mcxx()
Dcistpl.c946 static u_char *parse_timing(u_char *p, u_char *q, cistpl_timing_t *timing) in parse_timing() argument
956 timing->wait = SPEED_CVT(*p); in parse_timing()
957 timing->waitscale = exponent[scale & 3]; in parse_timing()
959 timing->wait = 0; in parse_timing()
964 timing->ready = SPEED_CVT(*p); in parse_timing()
965 timing->rdyscale = exponent[scale & 7]; in parse_timing()
967 timing->ready = 0; in parse_timing()
972 timing->reserved = SPEED_CVT(*p); in parse_timing()
973 timing->rsvscale = exponent[scale]; in parse_timing()
975 timing->reserved = 0; in parse_timing()
[all …]
Dsoc_common.c98 struct soc_pcmcia_timing *timing) in soc_common_pcmcia_get_timing() argument
100 timing->io = in soc_common_pcmcia_get_timing()
102 timing->mem = in soc_common_pcmcia_get_timing()
104 timing->attr = in soc_common_pcmcia_get_timing()
/linux-4.1.27/Documentation/bus-devices/
Dti-gpmc.txt16 GPMC generic timing calculation:
25 generic timing routine was developed to achieve above requirements.
33 happen that timing as specified by peripheral datasheet is not present
34 in timing structure, in this scenario, try to correlate peripheral
35 timing to the one available. If that doesn't work, try to add a new
36 field as required by peripheral, educate generic timing routine to
41 Generic timing routine has been verified to work properly on
44 A word of caution: generic timing routine has been developed based
46 custom timing routines, a kind of reverse engineering without
48 in mainline having custom timing routine) and by simulation.
[all …]
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramgt215.c350 gt215_ram_timing_calc(struct nvkm_fb *pfb, u32 *timing) in gt215_ram_timing_calc() argument
375 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); in gt215_ram_timing_calc()
376 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in gt215_ram_timing_calc()
380 timing[2] = (T(CWL) - 1) << 24 | in gt215_ram_timing_calc()
384 timing[3] = (cur3 & 0x00ff0000) | in gt215_ram_timing_calc()
388 timing[4] = T(20) << 24 | in gt215_ram_timing_calc()
392 timing[5] = T(RFC) << 24 | in gt215_ram_timing_calc()
396 timing[6] = (0x5a + T(CL)) << 16 | in gt215_ram_timing_calc()
399 timing[7] = (cur7 & 0xff000000) | in gt215_ram_timing_calc()
402 timing[8] = cur8 & 0xffffff00; in gt215_ram_timing_calc()
[all …]
Dramnv50.c71 } ramcfg, timing; in nv50_ram_calc() local
100 timing.data = nvbios_timingEe(bios, strap, &ver, &hdr, in nv50_ram_calc()
102 if (!timing.data || ver != 0x10 || hdr < 0x12) { in nv50_ram_calc()
105 strap, timing.data, ver, hdr); in nv50_ram_calc()
109 timing.data = 0; in nv50_ram_calc()
173 ram_mask(hwsq, timing[3], 0x00000000, 0x00000000); /*XXX*/ in nv50_ram_calc()
174 ram_mask(hwsq, timing[1], 0x00000000, 0x00000000); /*XXX*/ in nv50_ram_calc()
175 ram_mask(hwsq, timing[6], 0x00000000, 0x00000000); /*XXX*/ in nv50_ram_calc()
176 ram_mask(hwsq, timing[7], 0x00000000, 0x00000000); /*XXX*/ in nv50_ram_calc()
177 ram_mask(hwsq, timing[8], 0x00000000, 0x00000000); /*XXX*/ in nv50_ram_calc()
[all …]
Dgddr3.c84 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; in nvkm_gddr3_calc()
85 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; in nvkm_gddr3_calc()
86 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_gddr3_calc()
Dsddr3.c86 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; in nvkm_sddr3_calc()
87 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; in nvkm_sddr3_calc()
88 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_sddr3_calc()
Dgddr5.c57 WL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; in nvkm_gddr5_calc()
58 CL = (ram->next->bios.timing[1] & 0x0000001f); in nvkm_gddr5_calc()
59 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_gddr5_calc()
Dramgk104.c459 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]); in gk104_ram_calc_gddr5()
460 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]); in gk104_ram_calc_gddr5()
461 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]); in gk104_ram_calc_gddr5()
462 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]); in gk104_ram_calc_gddr5()
463 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]); in gk104_ram_calc_gddr5()
464 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]); in gk104_ram_calc_gddr5()
465 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]); in gk104_ram_calc_gddr5()
466 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]); in gk104_ram_calc_gddr5()
467 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]); in gk104_ram_calc_gddr5()
468 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]); in gk104_ram_calc_gddr5()
[all …]
Dsddr2.c72 CL = (ram->next->bios.timing[1] & 0x0000001f); in nvkm_sddr2_calc()
73 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_sddr2_calc()
Dramgf100.c138 } rammap, ramcfg, timing; in gf100_ram_calc() local
168 timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size, in gf100_ram_calc()
170 if (!timing.data || ver != 0x10 || timing.size < 0x19) { in gf100_ram_calc()
175 timing.data = 0; in gf100_ram_calc()
/linux-4.1.27/Documentation/devicetree/bindings/mips/cavium/
Dbootbus.txt32 - cavium,t-adr: A cell specifying the ADR timing (in nS).
34 - cavium,t-ce: A cell specifying the CE timing (in nS).
36 - cavium,t-oe: A cell specifying the OE timing (in nS).
38 - cavium,t-we: A cell specifying the WE timing (in nS).
40 - cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).
42 - cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).
44 - cavium,t-pause: A cell specifying the PAUSE timing (in nS).
46 - cavium,t-wait: A cell specifying the WAIT timing (in nS).
48 - cavium,t-page: A cell specifying the PAGE timing (in nS).
50 - cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).
/linux-4.1.27/drivers/iio/humidity/
Ddht11.c76 static unsigned char dht11_decode_byte(int *timing, int threshold) in dht11_decode_byte() argument
83 if (timing[i] >= threshold) in dht11_decode_byte()
92 int i, t, timing[DHT11_BITS_PER_READ], threshold, in dht11_decode() local
117 timing[i] = t / timeres; in dht11_decode()
120 hum_int = dht11_decode_byte(timing, threshold); in dht11_decode()
121 hum_dec = dht11_decode_byte(&timing[8], threshold); in dht11_decode()
122 temp_int = dht11_decode_byte(&timing[16], threshold); in dht11_decode()
123 temp_dec = dht11_decode_byte(&timing[24], threshold); in dht11_decode()
124 checksum = dht11_decode_byte(&timing[32], threshold); in dht11_decode()
/linux-4.1.27/drivers/mtd/nand/
Dcafe_nand.c90 static int timing[3]; variable
91 module_param_array(timing, int, &numtimings, 0644);
647 timing[0], timing[1], timing[2]); in cafe_nand_probe()
649 timing[0] = cafe_readl(cafe, NAND_TIMING1); in cafe_nand_probe()
650 timing[1] = cafe_readl(cafe, NAND_TIMING2); in cafe_nand_probe()
651 timing[2] = cafe_readl(cafe, NAND_TIMING3); in cafe_nand_probe()
653 if (timing[0] | timing[1] | timing[2]) { in cafe_nand_probe()
655 timing[0], timing[1], timing[2]); in cafe_nand_probe()
658 timing[0] = timing[1] = timing[2] = 0xffffffff; in cafe_nand_probe()
666 cafe_writel(cafe, timing[0], NAND_TIMING1); in cafe_nand_probe()
[all …]
Dpxa3xx_nand.c246 static struct pxa3xx_nand_timing timing[] = { variable
254 { "DEFAULT FLASH", 0, 0, 2048, 8, 8, 0, &timing[0] },
255 { "64MiB 16-bit", 0x46ec, 32, 512, 16, 16, 4096, &timing[1] },
256 { "256MiB 8-bit", 0xdaec, 64, 2048, 8, 8, 2048, &timing[1] },
257 { "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] },
258 { "128MiB 8-bit", 0xa12c, 64, 2048, 8, 8, 1024, &timing[2] },
259 { "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, 1024, &timing[2] },
260 { "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, 4096, &timing[2] },
261 { "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, 4096, &timing[2] },
262 { "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, &timing[3] },
[all …]
Ddavinci_nand.c77 struct davinci_aemif_timing *timing; member
676 info->timing = pdata->timing; in nand_davinci_probe()
Dfsl_ifc_nand.c452 int timing = IFC_FIR_OP_RB; in fsl_ifc_cmdfunc() local
454 timing = IFC_FIR_OP_RBCD; in fsl_ifc_cmdfunc()
458 (timing << IFC_NAND_FIR0_OP2_SHIFT), in fsl_ifc_cmdfunc()
/linux-4.1.27/Documentation/devicetree/bindings/media/xilinx/
Dxlnx,v-tc.txt4 The Video Timing Controller is a general purpose video timing generator and
13 - clocks: Must contain a clock specifier for the VTC core and timing
18 - xlnx,detector: The VTC has a timing detector
19 - xlnx,generator: The VTC has a timing generator
Dxlnx,v-tpg.txt29 - timing-gpios: Specifier for a GPIO that controls the timing mux at the TPG
33 The xlnx,vtc and timing-gpios properties are mandatory when the TPG is
44 timing-gpios = <&ps7_gpio_0 55 GPIO_ACTIVE_LOW>;
/linux-4.1.27/sound/pci/
Dsis7019.c95 struct voice *timing; member
344 if (!voice->timing) in sis_interrupt()
406 if (voice->timing) { in sis_free_voice()
408 voice->timing->flags &= ~(VOICE_IN_USE | VOICE_SSO_TIMING | in sis_free_voice()
410 voice->timing = NULL; in sis_free_voice()
466 if (needed && !voice->timing) { in sis_alloc_timing_voice()
468 voice->timing = __sis_alloc_playback_voice(sis); in sis_alloc_timing_voice()
469 if (voice->timing) in sis_alloc_timing_voice()
472 if (!voice->timing) in sis_alloc_timing_voice()
474 voice->timing->substream = substream; in sis_alloc_timing_voice()
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/mmc/
Dexynos-dw-mshc.txt30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
35 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
39 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
42 Notes for the sdr-timing and ddr-timing values:
48 Valid values for SDR and DDR CIU clock timing for Exynos5250:
88 samsung,dw-mshc-sdr-timing = <2 3>;
89 samsung,dw-mshc-ddr-timing = <1 2>;
90 samsung,dw-mshc-hs400-timing = <0 2>;
Dmmc.txt27 - cap-sd-highspeed: SD high-speed timing is supported
28 - cap-mmc-highspeed: MMC high-speed timing is supported
/linux-4.1.27/arch/arm/boot/dts/
Dexynos5410-smdk5410.dts47 samsung,dw-mshc-sdr-timing = <2 3>;
48 samsung,dw-mshc-ddr-timing = <1 2>;
58 samsung,dw-mshc-sdr-timing = <2 3>;
59 samsung,dw-mshc-ddr-timing = <1 2>;
Dtegra124-nyan-blaze-emc.dtsi6 timing-12750000 {
12 timing-20400000 {
18 timing-40800000 {
24 timing-68000000 {
30 timing-102000000 {
36 timing-204000000 {
42 timing-300000000 {
48 timing-396000000 {
55 timing-600000000 {
61 timing-792000000 {
[all …]
Dtegra124-jetson-tk1-emc.dtsi6 timing-12750000 {
12 timing-20400000 {
18 timing-40800000 {
24 timing-68000000 {
30 timing-102000000 {
36 timing-204000000 {
42 timing-300000000 {
48 timing-396000000 {
54 timing-528000000 {
60 timing-600000000 {
[all …]
Dtegra124-nyan-big-emc.dtsi6 timing-12750000 {
12 timing-20400000 {
18 timing-40800000 {
24 timing-68000000 {
30 timing-102000000 {
36 timing-204000000 {
42 timing-300000000 {
48 timing-396000000 {
55 timing-600000000 {
61 timing-792000000 {
[all …]
Dexynos5260-xyref5260.dts76 samsung,dw-mshc-sdr-timing = <0 4>;
77 samsung,dw-mshc-ddr-timing = <0 2>;
89 samsung,dw-mshc-sdr-timing = <2 3>;
90 samsung,dw-mshc-ddr-timing = <1 2>;
Dimx27-eukrea-cpuimx27.dtsi112 fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>;
120 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
133 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
146 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
159 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
Dexynos5420-smdk5420.dts81 samsung,dw-mshc-sdr-timing = <0 4>;
82 samsung,dw-mshc-ddr-timing = <0 2>;
83 samsung,dw-mshc-hs400-timing = <0 2>;
96 samsung,dw-mshc-sdr-timing = <2 3>;
97 samsung,dw-mshc-ddr-timing = <1 2>;
120 timing0: timing@0 {
Dexynos5250-smdk5250.dts100 timing0: timing@0 {
351 samsung,dw-mshc-sdr-timing = <2 3>;
352 samsung,dw-mshc-ddr-timing = <1 2>;
364 samsung,dw-mshc-sdr-timing = <2 3>;
365 samsung,dw-mshc-ddr-timing = <1 2>;
Dimx1-apf9328.dts57 fsl,weim-cs-timing = <0x00330e04 0x00000d01>;
72 fsl,weim-cs-timing = <0x0000c700 0x19190d01>;
Dexynos5420-arndale-octa.dts55 samsung,dw-mshc-sdr-timing = <0 4>;
56 samsung,dw-mshc-ddr-timing = <0 2>;
68 samsung,dw-mshc-sdr-timing = <2 3>;
69 samsung,dw-mshc-ddr-timing = <1 2>;
Dexynos5422-odroidxu3.dts312 samsung,dw-mshc-sdr-timing = <0 4>;
313 samsung,dw-mshc-ddr-timing = <0 2>;
324 samsung,dw-mshc-sdr-timing = <0 4>;
325 samsung,dw-mshc-ddr-timing = <0 2>;
Dexynos5250-arndale.dts136 timing0: timing@0 {
527 samsung,dw-mshc-sdr-timing = <2 3>;
528 samsung,dw-mshc-ddr-timing = <1 2>;
541 samsung,dw-mshc-sdr-timing = <2 3>;
542 samsung,dw-mshc-ddr-timing = <1 2>;
Dexynos5250-snow.dts539 samsung,dw-mshc-sdr-timing = <2 3>;
540 samsung,dw-mshc-ddr-timing = <1 2>;
552 samsung,dw-mshc-sdr-timing = <2 3>;
553 samsung,dw-mshc-ddr-timing = <1 2>;
573 samsung,dw-mshc-sdr-timing = <2 3>;
574 samsung,dw-mshc-ddr-timing = <1 2>;
Dr8a77xx-aa104xd12-panel.dtsi18 panel-timing {
Datlas6-evb.dts74 timing = <0x88>;
Dexynos5420-peach-pit.dts700 samsung,dw-mshc-sdr-timing = <0 4>;
701 samsung,dw-mshc-ddr-timing = <0 2>;
702 samsung,dw-mshc-hs400-timing = <0 2>;
718 samsung,dw-mshc-sdr-timing = <0 1>;
719 samsung,dw-mshc-ddr-timing = <0 2>;
736 samsung,dw-mshc-sdr-timing = <2 3>;
737 samsung,dw-mshc-ddr-timing = <1 2>;
Dexynos5800-peach-pi.dts663 samsung,dw-mshc-sdr-timing = <0 4>;
664 samsung,dw-mshc-ddr-timing = <0 2>;
665 samsung,dw-mshc-hs400-timing = <0 2>;
681 samsung,dw-mshc-sdr-timing = <0 1>;
682 samsung,dw-mshc-ddr-timing = <0 2>;
699 samsung,dw-mshc-sdr-timing = <2 3>;
700 samsung,dw-mshc-ddr-timing = <1 2>;
Domap4-var-dvk-om44.dts26 panel-timing {
Dexynos5250-spring.dts436 samsung,dw-mshc-sdr-timing = <2 3>;
437 samsung,dw-mshc-ddr-timing = <1 2>;
454 samsung,dw-mshc-sdr-timing = <2 3>;
455 samsung,dw-mshc-ddr-timing = <1 2>;
Dimx27-phytec-phycore-som.dtsi335 fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>;
345 fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>;
Dexynos4412-origen.dts144 samsung,dw-mshc-sdr-timing = <2 3>;
145 samsung,dw-mshc-ddr-timing = <1 2>;
164 timing0: timing {
Domap-zoom-common.dtsi14 * REVISIT: Add timing support from slls644g.pdf
Dimx1-ads.dts89 fsl,weim-cs-timing = <0x00003e00 0x00000801>;
Domap3-thunder.dts102 panel-timing {
Dexynos4412-odroid-common.dtsi97 samsung,dw-mshc-sdr-timing = <2 3>;
98 samsung,dw-mshc-ddr-timing = <1 2>;
Domap3-ha-lcd.dts138 panel-timing {
Dexynos3250-rinato.dts183 timing-0 {
584 samsung,dw-mshc-sdr-timing = <0 1>;
585 samsung,dw-mshc-ddr-timing = <1 2>;
Ds5pv210-smdkv210.dts200 timing0: timing@0 {
Domap3-overo-common-lcd43.dtsi113 panel-timing {
/linux-4.1.27/include/linux/mmc/
Dhost.h53 unsigned char timing; /* timing specification used */ member
491 return card->host->ios.timing == MMC_TIMING_SD_HS || in mmc_card_hs()
492 card->host->ios.timing == MMC_TIMING_MMC_HS; in mmc_card_hs()
497 return card->host->ios.timing >= MMC_TIMING_UHS_SDR12 && in mmc_card_uhs()
498 card->host->ios.timing <= MMC_TIMING_UHS_DDR50; in mmc_card_uhs()
503 return card->host->ios.timing == MMC_TIMING_MMC_HS200; in mmc_card_hs200()
508 return card->host->ios.timing == MMC_TIMING_MMC_DDR52; in mmc_card_ddr52()
513 return card->host->ios.timing == MMC_TIMING_MMC_HS400; in mmc_card_hs400()
Ddw_mmc.h146 unsigned char timing; member
/linux-4.1.27/Documentation/devicetree/bindings/video/
Dpanel-dpi.txt12 - "panel-timing" containing video timings
13 (Documentation/devicetree/bindings/video/display-timing.txt)
29 panel-timing {
Ddisplay-timing.txt1 display-timing bindings
14 timing subnode
19 - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters
21 vfront-porch, vback-porch, vsync-len: vertical display timing parameters in
99 timing1: timing {
Dexynos7-decon.txt33 - i80-if-timings: timing configuration for lcd i80 interface support.
37 - display-timings: timing settings for DECON, as described in document [1].
41 [1]: Documentation/devicetree/bindings/video/display-timing.txt
Dsamsung-fimd.txt44 - display-timings: timing settings for FIMD, as described in document [1].
48 - i80-if-timings: timing configuration for lcd i80 interface support.
85 [1]: Documentation/devicetree/bindings/video/display-timing.txt
Dwm,wm8505-fb.txt10 - display-timings: see display-timing.txt for information
Dvia,vt8500-fb.txt11 - display-timings: see display-timing.txt for information
Dcirrus,clps711x-fb.txt9 Documentation/devicetree/bindings/video/display-timing.txt.
Dfsl,imx-fb.txt12 Documentation/devicetree/bindings/video/display-timing.txt
Datmel,lcdc.txt22 - default-mode: a videomode within the display with timing parameters
Dexynos_dp.txt53 Documentation/devicetree/bindings/video/display-timing.txt
Darm,pl11x.txt98 panel-timing {
/linux-4.1.27/arch/arm64/boot/dts/exynos/
Dexynos7-espresso.dts64 samsung,dw-mshc-sdr-timing = <0 4>;
65 samsung,dw-mshc-ddr-timing = <0 2>;
78 samsung,dw-mshc-sdr-timing = <2 3>;
79 samsung,dw-mshc-ddr-timing = <1 2>;
/linux-4.1.27/drivers/media/platform/omap3isp/
Dispcsi2.c359 struct isp_csi2_timing_cfg *timing) in csi2_timing_config() argument
365 if (timing->force_rx_mode) in csi2_timing_config()
366 reg |= ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum); in csi2_timing_config()
368 reg &= ~ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum); in csi2_timing_config()
370 if (timing->stop_state_16x) in csi2_timing_config()
371 reg |= ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum); in csi2_timing_config()
373 reg &= ~ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum); in csi2_timing_config()
375 if (timing->stop_state_4x) in csi2_timing_config()
376 reg |= ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum); in csi2_timing_config()
378 reg &= ~ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum); in csi2_timing_config()
[all …]
Dispcsi2.h141 struct isp_csi2_timing_cfg timing[2]; member
/linux-4.1.27/drivers/cpufreq/
Dcris-etraxfs-cpufreq.c80 reg_bif_core_rw_sdram_timing timing = in cris_sdram_freq_notifier() local
82 timing.cpd = (freqs->new == 200000 ? 0 : 1); in cris_sdram_freq_notifier()
86 REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing); in cris_sdram_freq_notifier()
Dcris-artpec3-cpufreq.c86 REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing); in cris_sdram_freq_notifier()
/linux-4.1.27/drivers/video/fbdev/exynos/
Dexynos_mipi_dsi_common.c715 struct fb_videomode *timing; in exynos_mipi_dsi_set_display_mode() local
718 timing = (struct fb_videomode *)dsim_pd->lcd_panel_info; in exynos_mipi_dsi_set_display_mode()
725 timing->lower_margin, in exynos_mipi_dsi_set_display_mode()
726 timing->upper_margin); in exynos_mipi_dsi_set_display_mode()
728 timing->right_margin, in exynos_mipi_dsi_set_display_mode()
729 timing->left_margin); in exynos_mipi_dsi_set_display_mode()
731 timing->vsync_len, in exynos_mipi_dsi_set_display_mode()
732 timing->hsync_len); in exynos_mipi_dsi_set_display_mode()
736 exynos_mipi_dsi_set_main_disp_resol(dsim, timing->xres, in exynos_mipi_dsi_set_display_mode()
737 timing->yres); in exynos_mipi_dsi_set_display_mode()
[all …]
/linux-4.1.27/drivers/media/rc/img-ir/
Dimg-ir-hw.c81 static void img_ir_symbol_timing_preprocess(struct img_ir_symbol_timing *timing, in img_ir_symbol_timing_preprocess() argument
84 img_ir_timing_preprocess(&timing->pulse, unit); in img_ir_symbol_timing_preprocess()
85 img_ir_timing_preprocess(&timing->space, unit); in img_ir_symbol_timing_preprocess()
113 static void img_ir_symbol_timing_defaults(struct img_ir_symbol_timing *timing, in img_ir_symbol_timing_defaults() argument
116 img_ir_timing_defaults(&timing->pulse, &defaults->pulse); in img_ir_symbol_timing_defaults()
117 img_ir_timing_defaults(&timing->space, &defaults->space); in img_ir_symbol_timing_defaults()
207 static u32 img_ir_symbol_timing(const struct img_ir_symbol_timing *timing, in img_ir_symbol_timing() argument
215 hw_period.min = timing->pulse.min + timing->space.min; in img_ir_symbol_timing()
216 hw_period.max = timing->pulse.max + timing->space.max; in img_ir_symbol_timing()
219 img_ir_timing_range_convert(&hw_pulse, &timing->pulse, in img_ir_symbol_timing()
[all …]
/linux-4.1.27/drivers/iio/light/
Dtcs3414.c59 u8 timing; member
158 *val2 = tcs3414_times[data->timing & TCS3414_INTEG_MASK] * 1000; in tcs3414_read_raw()
189 data->timing &= ~TCS3414_INTEG_MASK; in tcs3414_write_raw()
190 data->timing |= i; in tcs3414_write_raw()
193 data->timing); in tcs3414_write_raw()
321 data->timing = TCS3414_INTEG_12MS; /* free running */ in tcs3414_probe()
323 data->timing); in tcs3414_probe()
Dtsl2563.c243 static int adc_shiftbits(u8 timing) in adc_shiftbits() argument
247 switch (timing & TSL2563_TIMING_MASK) { in adc_shiftbits()
259 if (!(timing & TSL2563_TIMING_GAIN16)) in adc_shiftbits()
266 static u32 normalize_adc(u16 adc, u8 timing) in normalize_adc() argument
268 return adc << adc_shiftbits(timing); in normalize_adc()
/linux-4.1.27/drivers/gpu/drm/rcar-du/
Drcar_du_lvdscon.c94 struct display_timing timing; in rcar_du_lvds_connector_init() local
101 ret = of_get_display_timing(np, "panel-timing", &timing); in rcar_du_lvds_connector_init()
105 videomode_from_timing(&timing, &lvdscon->panel.mode); in rcar_du_lvds_connector_init()
/linux-4.1.27/drivers/net/wireless/iwlwifi/dvm/
Drxon.c304 memset(&ctx->timing, 0, sizeof(struct iwl_rxon_time_cmd)); in iwl_send_rxon_timing()
306 ctx->timing.timestamp = cpu_to_le64(priv->timestamp); in iwl_send_rxon_timing()
307 ctx->timing.listen_interval = cpu_to_le16(conf->listen_interval); in iwl_send_rxon_timing()
315 ctx->timing.atim_window = 0; in iwl_send_rxon_timing()
322 ctx->timing.beacon_interval = in iwl_send_rxon_timing()
323 priv->contexts[IWL_RXON_CTX_BSS].timing.beacon_interval; in iwl_send_rxon_timing()
324 beacon_int = le16_to_cpu(ctx->timing.beacon_interval); in iwl_send_rxon_timing()
331 ctx->timing.beacon_interval = in iwl_send_rxon_timing()
332 priv->contexts[IWL_RXON_CTX_PAN].timing.beacon_interval; in iwl_send_rxon_timing()
333 beacon_int = le16_to_cpu(ctx->timing.beacon_interval); in iwl_send_rxon_timing()
[all …]
Ddevices.c415 u16 beacon_interval = le16_to_cpu(ctx->timing.beacon_interval); in iwl5000_hw_channel_switch()
576 u16 beacon_interval = le16_to_cpu(ctx->timing.beacon_interval); in iwl6000_hw_channel_switch()
/linux-4.1.27/drivers/gpu/drm/
Ddrm_edid.c1493 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1817 struct detailed_timing *timing, in drm_mode_detailed() argument
1821 struct detailed_pixel_timing *pt = &timing->data.pixel_data; in drm_mode_detailed()
1863 timing->pixel_clock = cpu_to_le16(1088); in drm_mode_detailed()
1865 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; in drm_mode_detailed()
1966 struct detailed_timing *timing) in mode_in_range() argument
1969 u8 *t = (u8 *)timing; in mode_in_range()
2012 struct detailed_timing *timing) in drm_dmt_modes_for_range() argument
2019 if (mode_in_range(drm_dmt_modes + i, edid, timing) && in drm_dmt_modes_for_range()
2047 struct detailed_timing *timing) in drm_gtf_modes_for_range() argument
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/bus/
Dimx-weim.txt49 - fsl,weim-cs-timing: The timing array, contains timing values for the
79 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
/linux-4.1.27/drivers/mmc/core/
Dsdio.c473 unsigned int bus_speed, timing; in sdio_set_bus_speed_mode() local
485 timing = MMC_TIMING_UHS_SDR12; in sdio_set_bus_speed_mode()
489 timing = MMC_TIMING_UHS_SDR104; in sdio_set_bus_speed_mode()
495 timing = MMC_TIMING_UHS_DDR50; in sdio_set_bus_speed_mode()
502 timing = MMC_TIMING_UHS_SDR50; in sdio_set_bus_speed_mode()
509 timing = MMC_TIMING_UHS_SDR25; in sdio_set_bus_speed_mode()
517 timing = MMC_TIMING_UHS_SDR12; in sdio_set_bus_speed_mode()
533 mmc_set_timing(card->host, timing); in sdio_set_bus_speed_mode()
569 ((card->host->ios.timing == MMC_TIMING_UHS_SDR50) || in mmc_sdio_init_uhs_card()
570 (card->host->ios.timing == MMC_TIMING_UHS_SDR104))) in mmc_sdio_init_uhs_card()
Dsd.c487 unsigned int timing = 0; in sd_set_bus_speed_mode() local
491 timing = MMC_TIMING_UHS_SDR104; in sd_set_bus_speed_mode()
495 timing = MMC_TIMING_UHS_DDR50; in sd_set_bus_speed_mode()
499 timing = MMC_TIMING_UHS_SDR50; in sd_set_bus_speed_mode()
503 timing = MMC_TIMING_UHS_SDR25; in sd_set_bus_speed_mode()
507 timing = MMC_TIMING_UHS_SDR12; in sd_set_bus_speed_mode()
522 mmc_set_timing(card->host, timing); in sd_set_bus_speed_mode()
664 (card->host->ios.timing == MMC_TIMING_UHS_SDR50 || in mmc_sd_init_uhs_card()
665 card->host->ios.timing == MMC_TIMING_UHS_DDR50 || in mmc_sd_init_uhs_card()
666 card->host->ios.timing == MMC_TIMING_UHS_SDR104)) { in mmc_sd_init_uhs_card()
[all …]
Ddebugfs.c119 switch (ios->timing) { in mmc_ios_show()
151 seq_printf(s, "timing spec:\t%u (%s)\n", ios->timing, str); in mmc_ios_show()
Dcore.h51 void mmc_set_timing(struct mmc_host *host, unsigned int timing);
/linux-4.1.27/drivers/staging/media/omap4iss/
Diss_csi2.c367 struct iss_csi2_timing_cfg *timing) in csi2_timing_config() argument
373 if (timing->force_rx_mode) in csi2_timing_config()
378 if (timing->stop_state_16x) in csi2_timing_config()
383 if (timing->stop_state_4x) in csi2_timing_config()
389 reg |= timing->stop_state_counter << in csi2_timing_config()
532 struct iss_csi2_timing_cfg *timing = &csi2->timing[0]; in csi2_configure() local
556 timing->force_rx_mode = 1; in csi2_configure()
557 timing->stop_state_16x = 1; in csi2_configure()
558 timing->stop_state_4x = 1; in csi2_configure()
559 timing->stop_state_counter = 0x1ff; in csi2_configure()
[all …]
Diss_csi2.h144 struct iss_csi2_timing_cfg timing[2]; member
/linux-4.1.27/drivers/media/platform/omap/
Domap_vout.c449 struct omap_video_timings *timing; in omapvid_init() local
462 timing = &dssdev->panel.timings; in omapvid_init()
474 posy = (timing->y_res - win->w.width) - win->w.left; in omapvid_init()
479 posx = (timing->x_res - win->w.width) - win->w.left; in omapvid_init()
480 posy = (timing->y_res - win->w.height) - win->w.top; in omapvid_init()
488 posx = (timing->x_res - win->w.height) - win->w.top; in omapvid_init()
1095 struct omap_video_timings *timing; in vidioc_try_fmt_vid_out() local
1107 timing = &dssdev->panel.timings; in vidioc_try_fmt_vid_out()
1109 vout->fbuf.fmt.height = timing->y_res; in vidioc_try_fmt_vid_out()
1110 vout->fbuf.fmt.width = timing->x_res; in vidioc_try_fmt_vid_out()
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/lpddr2/
Dlpddr2-timings.txt1 * AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
10 The following properties represent AC timing parameters from the memory
Dlpddr2.txt20 timing parameters of the DDR device in terms of number of clock cycles.
36 "lpddr2-timings" provides AC timing parameters of the device for
/linux-4.1.27/Documentation/devicetree/bindings/panel/
Dsamsung,s6e8aa0.txt24 [1]: Documentation/devicetree/bindings/video/display-timing.txt
44 timing0: timing-0 {
Dsamsung,ld9040.txt23 [1]: Documentation/devicetree/bindings/video/display-timing.txt
44 timing {
/linux-4.1.27/drivers/media/pci/zoran/
Dzoran.h48 #define BUZ_MAX_WIDTH (zr->timing->Wa)
49 #define BUZ_MAX_HEIGHT (zr->timing->Ha)
289 struct tvnorm *timing; member
Dzoran_device.c349 tvn = zr->timing; in zr36057_set_vfe()
728 tvn = zr->timing; in zr36057_set_jpg()
1014 zr->codec->set_video(zr->codec, zr->timing, &cap, in zr36057_enable_jpg()
1022 zr->vfe->set_video(zr->vfe, zr->timing, &cap, in zr36057_enable_jpg()
1048 zr->vfe->set_video(zr->vfe, zr->timing, &cap, in zr36057_enable_jpg()
1053 zr->codec->set_video(zr->codec, zr->timing, &cap, in zr36057_enable_jpg()
Dzoran_card.c1004 zr->timing = zr->card.tvn[0]; in zr36057_init()
1007 zr->timing = zr->card.tvn[1]; in zr36057_init()
1010 zr->timing = zr->card.tvn[2]; in zr36057_init()
1012 if (zr->timing == NULL) { in zr36057_init()
1018 zr->timing = zr->card.tvn[0]; in zr36057_init()
/linux-4.1.27/drivers/i2c/busses/
Di2c-img-scb.c1106 struct img_i2c_timings timing; in img_i2c_init() local
1132 timing = timings[0]; in img_i2c_init()
1135 timing = timings[i]; in img_i2c_init()
1186 tckh = timing.tckh / clk_period; in img_i2c_init()
1187 if (timing.tckh % clk_period) in img_i2c_init()
1208 tsdh = timing.tsdh / clk_period; in img_i2c_init()
1209 if (timing.tsdh % clk_period) in img_i2c_init()
1222 data = timing.tpl / clk_period; in img_i2c_init()
1228 data = timing.tph / clk_period; in img_i2c_init()
1237 data = timing.tp2s / clk_period; in img_i2c_init()
/linux-4.1.27/drivers/usb/dwc3/
Dep0.c602 struct timing { in dwc3_ep0_set_sel_cmpl() struct
607 } __packed timing; in dwc3_ep0_set_sel_cmpl() local
611 memcpy(&timing, req->buf, sizeof(timing)); in dwc3_ep0_set_sel_cmpl()
613 dwc->u1sel = timing.u1sel; in dwc3_ep0_set_sel_cmpl()
614 dwc->u1pel = timing.u1pel; in dwc3_ep0_set_sel_cmpl()
615 dwc->u2sel = le16_to_cpu(timing.u2sel); in dwc3_ep0_set_sel_cmpl()
616 dwc->u2pel = le16_to_cpu(timing.u2pel); in dwc3_ep0_set_sel_cmpl()
/linux-4.1.27/drivers/net/can/
Dbfin_can.c88 __BFP(timing); /* offset 0x84 */
176 u16 clk, timing; in bfin_can_set_bittiming() local
179 timing = ((bt->sjw - 1) << 8) | (bt->prop_seg + bt->phase_seg1 - 1) | in bfin_can_set_bittiming()
187 timing |= SAM; in bfin_can_set_bittiming()
190 writew(timing, &reg->timing); in bfin_can_set_bittiming()
192 netdev_info(dev, "setting CLOCK=0x%04x TIMING=0x%04x\n", clk, timing); in bfin_can_set_bittiming()
DKconfig43 bool "CAN bit-timing calculation"
46 If enabled, CAN bit-timing parameters will be calculated for the
51 bit-timing parameters must be specified directly using the Netlink
Dgrcan.c412 u32 timing = 0; in grcan_set_bittiming() local
439 timing |= (bpr << GRCAN_CONF_BPR_BIT) & GRCAN_CONF_BPR; in grcan_set_bittiming()
440 timing |= (rsj << GRCAN_CONF_RSJ_BIT) & GRCAN_CONF_RSJ; in grcan_set_bittiming()
441 timing |= (ps1 << GRCAN_CONF_PS1_BIT) & GRCAN_CONF_PS1; in grcan_set_bittiming()
442 timing |= (ps2 << GRCAN_CONF_PS2_BIT) & GRCAN_CONF_PS2; in grcan_set_bittiming()
443 timing |= (scaler << GRCAN_CONF_SCALER_BIT) & GRCAN_CONF_SCALER; in grcan_set_bittiming()
444 netdev_info(dev, "setting timing=0x%x\n", timing); in grcan_set_bittiming()
445 grcan_write_bits(&regs->conf, timing, GRCAN_CONF_TIMING); in grcan_set_bittiming()
/linux-4.1.27/Documentation/devicetree/bindings/drm/tilcdc/
Dpanel.txt18 Documentation/devicetree/bindings/video/display-timing.txt for display
19 timing binding details.
/linux-4.1.27/sound/core/
DKconfig110 the hrtimer as a precise timing source. The ALSA sequencer code
111 also can use this timing source.
130 the RTC timer as a precise timing source and maps the RTC
132 can use this timing source.
148 precise MIDI timing even when the system timer runs at less
/linux-4.1.27/drivers/video/fbdev/omap2/displays-new/
Dpanel-dpi.c208 struct display_timing timing; in panel_dpi_probe_of() local
227 r = of_get_display_timing(node, "panel-timing", &timing); in panel_dpi_probe_of()
233 videomode_from_timing(&timing, &vm); in panel_dpi_probe_of()
/linux-4.1.27/include/linux/platform_data/
Dmtd-davinci.h87 struct davinci_aemif_timing *timing; member
Dmtd-nand-pxa3xx.h28 struct pxa3xx_nand_timing *timing; /* NAND Flash timing */ member
/linux-4.1.27/arch/arm/mach-davinci/
Daemif.c205 if (pdata->timing) in davinci_aemif_setup()
206 ret = davinci_aemif_setup_timing(pdata->timing, base, pdev->id, in davinci_aemif_setup()
/linux-4.1.27/arch/avr32/mach-at32ap/include/mach/
Dsmc.h108 const struct smc_timing *timing);
/linux-4.1.27/arch/mips/include/asm/mach-rc32434/
Drb.h65 u32 timing; member
/linux-4.1.27/Documentation/devicetree/bindings/net/
Drockchip-dwmac.txt34 - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
35 - rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
Dramcfg.h92 unsigned timing[11]; member
/linux-4.1.27/drivers/net/wireless/iwlwifi/mvm/
Dtdls.c423 cmd.timing.frame_timestamp = cpu_to_le32(timestamp); in iwl_mvm_tdls_config_channel_switch()
424 cmd.timing.switch_time = cpu_to_le32(switch_time); in iwl_mvm_tdls_config_channel_switch()
425 cmd.timing.switch_timeout = cpu_to_le32(switch_timeout); in iwl_mvm_tdls_config_channel_switch()
466 cmd.timing.max_offchan_duration = in iwl_mvm_tdls_config_channel_switch()
/linux-4.1.27/Documentation/fb/
Dmodedb.txt37 Sample usage: 1024x768M@60m - CVT timing with margins
62 timing specifications for computer display products, both those
90 blocks where additional timing information is placed. As of this time, there
104 Note: VESA(TM) has restrictions on what is a standard CVT timing:
/linux-4.1.27/Documentation/devicetree/bindings/powerpc/fsl/
Ddiu.txt16 Data from the detailed timing descriptor will be used to
/linux-4.1.27/Documentation/devicetree/bindings/fb/
Dmxsfb.txt17 - display-timings : Refer to binding doc display-timing.txt for details.
Dsm501fb.txt19 Data from the detailed timing descriptor will be used to
/linux-4.1.27/arch/cris/arch-v32/mach-a3/
DKconfig23 hex "DDR2 SDRAM timing"
26 SDRAM timing parameters.
Ddram_init.S73 ; Set timing
/linux-4.1.27/Documentation/devicetree/bindings/mtd/
Dgpmc-onenand.txt6 All timing relevant properties as well as generic gpmc child properties are
Ddavinci-nand.txt71 the address space. See partition.txt for more detail. The NAND Flash timing
Dgpmc-nor.txt6 All timing relevant properties as well as generic GPMC child properties are
/linux-4.1.27/Documentation/blackfin/
Dbfin-spi-notes.txt11 timing, you can utilize the GPIO controlled SPI Slave Select option instead.
/linux-4.1.27/arch/arm/crypto/
DKconfig89 among the easiest to defend against power and timing attacks.
109 believed to be invulnerable to cache timing attacks.
/linux-4.1.27/Documentation/mips/
DAU1xxx_IDE.README49 timing parameters for PIO mode 0/1/2/3/4
50 timing parameters for MWDMA 0/1/2
/linux-4.1.27/Documentation/devicetree/bindings/usb/
Dnvidia,tegra20-usb-phy.txt36 Required PHY timing params for utmi phy, for all chips:
51 Required PHY timing params for utmi phy, only on Tegra30 and above:
/linux-4.1.27/arch/c6x/kernel/
Dvectors.S12 ; At RESET the processor sets up the DRAM timing parameters and
/linux-4.1.27/Documentation/memory-devices/
Dti-emif.txt28 functions of the driver includes re-configuring AC timing
/linux-4.1.27/Documentation/arm/SA1100/
DADSBitsy40 mode, the timing is off so the image is corrupted. This will be
DGraphicsMaster50 mode, the timing is off so the image is corrupted. This will be
/linux-4.1.27/drivers/mtd/nand/gpmi-nand/
Dgpmi-nand.h150 struct nand_timing timing; member
/linux-4.1.27/arch/powerpc/kvm/
DKconfig114 bool "Detailed timing for hypervisor real-mode code"
131 bool "Detailed exit timing"
DMakefile19 obj-$(CONFIG_KVM_EXIT_TIMING) += timing.o
/linux-4.1.27/Documentation/networking/
Dray_cs.txt68 bc integer 0 = normal mode (802.11 timing)
69 1 = slow down inter frame timing to allow
Dcan.txt49 6.5.2 Setting the CAN bit-timing
998 configure the CAN device, like setting the bit-timing parameters, via
1073 range 0.000..0.999. If the calculation of bit-timing parameters
1075 bit-timing can be defined by setting the "bitrate" argument.
1082 tq. They allow to define the CAN bit-timing in a hardware
1088 Shows the bit-timing constants of the CAN controller, here the
1093 bit-timing calculation algorithms in user-space.
1101 6.5.2 Setting the CAN bit-timing
1103 The CAN bit-timing parameters can always be defined in a hardware
1112 recommended CAN bit-timing parameters will be calculated if the bit-
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/linux-4.1.27/arch/arm/mach-sa1100/
Dsleep.S50 @ Adjust memory timing before lowering CPU clock
/linux-4.1.27/Documentation/timers/
Dhrtimers.txt32 timing inaccuracies. Cascading is a fundamental property of the timer
52 Accurate timing for them is not a core purpose - in fact most of the
88 - simplification of existing, timing related kernel code
/linux-4.1.27/arch/cris/arch-v32/mach-fs/
Ddram_init.S64 ; Set timing parameters (refresh off to avoid Guinness TR 83)
/linux-4.1.27/Documentation/devicetree/bindings/memory-controllers/
Dmvebu-devbus.txt29 using the timing parameters set by the
30 bootloader. It makes all the timing properties
/linux-4.1.27/Documentation/video4linux/cx2341x/
Dfw-decoder-api.txt82 has to be set to the correct value in order to keep the timing correct.
206 Returns timing information from start of playback
/linux-4.1.27/Documentation/devicetree/bindings/spi/
Dspi-davinci.txt43 Below is timing diagram which shows functional meaning of
/linux-4.1.27/arch/cris/arch-v10/lib/
Ddram_init.S83 ; Set timing parameters. Starts master clock
/linux-4.1.27/Documentation/video4linux/
Dcpia2_overview.txt26 how the video from the sensor is processed. Examples are timing registers,
/linux-4.1.27/Documentation/filesystems/
Dgfs2-glocks.txt130 block timing statistics are used to provide default values for
131 the glock timing statistics, so that newly created glocks
220 using the format mean/variance for each of the timing stats.
/linux-4.1.27/drivers/net/wireless/rsi/
Drsi_91x_sdio.c183 host->ios.timing = MMC_TIMING_LEGACY; in rsi_reset_card()
298 host->ios.timing = MMC_TIMING_SD_HS; in rsi_reset_card()
/linux-4.1.27/Documentation/EDID/
DHOWTO.txt33 Makefile. Please note that the EDID data structure expects the timing
/linux-4.1.27/Documentation/devicetree/bindings/gpu/
Dst,stih4xx.txt3 - sti-vtg: video timing generator
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
/linux-4.1.27/arch/arm/mach-s3c24xx/
DKconfig133 Internal node to select io timing code that is common to the s3c2410
140 Internal node to select timing code that is common to the s3c2410
149 Intel node to select io timing code that is common to the s3c2412
/linux-4.1.27/drivers/memory/
DKconfig40 functions of the driver includes re-configuring AC timing
/linux-4.1.27/drivers/net/wireless/iwlegacy/
Dcommon.c3652 memset(&il->timing, 0, sizeof(struct il_rxon_time_cmd)); in il_send_rxon_timing()
3654 il->timing.timestamp = cpu_to_le64(il->timestamp); in il_send_rxon_timing()
3655 il->timing.listen_interval = cpu_to_le16(conf->listen_interval); in il_send_rxon_timing()
3663 il->timing.atim_win = 0; in il_send_rxon_timing()
3669 il->timing.beacon_interval = cpu_to_le16(beacon_int); in il_send_rxon_timing()
3674 il->timing.beacon_init_val = cpu_to_le32(interval_tm - rem); in il_send_rxon_timing()
3676 il->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ? : 1) : 1; in il_send_rxon_timing()
3679 le16_to_cpu(il->timing.beacon_interval), in il_send_rxon_timing()
3680 le32_to_cpu(il->timing.beacon_init_val), in il_send_rxon_timing()
3681 le16_to_cpu(il->timing.atim_win)); in il_send_rxon_timing()
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