| /linux-4.1.27/drivers/gpu/drm/i915/ |
| H A D | i915_gem_tiling.c | 232 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) i915_tiling_ok() argument
237 if (tiling_mode == I915_TILING_NONE) i915_tiling_ok()
241 (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) i915_tiling_ok()
287 i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode) i915_gem_object_fence_ok() argument
291 if (tiling_mode == I915_TILING_NONE) i915_gem_object_fence_ok()
305 size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode); i915_gem_object_fence_ok()
333 args->stride, obj->base.size, args->tiling_mode)) { i915_gem_set_tiling()
344 if (args->tiling_mode == I915_TILING_NONE) { i915_gem_set_tiling()
348 if (args->tiling_mode == I915_TILING_X) i915_gem_set_tiling()
367 args->tiling_mode = I915_TILING_NONE; i915_gem_set_tiling()
373 if (args->tiling_mode != obj->tiling_mode || i915_gem_set_tiling()
388 !i915_gem_object_fence_ok(obj, args->tiling_mode)) i915_gem_set_tiling()
395 if (args->tiling_mode == I915_TILING_NONE) i915_gem_set_tiling()
397 if (obj->tiling_mode == I915_TILING_NONE) i915_gem_set_tiling()
405 obj->tiling_mode = args->tiling_mode; i915_gem_set_tiling()
414 args->tiling_mode = obj->tiling_mode; i915_gem_set_tiling()
451 args->tiling_mode = obj->tiling_mode; i915_gem_get_tiling()
452 switch (obj->tiling_mode) { i915_gem_get_tiling()
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| H A D | intel_sprite.c | 423 if (obj->tiling_mode != I915_TILING_NONE) vlv_update_plane()
438 obj->tiling_mode, vlv_update_plane()
468 if (obj->tiling_mode != I915_TILING_NONE) vlv_update_plane()
556 if (obj->tiling_mode != I915_TILING_NONE) ivb_update_plane()
582 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, ivb_update_plane()
618 else if (obj->tiling_mode != I915_TILING_NONE) ivb_update_plane()
704 if (obj->tiling_mode != I915_TILING_NONE) ilk_update_plane()
726 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, ilk_update_plane()
754 if (obj->tiling_mode != I915_TILING_NONE) ilk_update_plane()
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| H A D | i915_gem.c | 71 if (obj->tiling_mode) i915_gem_object_fence_lost()
1104 if (obj->tiling_mode == I915_TILING_NONE && i915_gem_pwrite_ioctl()
1772 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) i915_gem_get_gtt_size() argument
1777 tiling_mode == I915_TILING_NONE) i915_gem_get_gtt_size()
1801 int tiling_mode, bool fenced) i915_gem_get_gtt_alignment()
1808 tiling_mode == I915_TILING_NONE) i915_gem_get_gtt_alignment()
1815 return i915_gem_get_gtt_size(dev, size, tiling_mode); i915_gem_get_gtt_alignment()
2125 if (obj->tiling_mode != I915_TILING_NONE && i915_gem_object_get_pages_gtt()
2625 reg->obj->tiling_mode); i915_gem_restore_fences()
3090 if (obj->tiling_mode != I915_TILING_NONE) { i965_write_fence_reg()
3092 (obj->tiling_mode == I915_TILING_Y ? 32 : 8); i965_write_fence_reg()
3100 if (obj->tiling_mode == I915_TILING_Y) i965_write_fence_reg()
3132 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) i915_write_fence_reg()
3142 if (obj->tiling_mode == I915_TILING_Y) i915_write_fence_reg()
3179 if (obj->tiling_mode == I915_TILING_Y) i830_write_fence_reg()
3207 WARN(obj && (!obj->stride || !obj->tiling_mode), i915_gem_write_fence()
3209 obj->stride, obj->tiling_mode); i915_gem_write_fence()
3347 bool enable = obj->tiling_mode != I915_TILING_NONE; i915_gem_object_get_fence()
3451 obj->tiling_mode); i915_gem_object_bind_to_vm()
3454 obj->tiling_mode, true); i915_gem_object_bind_to_vm()
3458 obj->tiling_mode, false); i915_gem_object_bind_to_vm()
4181 obj->tiling_mode); i915_gem_object_do_pin()
4184 obj->tiling_mode, i915_gem_object_do_pin()
4348 obj->tiling_mode != I915_TILING_NONE && i915_gem_madvise_ioctl()
4508 obj->tiling_mode != I915_TILING_NONE) i915_gem_free_object()
1800 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, int tiling_mode, bool fenced) i915_gem_get_gtt_alignment() argument
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| H A D | intel_display.c | 2468 unsigned int tiling_mode, intel_gen4_compute_page_offset()
2472 if (tiling_mode != I915_TILING_NONE) { intel_gen4_compute_page_offset()
2563 obj->tiling_mode = plane_config->tiling; intel_alloc_initial_plane_obj()
2564 if (obj->tiling_mode == I915_TILING_X) intel_alloc_initial_plane_obj()
2655 if (obj->tiling_mode != I915_TILING_NONE)
2750 obj->tiling_mode != I915_TILING_NONE) i9xx_update_primary_plane()
2760 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, i9xx_update_primary_plane()
2855 if (obj->tiling_mode != I915_TILING_NONE) ironlake_update_primary_plane()
2863 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, ironlake_update_primary_plane()
9738 obj->tiling_mode); intel_gen4_queue_flip()
9771 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); intel_gen6_queue_flip()
9875 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); intel_gen7_queue_flip()
9923 if (obj->tiling_mode == I915_TILING_X) skl_do_mmio_flip()
9931 if (obj->tiling_mode == I915_TILING_X) skl_do_mmio_flip()
9958 if (obj->tiling_mode != I915_TILING_NONE) ilk_do_mmio_flip()
10200 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) intel_crtc_page_flip()
13272 if (!!(obj->tiling_mode == I915_TILING_X) != intel_framebuffer_init()
13274 DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); intel_framebuffer_init()
13278 if (obj->tiling_mode == I915_TILING_X) intel_framebuffer_init()
13280 else if (obj->tiling_mode == I915_TILING_Y) { intel_framebuffer_init()
2467 intel_gen4_compute_page_offset(int *x, int *y, unsigned int tiling_mode, unsigned int cpp, unsigned int pitch) intel_gen4_compute_page_offset() argument
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| H A D | i915_drv.h | 1950 unsigned int tiling_mode:2; member in struct:drm_i915_gem_object
2781 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2784 int tiling_mode, bool fenced);
2978 obj->tiling_mode != I915_TILING_NONE; i915_gem_object_needs_bit17_swizzle()
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| H A D | intel_fbc.c | 582 if (obj->tiling_mode != I915_TILING_X || intel_fbc_update()
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| H A D | i915_gpu_error.c | 694 err->tiling = obj->tiling_mode; capture_bo()
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| H A D | intel_overlay.c | 1108 if (new_bo->tiling_mode) { intel_overlay_put_image()
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| H A D | i915_gem_execbuffer.c | 711 obj->tiling_mode != I915_TILING_NONE; i915_gem_execbuffer_reserve()
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| H A D | intel_drv.h | 1034 unsigned int tiling_mode,
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| H A D | i915_debugfs.c | 107 switch (obj->tiling_mode) { get_tiling_flag()
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| H A D | intel_pm.c | 1328 if (obj->tiling_mode == I915_TILING_NONE) i9xx_update_wm()
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| /linux-4.1.27/include/uapi/drm/ |
| H A D | i915_drm.h | 871 * Buffer contents become undefined when changing tiling_mode.
873 __u32 tiling_mode; member in struct:drm_i915_gem_set_tiling
896 __u32 tiling_mode; member in struct:drm_i915_gem_get_tiling
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