Searched refs:spu_adv_reg (Results 1 – 4 of 4) sorted by relevance
81 .spu_adv_reg = ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,
47 uint32_t spu_adv_reg; member
63 uint32_t spu_adv_reg; member
388 val |= dcrtc->v[i].spu_adv_reg; in armada_drm_crtc_irq()564 dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN | in armada_drm_crtc_mode_set()565 dcrtc->variant->spu_adv_reg; in armada_drm_crtc_mode_set()573 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN | in armada_drm_crtc_mode_set()574 dcrtc->variant->spu_adv_reg; in armada_drm_crtc_mode_set()590 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg, in armada_drm_crtc_mode_set()