Searched refs:sdiv (Results 1 - 11 of 11) sorted by relevance

/linux-4.1.27/drivers/clk/samsung/
H A Dclk-pll.h47 .sdiv = (_s), \
55 .sdiv = (_s), \
64 .sdiv = (_s), \
73 .sdiv = (_s), \
83 .sdiv = (_s), \
96 unsigned int sdiv; member in struct:samsung_pll_rate_table
H A Dclk-pll.c77 u32 pll_con, mdiv, pdiv, sdiv; samsung_pll2126_recalc_rate() local
83 sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK; samsung_pll2126_recalc_rate()
86 do_div(fvco, (pdiv + 2) << sdiv); samsung_pll2126_recalc_rate()
110 u32 pll_con, mdiv, pdiv, sdiv; samsung_pll3000_recalc_rate() local
116 sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK; samsung_pll3000_recalc_rate()
119 do_div(fvco, pdiv << sdiv); samsung_pll3000_recalc_rate()
147 u32 mdiv, pdiv, sdiv, pll_con; samsung_pll35xx_recalc_rate() local
153 sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK; samsung_pll35xx_recalc_rate()
156 do_div(fvco, (pdiv << sdiv)); samsung_pll35xx_recalc_rate()
192 tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT; samsung_pll35xx_set_rate()
208 (rate->sdiv << PLL35XX_SDIV_SHIFT); samsung_pll35xx_set_rate()
250 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; samsung_pll36xx_recalc_rate() local
258 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK; samsung_pll36xx_recalc_rate()
262 do_div(fvco, (pdiv << sdiv)); samsung_pll36xx_recalc_rate()
301 pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT); samsung_pll36xx_set_rate()
316 (rate->sdiv << PLL36XX_SDIV_SHIFT); samsung_pll36xx_set_rate()
364 u32 mdiv, pdiv, sdiv, pll_con; samsung_pll45xx_recalc_rate() local
370 sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK; samsung_pll45xx_recalc_rate()
373 sdiv = sdiv - 1; samsung_pll45xx_recalc_rate()
376 do_div(fvco, (pdiv << sdiv)); samsung_pll45xx_recalc_rate()
416 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT; samsung_pll45xx_set_rate()
428 (rate->sdiv << PLL45XX_SDIV_SHIFT); samsung_pll45xx_set_rate()
511 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift; samsung_pll46xx_recalc_rate() local
519 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; samsung_pll46xx_recalc_rate()
526 do_div(fvco, (pdiv << sdiv)); samsung_pll46xx_recalc_rate()
567 con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT; samsung_pll46xx_set_rate()
594 (rate->sdiv << PLL46XX_SDIV_SHIFT); samsung_pll46xx_set_rate()
654 u32 mdiv, pdiv, sdiv, pll_con; samsung_pll6552_recalc_rate() local
665 sdiv = (pll_con >> PLL6552_SDIV_SHIFT) & PLL6552_SDIV_MASK; samsung_pll6552_recalc_rate()
668 do_div(fvco, (pdiv << sdiv)); samsung_pll6552_recalc_rate()
694 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1; samsung_pll6553_recalc_rate() local
701 sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK; samsung_pll6553_recalc_rate()
705 do_div(fvco, (pdiv << sdiv)); samsung_pll6553_recalc_rate()
732 u32 pll_con, mdiv, pdiv, sdiv; samsung_s3c2410_pll_recalc_rate() local
738 sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK; samsung_s3c2410_pll_recalc_rate()
741 do_div(fvco, (pdiv + 2) << sdiv); samsung_s3c2410_pll_recalc_rate()
750 u32 pll_con, mdiv, pdiv, sdiv; samsung_s3c2440_mpll_recalc_rate() local
756 sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK; samsung_s3c2440_mpll_recalc_rate()
759 do_div(fvco, (pdiv + 2) << sdiv); samsung_s3c2440_mpll_recalc_rate()
787 (rate->sdiv << PLLS3C2410_SDIV_SHIFT); samsung_s3c2410_pll_set_rate()
981 u32 mdiv, pdiv, sdiv, pll_con; samsung_pll2550xx_recalc_rate() local
987 sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK; samsung_pll2550xx_recalc_rate()
990 do_div(fvco, (pdiv << sdiv)); samsung_pll2550xx_recalc_rate()
1025 tmp |= rate->sdiv << PLL2550XX_S_SHIFT; samsung_pll2550xx_set_rate()
1040 (rate->sdiv << PLL2550XX_S_SHIFT); samsung_pll2550xx_set_rate()
1086 u32 mdiv, pdiv, sdiv, pll_con0, pll_con2; samsung_pll2650xx_recalc_rate() local
1094 sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK; samsung_pll2650xx_recalc_rate()
1098 do_div(fvco, (pdiv << sdiv)); samsung_pll2650xx_recalc_rate()
1127 pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT; samsung_pll2650xx_set_rate()
/linux-4.1.27/drivers/clk/st/
H A Dclkgen-fsyn.c40 unsigned long sdiv; member in struct:stm_fs
45 { .mdiv = 0x1f, .pe = 0x0, .sdiv = 0x7, .nsdiv = 0 }, /* 312.5 Khz */
46 { .mdiv = 0x17, .pe = 0x25ed, .sdiv = 0x1, .nsdiv = 0 }, /* 27 MHz */
47 { .mdiv = 0x1a, .pe = 0x7b36, .sdiv = 0x2, .nsdiv = 1 }, /* 36.87 MHz */
48 { .mdiv = 0x13, .pe = 0x0, .sdiv = 0x2, .nsdiv = 1 }, /* 48 MHz */
49 { .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x1, .nsdiv = 1 }, /* 108 MHz */
53 { .mdiv = 0x1f, .pe = 0x0, .sdiv = 0x7, .nsdiv = 0 }, /* 625 Khz */
54 { .mdiv = 0x13, .pe = 0x777c, .sdiv = 0x4, .nsdiv = 1 }, /* 25.175 MHz */
55 { .mdiv = 0x19, .pe = 0x4d35, .sdiv = 0x2, .nsdiv = 0 }, /* 25.200 MHz */
56 { .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x4, .nsdiv = 1 }, /* 27.000 MHz */
57 { .mdiv = 0x17, .pe = 0x28f5, .sdiv = 0x2, .nsdiv = 0 }, /* 27.027 MHz */
58 { .mdiv = 0x16, .pe = 0x3359, .sdiv = 0x2, .nsdiv = 0 }, /* 28.320 MHz */
59 { .mdiv = 0x1f, .pe = 0x2083, .sdiv = 0x3, .nsdiv = 1 }, /* 30.240 MHz */
60 { .mdiv = 0x1e, .pe = 0x430d, .sdiv = 0x3, .nsdiv = 1 }, /* 31.500 MHz */
61 { .mdiv = 0x17, .pe = 0x0, .sdiv = 0x3, .nsdiv = 1 }, /* 40.000 MHz */
62 { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x1, .nsdiv = 0 }, /* 49.500 MHz */
63 { .mdiv = 0x13, .pe = 0x6667, .sdiv = 0x3, .nsdiv = 1 }, /* 50.000 MHz */
64 { .mdiv = 0x10, .pe = 0x1ee6, .sdiv = 0x3, .nsdiv = 1 }, /* 57.284 MHz */
65 { .mdiv = 0x1d, .pe = 0x3b14, .sdiv = 0x2, .nsdiv = 1 }, /* 65.000 MHz */
66 { .mdiv = 0x12, .pe = 0x7c65, .sdiv = 0x1, .nsdiv = 0 }, /* 71.000 MHz */
67 { .mdiv = 0x19, .pe = 0xecd, .sdiv = 0x2, .nsdiv = 1 }, /* 74.176 MHz */
68 { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x2, .nsdiv = 1 }, /* 74.250 MHz */
69 { .mdiv = 0x19, .pe = 0x3334, .sdiv = 0x2, .nsdiv = 1 }, /* 75.000 MHz */
70 { .mdiv = 0x18, .pe = 0x5138, .sdiv = 0x2, .nsdiv = 1 }, /* 78.800 MHz */
71 { .mdiv = 0x1d, .pe = 0x77d, .sdiv = 0x0, .nsdiv = 0 }, /* 85.500 MHz */
72 { .mdiv = 0x1c, .pe = 0x13d5, .sdiv = 0x0, .nsdiv = 0 }, /* 88.750 MHz */
73 { .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x2, .nsdiv = 1 }, /* 108.000 MHz */
74 { .mdiv = 0x17, .pe = 0x28f5, .sdiv = 0x0, .nsdiv = 0 }, /* 108.108 MHz */
75 { .mdiv = 0x10, .pe = 0x6e26, .sdiv = 0x2, .nsdiv = 1 }, /* 118.963 MHz */
76 { .mdiv = 0x15, .pe = 0x3e63, .sdiv = 0x0, .nsdiv = 0 }, /* 119.000 MHz */
77 { .mdiv = 0x1c, .pe = 0x471d, .sdiv = 0x1, .nsdiv = 1 }, /* 135.000 MHz */
78 { .mdiv = 0x19, .pe = 0xecd, .sdiv = 0x1, .nsdiv = 1 }, /* 148.352 MHz */
79 { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x1, .nsdiv = 1 }, /* 148.500 MHz */
80 { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x0, .nsdiv = 1 }, /* 297 MHz */
84 { .mdiv = 0x14, .pe = 0x376b, .sdiv = 0x4, .nsdiv = 1 }, /* 25.175 MHz */
85 { .mdiv = 0x14, .pe = 0x30c3, .sdiv = 0x4, .nsdiv = 1 }, /* 25.200 MHz */
86 { .mdiv = 0x10, .pe = 0x71c7, .sdiv = 0x4, .nsdiv = 1 }, /* 27.000 MHz */
87 { .mdiv = 0x00, .pe = 0x47af, .sdiv = 0x3, .nsdiv = 0 }, /* 27.027 MHz */
88 { .mdiv = 0x0e, .pe = 0x4e1a, .sdiv = 0x4, .nsdiv = 1 }, /* 28.320 MHz */
89 { .mdiv = 0x0b, .pe = 0x534d, .sdiv = 0x4, .nsdiv = 1 }, /* 30.240 MHz */
90 { .mdiv = 0x17, .pe = 0x6fbf, .sdiv = 0x2, .nsdiv = 0 }, /* 31.500 MHz */
91 { .mdiv = 0x01, .pe = 0x0, .sdiv = 0x4, .nsdiv = 1 }, /* 40.000 MHz */
92 { .mdiv = 0x15, .pe = 0x2aab, .sdiv = 0x3, .nsdiv = 1 }, /* 49.500 MHz */
93 { .mdiv = 0x14, .pe = 0x6666, .sdiv = 0x3, .nsdiv = 1 }, /* 50.000 MHz */
94 { .mdiv = 0x1d, .pe = 0x395f, .sdiv = 0x1, .nsdiv = 0 }, /* 57.284 MHz */
95 { .mdiv = 0x08, .pe = 0x4ec5, .sdiv = 0x3, .nsdiv = 1 }, /* 65.000 MHz */
96 { .mdiv = 0x05, .pe = 0x1770, .sdiv = 0x3, .nsdiv = 1 }, /* 71.000 MHz */
97 { .mdiv = 0x03, .pe = 0x4ba7, .sdiv = 0x3, .nsdiv = 1 }, /* 74.176 MHz */
98 { .mdiv = 0x0f, .pe = 0x3426, .sdiv = 0x1, .nsdiv = 0 }, /* 74.250 MHz */
99 { .mdiv = 0x0e, .pe = 0x7777, .sdiv = 0x1, .nsdiv = 0 }, /* 75.000 MHz */
100 { .mdiv = 0x01, .pe = 0x4053, .sdiv = 0x3, .nsdiv = 1 }, /* 78.800 MHz */
101 { .mdiv = 0x09, .pe = 0x15b5, .sdiv = 0x1, .nsdiv = 0 }, /* 85.500 MHz */
102 { .mdiv = 0x1b, .pe = 0x3f19, .sdiv = 0x2, .nsdiv = 1 }, /* 88.750 MHz */
103 { .mdiv = 0x10, .pe = 0x71c7, .sdiv = 0x2, .nsdiv = 1 }, /* 108.000 MHz */
104 { .mdiv = 0x00, .pe = 0x47af, .sdiv = 0x1, .nsdiv = 0 }, /* 108.108 MHz */
105 { .mdiv = 0x0c, .pe = 0x3118, .sdiv = 0x2, .nsdiv = 1 }, /* 118.963 MHz */
106 { .mdiv = 0x0c, .pe = 0x2f54, .sdiv = 0x2, .nsdiv = 1 }, /* 119.000 MHz */
107 { .mdiv = 0x07, .pe = 0xe39, .sdiv = 0x2, .nsdiv = 1 }, /* 135.000 MHz */
108 { .mdiv = 0x03, .pe = 0x4ba7, .sdiv = 0x2, .nsdiv = 1 }, /* 148.352 MHz */
109 { .mdiv = 0x0f, .pe = 0x3426, .sdiv = 0x0, .nsdiv = 0 }, /* 148.500 MHz */
110 { .mdiv = 0x03, .pe = 0x4ba7, .sdiv = 0x1, .nsdiv = 1 }, /* 296.704 MHz */
111 { .mdiv = 0x03, .pe = 0x471c, .sdiv = 0x1, .nsdiv = 1 }, /* 297.000 MHz */
112 { .mdiv = 0x00, .pe = 0x295f, .sdiv = 0x1, .nsdiv = 1 }, /* 326.700 MHz */
113 { .mdiv = 0x1f, .pe = 0x3633, .sdiv = 0x0, .nsdiv = 1 }, /* 333.000 MHz */
114 { .mdiv = 0x1c, .pe = 0x0, .sdiv = 0x0, .nsdiv = 1 }, /* 352.000 Mhz */
136 struct clkgen_field sdiv[QUADFS_MAX_CHAN]; member in struct:clkgen_quadfs_data
191 .sdiv = { CLKGEN_FIELD(0xC, 0x7, 0),
227 .sdiv = { CLKGEN_FIELD(0xC, 0x7, 0),
261 .sdiv = { CLKGEN_FIELD(0xC, 0xf, 0),
297 .sdiv = { CLKGEN_FIELD(0xC, 0xf, 0),
338 .sdiv = { CLKGEN_FIELD(0x304, 0xf, 20),
363 .sdiv = { CLKGEN_FIELD(0x2b4, 0xf, 20),
559 pr_debug("%s: %s new rate %ld [sdiv=0x%x,md=0x%x,pe=0x%x,nsdiv3=%u]\n", quadfs_pll_fs660c32_round_rate()
561 rate, (unsigned int)params.sdiv, quadfs_pll_fs660c32_round_rate()
700 u32 sdiv; member in struct:st_clk_quadfs_fsynth
730 CLKGEN_WRITE(fs, sdiv[fs->chan], fs->sdiv); quadfs_fsynth_program_rate()
806 s = 1 << (fs->sdiv + 1); clk_fs216c65_get_rate()
826 sd = 1 << (fs->sdiv + 1); clk_fs432c65_get_rate()
841 unsigned long s = (1 << fs->sdiv); clk_fs660c32_dig_get_rate()
869 params->sdiv = CLKGEN_READ(fs, sdiv[fs->chan]); quadfs_fsynt_get_hw_value_for_recalc()
879 if (!params->mdiv && !params->pe && !params->sdiv) quadfs_fsynt_get_hw_value_for_recalc()
884 fs->sdiv = params->sdiv; quadfs_fsynt_get_hw_value_for_recalc()
963 pr_debug("%s: %s new rate %ld [sdiv=0x%x,md=0x%x,pe=0x%x,nsdiv3=%u]\n", quadfs_round_rate()
965 rate, (unsigned int)params.sdiv, (unsigned int)params.mdiv, quadfs_round_rate()
977 fs->sdiv = params->sdiv; quadfs_program_and_enable()
/linux-4.1.27/arch/arm/mach-s3c24xx/include/mach/
H A Dregs-s3c2443-clock.h154 unsigned int mdiv, pdiv, sdiv; s3c2443_get_mpll() local
159 sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT; s3c2443_get_mpll()
163 sdiv &= S3C2443_PLLCON_SDIVMASK; s3c2443_get_mpll()
166 do_div(fvco, pdiv << sdiv); s3c2443_get_mpll()
174 unsigned int mdiv, pdiv, sdiv; s3c2443_get_epll() local
179 sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT; s3c2443_get_epll()
183 sdiv &= S3C2443_PLLCON_SDIVMASK; s3c2443_get_epll()
186 do_div(fvco, (pdiv + 2) << sdiv); s3c2443_get_epll()
/linux-4.1.27/arch/mips/cavium-octeon/
H A Dcsrc-octeon.c25 static u64 sdiv; variable
45 sdiv = rst_boot.s.pnr_mul; /* I/O clock */ octeon_setup_delays()
46 f = (0x8000000000000000ull / sdiv) * 2; octeon_setup_delays()
52 sdiv = rst_boot.s.pnr_mul; /* I/O clock */ octeon_setup_delays()
53 f = (0x8000000000000000ull / sdiv) * 2; octeon_setup_delays()
64 * On CPU_CAVIUM_OCTEON2 the IPD_CLK_COUNT is scaled by rdiv/sdiv.
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk104.c119 u32 sdiv = (sctl & 0x0000003f) + 2; read_div() local
120 return (sclk * 2) / sdiv; read_div()
144 u32 sclk, sdiv; read_clk() local
150 sdiv = 1; read_clk()
153 sdiv = 0; read_clk()
162 sdiv = 1; read_clk()
164 sdiv = 0; read_clk()
168 sdiv = 0; read_clk()
173 if (sdiv) read_clk()
174 sdiv = ((sctl & 0x00003f00) >> 8) + 2; read_clk()
176 sdiv = ((sctl & 0x0000003f) >> 0) + 2; read_clk()
177 return (sclk * 2) / sdiv; read_clk()
H A Dgt215.c62 u32 sctl, sdiv, sclk; read_clk() local
98 sdiv = ((sctl & 0x003f0000) >> 16) + 2; read_clk()
99 return (sclk * 2) / sdiv; read_clk()
183 u32 oclk, sclk, sdiv, diff; gt215_clk_info() local
199 sdiv = min((sclk * 2) / khz, (u32)65); gt215_clk_info()
200 oclk = (sclk * 2) / sdiv; gt215_clk_info()
206 sdiv++; gt215_clk_info()
207 oclk = (sclk * 2) / sdiv; gt215_clk_info()
214 if (sdiv > 4) { gt215_clk_info()
215 info->clk = (((sdiv - 2) << 16) | 0x00003100); gt215_clk_info()
H A Dgf100.c113 u32 sdiv = (sctl & 0x0000003f) + 2; read_div() local
114 return (sclk * 2) / sdiv; read_div()
128 u32 sclk, sdiv; read_clk() local
135 sdiv = ((sctl & 0x00003f00) >> 8) + 2; read_clk()
138 sdiv = ((sctl & 0x0000003f) >> 0) + 2; read_clk()
142 return (sclk * 2) / sdiv; read_clk()
/linux-4.1.27/arch/sh/lib/
H A Dudivsi3_i4i-Os.S35 sdiv small divisor, positive result: 59 cycles
36 sdiv large divisor, positive result: 56 cycles
37 sdiv small divisor, negative result: 65 cycles (*)
38 sdiv large divisor, negative result: 62 cycles (*)
/linux-4.1.27/sound/soc/cirrus/
H A Dep93xx-i2s.c250 unsigned word_len, div, sdiv, lrdiv; ep93xx_i2s_hw_params() local
284 sdiv = 4; ep93xx_i2s_hw_params()
290 sdiv = 2; ep93xx_i2s_hw_params()
293 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv); ep93xx_i2s_hw_params()
/linux-4.1.27/arch/arm64/include/asm/
H A Dinsn.h249 __AARCH64_INSN_FUNCS(sdiv, 0x7FE0FC00, 0x1AC00C00)

Completed in 499 milliseconds