Searched refs:rw (Results 1 - 200 of 494) sorted by relevance

123

/linux-4.1.27/drivers/net/wireless/zd1211rw/
H A Dzd_rf_rf2959.c44 static int bits(u32 rw, int from, int to)
46 rw &= ~(0xffffffffU << (to+1));
47 rw >>= from;
48 return rw;
51 static int bit(u32 rw, int bit)
53 return bits(rw, bit, bit);
56 static void dump_regwrite(u32 rw)
58 int reg = bits(rw, 18, 22);
59 int rw_flag = bits(rw, 23, 23);
60 PDEBUG("rf2959 %#010x reg %d rw %d", rw, reg, rw_flag);
66 bits(rw, 14, 15), bit(rw, 3), bit(rw, 2), bit(rw, 1),
67 bit(rw, 0));
73 bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
74 bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
75 bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0, 3));
79 bits(rw, 6, 17), bits(rw, 0, 5));
82 PDEBUG("reg3 IFPLL3 num %d", bits(rw, 0, 17));
86 bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
92 bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
93 bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
94 bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0,3));
98 bits(rw, 6, 17), bits(rw, 0, 5));
101 PDEBUG("reg7 RFPLL3 num2 %d", bits(rw, 0, 17));
105 bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
109 bits(rw, 13, 17), bits(rw, 8, 12), bits(rw, 3, 7),
110 bits(rw, 0, 2));
116 bit(rw, 17), bits(rw, 15, 16), bits(rw, 10, 14),
117 bits(rw, 7, 9), bits(rw, 4, 6), bit(rw, 3), bit(rw, 2),
118 bit(rw, 1), bit(rw, 0));
123 bits(rw, 15, 17), bits(rw, 9, 14), bits(rw, 3, 8),
124 bits(rw, 0, 2));
128 bits(rw, 12, 17), bits(rw, 6, 11), bits(rw, 0, 5));
134 bit(rw, 17), bit(rw, 16), bit(rw, 15),
135 bits(rw, 8, 9), bits(rw, 5, 7), bits(rw, 3, 4),
136 bits(rw, 0, 2));
141 bits(rw, 13, 17), bits(rw, 9, 12), bits(rw, 4, 8),
142 bits(rw, 0, 3));
/linux-4.1.27/arch/s390/include/asm/
H A Dspinlock.h132 static inline int arch_read_trylock_once(arch_rwlock_t *rw) arch_read_trylock_once() argument
134 unsigned int old = ACCESS_ONCE(rw->lock); arch_read_trylock_once()
136 _raw_compare_and_swap(&rw->lock, old, old + 1)); arch_read_trylock_once()
139 static inline int arch_write_trylock_once(arch_rwlock_t *rw) arch_write_trylock_once() argument
141 unsigned int old = ACCESS_ONCE(rw->lock); arch_write_trylock_once()
143 _raw_compare_and_swap(&rw->lock, 0, 0x80000000)); arch_write_trylock_once()
183 static inline void arch_read_lock(arch_rwlock_t *rw) arch_read_lock() argument
187 old = __RAW_LOCK(&rw->lock, 1, __RAW_OP_ADD); arch_read_lock()
189 _raw_read_lock_wait(rw); arch_read_lock()
192 static inline void arch_read_unlock(arch_rwlock_t *rw) arch_read_unlock() argument
194 __RAW_UNLOCK(&rw->lock, -1, __RAW_OP_ADD); arch_read_unlock()
197 static inline void arch_write_lock(arch_rwlock_t *rw) arch_write_lock() argument
201 old = __RAW_LOCK(&rw->lock, 0x80000000, __RAW_OP_OR); arch_write_lock()
203 _raw_write_lock_wait(rw, old); arch_write_lock()
204 rw->owner = SPINLOCK_LOCKVAL; arch_write_lock()
207 static inline void arch_write_unlock(arch_rwlock_t *rw) arch_write_unlock() argument
209 rw->owner = 0; arch_write_unlock()
210 __RAW_UNLOCK(&rw->lock, 0x7fffffff, __RAW_OP_AND); arch_write_unlock()
218 static inline void arch_read_lock(arch_rwlock_t *rw) arch_read_lock() argument
220 if (!arch_read_trylock_once(rw)) arch_read_lock()
221 _raw_read_lock_wait(rw); arch_read_lock()
224 static inline void arch_read_unlock(arch_rwlock_t *rw) arch_read_unlock() argument
229 old = ACCESS_ONCE(rw->lock); arch_read_unlock()
230 } while (!_raw_compare_and_swap(&rw->lock, old, old - 1)); arch_read_unlock()
233 static inline void arch_write_lock(arch_rwlock_t *rw) arch_write_lock() argument
235 if (!arch_write_trylock_once(rw)) arch_write_lock()
236 _raw_write_lock_wait(rw); arch_write_lock()
237 rw->owner = SPINLOCK_LOCKVAL; arch_write_lock()
240 static inline void arch_write_unlock(arch_rwlock_t *rw) arch_write_unlock() argument
242 typecheck(unsigned int, rw->lock); arch_write_unlock()
244 rw->owner = 0; arch_write_unlock()
248 : "+Q" (rw->lock) arch_write_unlock()
255 static inline int arch_read_trylock(arch_rwlock_t *rw) arch_read_trylock() argument
257 if (!arch_read_trylock_once(rw)) arch_read_trylock()
258 return _raw_read_trylock_retry(rw); arch_read_trylock()
262 static inline int arch_write_trylock(arch_rwlock_t *rw) arch_write_trylock() argument
264 if (!arch_write_trylock_once(rw) && !_raw_write_trylock_retry(rw)) arch_write_trylock()
266 rw->owner = SPINLOCK_LOCKVAL; arch_write_trylock()
270 static inline void arch_read_relax(arch_rwlock_t *rw) arch_read_relax() argument
272 arch_lock_relax(rw->owner); arch_read_relax()
275 static inline void arch_write_relax(arch_rwlock_t *rw) arch_write_relax() argument
277 arch_lock_relax(rw->owner); arch_write_relax()
/linux-4.1.27/arch/blackfin/include/asm/
H A Dspinlock.h55 static inline int arch_read_can_lock(arch_rwlock_t *rw) arch_read_can_lock() argument
57 return __raw_uncached_fetch_asm(&rw->lock) > 0; arch_read_can_lock()
60 static inline int arch_write_can_lock(arch_rwlock_t *rw) arch_write_can_lock() argument
62 return __raw_uncached_fetch_asm(&rw->lock) == RW_LOCK_BIAS; arch_write_can_lock()
65 static inline void arch_read_lock(arch_rwlock_t *rw) arch_read_lock() argument
67 __raw_read_lock_asm(&rw->lock); arch_read_lock()
72 static inline int arch_read_trylock(arch_rwlock_t *rw) arch_read_trylock() argument
74 return __raw_read_trylock_asm(&rw->lock); arch_read_trylock()
77 static inline void arch_read_unlock(arch_rwlock_t *rw) arch_read_unlock() argument
79 __raw_read_unlock_asm(&rw->lock); arch_read_unlock()
82 static inline void arch_write_lock(arch_rwlock_t *rw) arch_write_lock() argument
84 __raw_write_lock_asm(&rw->lock); arch_write_lock()
89 static inline int arch_write_trylock(arch_rwlock_t *rw) arch_write_trylock() argument
91 return __raw_write_trylock_asm(&rw->lock); arch_write_trylock()
94 static inline void arch_write_unlock(arch_rwlock_t *rw) arch_write_unlock() argument
96 __raw_write_unlock_asm(&rw->lock); arch_write_unlock()
/linux-4.1.27/arch/mn10300/include/asm/
H A Drwlock.h2 * Helpers used by both rw spinlocks and rw semaphores.
32 #define __build_read_lock_ptr(rw, helper) \
47 : "d" (rw) \
51 #define __build_read_lock_const(rw, helper) \
66 : "d" (rw) \
70 #define __build_read_lock(rw, helper) \
72 if (__builtin_constant_p(rw)) \
73 __build_read_lock_const(rw, helper); \
75 __build_read_lock_ptr(rw, helper); \
78 #define __build_write_lock_ptr(rw, helper) \
93 : "d" (rw) \
97 #define __build_write_lock_const(rw, helper) \
112 : "d" (rw) \
116 #define __build_write_lock(rw, helper) \
118 if (__builtin_constant_p(rw)) \
119 __build_write_lock_const(rw, helper); \
121 __build_write_lock_ptr(rw, helper); \
H A Dspinlock.h116 static inline void arch_read_lock(arch_rwlock_t *rw) arch_read_lock() argument
119 __build_read_lock(rw, "__read_lock_failed"); arch_read_lock()
122 atomic_t *count = (atomic_t *)rw; arch_read_lock()
129 static inline void arch_write_lock(arch_rwlock_t *rw) arch_write_lock() argument
132 __build_write_lock(rw, "__write_lock_failed"); arch_write_lock()
135 atomic_t *count = (atomic_t *)rw; arch_write_lock()
142 static inline void arch_read_unlock(arch_rwlock_t *rw) arch_read_unlock() argument
145 __build_read_unlock(rw); arch_read_unlock()
148 atomic_t *count = (atomic_t *)rw; arch_read_unlock()
154 static inline void arch_write_unlock(arch_rwlock_t *rw) arch_write_unlock() argument
157 __build_write_unlock(rw); arch_write_unlock()
160 atomic_t *count = (atomic_t *)rw; arch_write_unlock()
/linux-4.1.27/arch/parisc/include/asm/
H A Dspinlock.h73 static __inline__ void arch_read_lock(arch_rwlock_t *rw) arch_read_lock() argument
77 arch_spin_lock_flags(&rw->lock, flags); arch_read_lock()
78 rw->counter++; arch_read_lock()
79 arch_spin_unlock(&rw->lock); arch_read_lock()
85 static __inline__ void arch_read_unlock(arch_rwlock_t *rw) arch_read_unlock() argument
89 arch_spin_lock_flags(&rw->lock, flags); arch_read_unlock()
90 rw->counter--; arch_read_unlock()
91 arch_spin_unlock(&rw->lock); arch_read_unlock()
97 static __inline__ int arch_read_trylock(arch_rwlock_t *rw) arch_read_trylock() argument
102 if (arch_spin_trylock(&rw->lock)) { arch_read_trylock()
103 rw->counter++; arch_read_trylock()
104 arch_spin_unlock(&rw->lock); arch_read_trylock()
111 if (rw->counter < 0) arch_read_trylock()
115 while (arch_spin_is_locked(&rw->lock) && rw->counter >= 0) arch_read_trylock()
123 static __inline__ void arch_write_lock(arch_rwlock_t *rw) arch_write_lock() argument
128 arch_spin_lock_flags(&rw->lock, flags); arch_write_lock()
130 if (rw->counter != 0) { arch_write_lock()
131 arch_spin_unlock(&rw->lock); arch_write_lock()
134 while (rw->counter != 0) arch_write_lock()
140 rw->counter = -1; /* mark as write-locked */ arch_write_lock()
145 static __inline__ void arch_write_unlock(arch_rwlock_t *rw) arch_write_unlock() argument
147 rw->counter = 0; arch_write_unlock()
148 arch_spin_unlock(&rw->lock); arch_write_unlock()
153 static __inline__ int arch_write_trylock(arch_rwlock_t *rw) arch_write_trylock() argument
159 if (arch_spin_trylock(&rw->lock)) { arch_write_trylock()
160 if (rw->counter == 0) { arch_write_trylock()
161 rw->counter = -1; arch_write_trylock()
165 arch_spin_unlock(&rw->lock); arch_write_trylock()
177 static __inline__ int arch_read_can_lock(arch_rwlock_t *rw) arch_read_can_lock() argument
179 return rw->counter >= 0; arch_read_can_lock()
186 static __inline__ int arch_write_can_lock(arch_rwlock_t *rw) arch_write_can_lock() argument
188 return !rw->counter; arch_write_can_lock()
/linux-4.1.27/arch/metag/include/asm/
H A Dspinlock_lock1.h66 static inline void arch_write_lock(arch_rwlock_t *rw) arch_write_lock() argument
73 if (rw->lock == 0) { arch_write_lock()
75 rw->lock = 0x80000000; arch_write_lock()
81 WARN_ON(rw->lock != 0x80000000); arch_write_lock()
84 static inline int arch_write_trylock(arch_rwlock_t *rw) arch_write_trylock() argument
90 ret = rw->lock; arch_write_trylock()
93 rw->lock = 0x80000000; arch_write_trylock()
100 static inline void arch_write_unlock(arch_rwlock_t *rw) arch_write_unlock() argument
103 WARN_ON(rw->lock != 0x80000000); arch_write_unlock()
104 rw->lock = 0; arch_write_unlock()
108 static inline int arch_write_can_lock(arch_rwlock_t *rw) arch_write_can_lock() argument
113 ret = rw->lock; arch_write_can_lock()
129 static inline void arch_read_lock(arch_rwlock_t *rw) arch_read_lock() argument
136 ret = rw->lock; arch_read_lock()
139 rw->lock = ret + 1; arch_read_lock()
147 static inline void arch_read_unlock(arch_rwlock_t *rw) arch_read_unlock() argument
154 ret = rw->lock--; arch_read_unlock()
159 static inline int arch_read_trylock(arch_rwlock_t *rw) arch_read_trylock() argument
165 ret = rw->lock; arch_read_trylock()
168 rw->lock = ret + 1; arch_read_trylock()
175 static inline int arch_read_can_lock(arch_rwlock_t *rw) arch_read_can_lock() argument
180 ret = rw->lock; arch_read_can_lock()
H A Dspinlock_lnkget.h86 static inline void arch_write_lock(arch_rwlock_t *rw) arch_write_lock() argument
100 : "da" (&rw->lock), "bd" (0x80000000) arch_write_lock()
106 static inline int arch_write_trylock(arch_rwlock_t *rw) arch_write_trylock() argument
121 : "da" (&rw->lock), "bd" (0x80000000) arch_write_trylock()
129 static inline void arch_write_unlock(arch_rwlock_t *rw) arch_write_unlock() argument
135 : "da" (&rw->lock), "da" (0) arch_write_unlock()
140 static inline int arch_write_can_lock(arch_rwlock_t *rw) arch_write_can_lock() argument
149 : "da" (&rw->lock) arch_write_can_lock()
166 static inline void arch_read_lock(arch_rwlock_t *rw) arch_read_lock() argument
179 : "da" (&rw->lock) arch_read_lock()
185 static inline void arch_read_unlock(arch_rwlock_t *rw) arch_read_unlock() argument
199 : "da" (&rw->lock) arch_read_unlock()
203 static inline int arch_read_trylock(arch_rwlock_t *rw) arch_read_trylock() argument
219 : "da" (&rw->lock) arch_read_trylock()
228 static inline int arch_read_can_lock(arch_rwlock_t *rw) arch_read_can_lock() argument
237 : "da" (&rw->lock), "bd" (0x80000000) arch_read_can_lock()
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/asm/
H A Ddma_defs_asm.h56 /* Register rw_data, scope dma, type rw */
59 /* Register rw_data_next, scope dma, type rw */
62 /* Register rw_data_buf, scope dma, type rw */
65 /* Register rw_data_ctrl, scope dma, type rw */
80 /* Register rw_data_stat, scope dma, type rw */
86 /* Register rw_data_md, scope dma, type rw */
91 /* Register rw_data_md_s, scope dma, type rw */
96 /* Register rw_data_after, scope dma, type rw */
99 /* Register rw_ctxt, scope dma, type rw */
102 /* Register rw_ctxt_next, scope dma, type rw */
105 /* Register rw_ctxt_ctrl, scope dma, type rw */
120 /* Register rw_ctxt_stat, scope dma, type rw */
126 /* Register rw_ctxt_md0, scope dma, type rw */
131 /* Register rw_ctxt_md0_s, scope dma, type rw */
136 /* Register rw_ctxt_md1, scope dma, type rw */
139 /* Register rw_ctxt_md1_s, scope dma, type rw */
142 /* Register rw_ctxt_md2, scope dma, type rw */
145 /* Register rw_ctxt_md2_s, scope dma, type rw */
148 /* Register rw_ctxt_md3, scope dma, type rw */
151 /* Register rw_ctxt_md3_s, scope dma, type rw */
154 /* Register rw_ctxt_md4, scope dma, type rw */
157 /* Register rw_ctxt_md4_s, scope dma, type rw */
160 /* Register rw_saved_data, scope dma, type rw */
163 /* Register rw_saved_data_buf, scope dma, type rw */
166 /* Register rw_group, scope dma, type rw */
169 /* Register rw_group_next, scope dma, type rw */
172 /* Register rw_group_ctrl, scope dma, type rw */
190 /* Register rw_group_stat, scope dma, type rw */
196 /* Register rw_group_md, scope dma, type rw */
201 /* Register rw_group_md_s, scope dma, type rw */
206 /* Register rw_group_up, scope dma, type rw */
209 /* Register rw_group_down, scope dma, type rw */
212 /* Register rw_cmd, scope dma, type rw */
218 /* Register rw_cfg, scope dma, type rw */
227 /* Register rw_stat, scope dma, type rw */
238 /* Register rw_intr_mask, scope dma, type rw */
256 /* Register rw_ack_intr, scope dma, type rw */
310 /* Register rw_stream_cmd, scope dma, type rw */
H A Dcris_defs_asm.h56 /* Register rw_gc_cfg, scope cris, type rw */
80 /* Register rw_gc_ccs, scope cris, type rw */
83 /* Register rw_gc_srs, scope cris, type rw */
88 /* Register rw_gc_nrp, scope cris, type rw */
91 /* Register rw_gc_exs, scope cris, type rw */
94 /* Register rw_gc_eda, scope cris, type rw */
97 /* Register rw_gc_r0, scope cris, type rw */
100 /* Register rw_gc_r1, scope cris, type rw */
103 /* Register rw_gc_r2, scope cris, type rw */
106 /* Register rw_gc_r3, scope cris, type rw */
H A Dbif_dma_defs_asm.h56 /* Register rw_ch0_ctrl, scope bif_dma, type rw */
89 /* Register rw_ch0_addr, scope bif_dma, type rw */
94 /* Register rw_ch0_start, scope bif_dma, type rw */
100 /* Register rw_ch0_cnt, scope bif_dma, type rw */
113 /* Register rw_ch1_ctrl, scope bif_dma, type rw */
143 /* Register rw_ch1_addr, scope bif_dma, type rw */
148 /* Register rw_ch1_start, scope bif_dma, type rw */
154 /* Register rw_ch1_cnt, scope bif_dma, type rw */
167 /* Register rw_ch2_ctrl, scope bif_dma, type rw */
200 /* Register rw_ch2_addr, scope bif_dma, type rw */
205 /* Register rw_ch2_start, scope bif_dma, type rw */
211 /* Register rw_ch2_cnt, scope bif_dma, type rw */
224 /* Register rw_ch3_ctrl, scope bif_dma, type rw */
254 /* Register rw_ch3_addr, scope bif_dma, type rw */
259 /* Register rw_ch3_start, scope bif_dma, type rw */
265 /* Register rw_ch3_cnt, scope bif_dma, type rw */
278 /* Register rw_intr_mask, scope bif_dma, type rw */
293 /* Register rw_ack_intr, scope bif_dma, type rw */
338 /* Register rw_pin0_cfg, scope bif_dma, type rw */
349 /* Register rw_pin1_cfg, scope bif_dma, type rw */
360 /* Register rw_pin2_cfg, scope bif_dma, type rw */
371 /* Register rw_pin3_cfg, scope bif_dma, type rw */
382 /* Register rw_pin4_cfg, scope bif_dma, type rw */
393 /* Register rw_pin5_cfg, scope bif_dma, type rw */
404 /* Register rw_pin6_cfg, scope bif_dma, type rw */
415 /* Register rw_pin7_cfg, scope bif_dma, type rw */
H A Dtimer_defs_asm.h56 /* Register rw_tmr0_div, scope timer, type rw */
62 /* Register rw_tmr0_ctrl, scope timer, type rw */
69 /* Register rw_tmr1_div, scope timer, type rw */
75 /* Register rw_tmr1_ctrl, scope timer, type rw */
96 /* Register rw_cnt_cfg, scope timer, type rw */
101 /* Register rw_trig, scope timer, type rw */
104 /* Register rw_trig_cfg, scope timer, type rw */
112 /* Register rw_out, scope timer, type rw */
117 /* Register rw_wd_ctrl, scope timer, type rw */
135 /* Register rw_intr_mask, scope timer, type rw */
150 /* Register rw_ack_intr, scope timer, type rw */
195 /* Register rw_test, scope timer, type rw */
H A Dgio_defs_asm.h56 /* Register rw_pa_dout, scope gio, type rw */
66 /* Register rw_pa_oe, scope gio, type rw */
71 /* Register rw_intr_cfg, scope gio, type rw */
90 /* Register rw_intr_mask, scope gio, type rw */
117 /* Register rw_ack_intr, scope gio, type rw */
198 /* Register rw_pb_dout, scope gio, type rw */
208 /* Register rw_pb_oe, scope gio, type rw */
213 /* Register rw_pc_dout, scope gio, type rw */
223 /* Register rw_pc_oe, scope gio, type rw */
228 /* Register rw_pd_dout, scope gio, type rw */
238 /* Register rw_pd_oe, scope gio, type rw */
243 /* Register rw_pe_dout, scope gio, type rw */
253 /* Register rw_pe_oe, scope gio, type rw */
H A Dbif_slave_defs_asm.h56 /* Register rw_slave_cfg, scope bif_slave, type rw */
88 /* Register rw_ch0_cfg, scope bif_slave, type rw */
101 /* Register rw_ch1_cfg, scope bif_slave, type rw */
114 /* Register rw_ch2_cfg, scope bif_slave, type rw */
127 /* Register rw_ch3_cfg, scope bif_slave, type rw */
140 /* Register rw_arb_cfg, scope bif_slave, type rw */
178 /* Register rw_intr_mask, scope bif_slave, type rw */
187 /* Register rw_ack_intr, scope bif_slave, type rw */
H A Dser_defs_asm.h56 /* Register rw_tr_ctrl, scope ser, type rw */
92 /* Register rw_tr_dma_en, scope ser, type rw */
98 /* Register rw_rec_ctrl, scope ser, type rw */
137 /* Register rw_tr_baud_div, scope ser, type rw */
142 /* Register rw_rec_baud_div, scope ser, type rw */
147 /* Register rw_xoff, scope ser, type rw */
155 /* Register rw_xoff_clr, scope ser, type rw */
161 /* Register rw_dout, scope ser, type rw */
254 /* Register rw_rec_eop, scope ser, type rw */
260 /* Register rw_intr_mask, scope ser, type rw */
275 /* Register rw_ack_intr, scope ser, type rw */
H A Deth_defs_asm.h56 /* Register rw_ma0_lo, scope eth, type rw */
61 /* Register rw_ma0_hi, scope eth, type rw */
66 /* Register rw_ma1_lo, scope eth, type rw */
71 /* Register rw_ma1_hi, scope eth, type rw */
76 /* Register rw_ga_lo, scope eth, type rw */
81 /* Register rw_ga_hi, scope eth, type rw */
86 /* Register rw_gen_ctrl, scope eth, type rw */
103 /* Register rw_rec_ctrl, scope eth, type rw */
133 /* Register rw_tr_ctrl, scope eth, type rw */
157 /* Register rw_clr_err, scope eth, type rw */
163 /* Register rw_mgm_ctrl, scope eth, type rw */
281 /* Register rw_test_ctrl, scope eth, type rw */
293 /* Register rw_intr_mask, scope eth, type rw */
338 /* Register rw_ack_intr, scope eth, type rw */
H A Data_defs_asm.h56 /* Register rw_ctrl0, scope ata, type rw */
75 /* Register rw_ctrl1, scope ata, type rw */
82 /* Register rw_ctrl2, scope ata, type rw */
133 /* Register rw_trf_cnt, scope ata, type rw */
143 /* Register rw_intr_mask, scope ata, type rw */
158 /* Register rw_ack_intr, scope ata, type rw */
H A Dmmu_defs_asm.h56 /* Register rw_mm_cfg, scope mmu, type rw */
119 /* Register rw_mm_kbase_lo, scope mmu, type rw */
138 /* Register rw_mm_kbase_hi, scope mmu, type rw */
166 /* Register rw_mm_tlb_sel, scope mmu, type rw */
173 /* Register rw_mm_tlb_lo, scope mmu, type rw */
193 /* Register rw_mm_tlb_hi, scope mmu, type rw */
H A Drt_trace_defs_asm.h56 /* Register rw_cfg, scope rt_trace, type rw */
78 /* Register rw_tap_ctrl, scope rt_trace, type rw */
96 /* Register rw_tap_data, scope rt_trace, type rw */
99 /* Register rw_tap_hdata, scope rt_trace, type rw */
H A Dbif_core_defs_asm.h56 /* Register rw_grp1_cfg, scope bif_core, type rw */
83 /* Register rw_grp2_cfg, scope bif_core, type rw */
110 /* Register rw_grp3_cfg, scope bif_core, type rw */
145 /* Register rw_grp4_cfg, scope bif_core, type rw */
178 /* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
201 /* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
222 /* Register rw_sdram_timing, scope bif_core, type rw */
249 /* Register rw_sdram_cmd, scope bif_core, type rw */
H A Dmarb_defs_asm.h57 /* Register rw_int_slots, scope marb, type rw */
63 /* Register rw_ext_slots, scope marb, type rw */
69 /* Register rw_regs_slots, scope marb, type rw */
74 /* Register rw_intr_mask, scope marb, type rw */
89 /* Register rw_ack_intr, scope marb, type rw */
134 /* Register rw_stop_mask, scope marb, type rw */
224 /* Register rw_no_snoop, scope marb, type rw */
269 /* Register rw_no_snoop_rq, scope marb, type rw */
363 /* Register rw_first_addr, scope marb_bp, type rw */
366 /* Register rw_last_addr, scope marb_bp, type rw */
369 /* Register rw_op, scope marb_bp, type rw */
396 /* Register rw_clients, scope marb_bp, type rw */
441 /* Register rw_options, scope marb_bp, type rw */
570 /* Register rw_ack, scope marb_bp, type rw */
H A Dsser_defs_asm.h56 /* Register rw_cfg, scope sser, type rw */
95 /* Register rw_frm_cfg, scope sser, type rw */
137 /* Register rw_tr_cfg, scope sser, type rw */
192 /* Register rw_rec_cfg, scope sser, type rw */
241 /* Register rw_tr_data, scope sser, type rw */
275 /* Register rw_extra, scope sser, type rw */
288 /* Register rw_intr_mask, scope sser, type rw */
318 /* Register rw_ack_intr, scope sser, type rw */
H A Dconfig_defs_asm.h73 /* Register rw_clk_ctrl, scope config, type rw */
106 /* Register rw_pad_ctrl, scope config, type rw */
H A Dirq_nmi_defs_asm.h56 /* Register rw_cmd, scope irq_nmi, type rw */
/linux-4.1.27/arch/s390/lib/
H A Dspinlock.c137 void _raw_read_lock_wait(arch_rwlock_t *rw) _raw_read_lock_wait() argument
143 __RAW_LOCK(&rw->lock, -1, __RAW_OP_ADD); _raw_read_lock_wait()
152 old = ACCESS_ONCE(rw->lock); _raw_read_lock_wait()
153 owner = ACCESS_ONCE(rw->owner); _raw_read_lock_wait()
156 _raw_compare_and_delay(&rw->lock, old); _raw_read_lock_wait()
159 if (_raw_compare_and_swap(&rw->lock, old, old + 1)) _raw_read_lock_wait()
165 int _raw_read_trylock_retry(arch_rwlock_t *rw) _raw_read_trylock_retry() argument
171 old = ACCESS_ONCE(rw->lock); _raw_read_trylock_retry()
174 _raw_compare_and_delay(&rw->lock, old); _raw_read_trylock_retry()
177 if (_raw_compare_and_swap(&rw->lock, old, old + 1)) _raw_read_trylock_retry()
186 void _raw_write_lock_wait(arch_rwlock_t *rw, unsigned int prev) _raw_write_lock_wait() argument
198 old = ACCESS_ONCE(rw->lock); _raw_write_lock_wait()
199 owner = ACCESS_ONCE(rw->owner); _raw_write_lock_wait()
202 prev = __RAW_LOCK(&rw->lock, 0x80000000, __RAW_OP_OR); _raw_write_lock_wait()
208 _raw_compare_and_delay(&rw->lock, old); _raw_write_lock_wait()
215 void _raw_write_lock_wait(arch_rwlock_t *rw) _raw_write_lock_wait() argument
228 old = ACCESS_ONCE(rw->lock); _raw_write_lock_wait()
229 owner = ACCESS_ONCE(rw->owner); _raw_write_lock_wait()
231 _raw_compare_and_swap(&rw->lock, old, old | 0x80000000)) _raw_write_lock_wait()
238 _raw_compare_and_delay(&rw->lock, old); _raw_write_lock_wait()
245 int _raw_write_trylock_retry(arch_rwlock_t *rw) _raw_write_trylock_retry() argument
251 old = ACCESS_ONCE(rw->lock); _raw_write_trylock_retry()
254 _raw_compare_and_delay(&rw->lock, old); _raw_write_trylock_retry()
257 if (_raw_compare_and_swap(&rw->lock, 0, 0x80000000)) _raw_write_trylock_retry()
/linux-4.1.27/tools/virtio/virtio-trace/
H A DMakefile9 trace-agent: trace-agent.o trace-agent-ctl.o trace-agent-rw.o
H A Dtrace-agent-rw.c70 pr_err("Could not create pipe in rw-thread(%d)\n", cpu); rw_thread_init()
79 pr_err("Could not change pipe size in rw-thread(%d)\n", cpu); rw_thread_init()
133 pr_err("Splice_read in rw-thread(%d)\n", ts->cpu_num); rw_thread_main()
155 pr_err("Splice_write in rw-thread(%d)\n", rw_thread_main()
187 pr_err("Could not create a rw thread(%d)\n", rw_ti->cpu_num); rw_thread_run()
H A Dtrace-agent.h43 /* use for stopping rw threads */
/linux-4.1.27/arch/arc/include/asm/
H A Dspinlock.h107 static inline int arch_read_trylock(arch_rwlock_t *rw) arch_read_trylock() argument
111 arch_spin_lock(&(rw->lock_mutex)); arch_read_trylock()
117 if (rw->counter > 0) { arch_read_trylock()
118 rw->counter--; arch_read_trylock()
122 arch_spin_unlock(&(rw->lock_mutex)); arch_read_trylock()
129 static inline int arch_write_trylock(arch_rwlock_t *rw) arch_write_trylock() argument
133 arch_spin_lock(&(rw->lock_mutex)); arch_write_trylock()
141 if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) { arch_write_trylock()
142 rw->counter = 0; arch_write_trylock()
145 arch_spin_unlock(&(rw->lock_mutex)); arch_write_trylock()
150 static inline void arch_read_lock(arch_rwlock_t *rw) arch_read_lock() argument
152 while (!arch_read_trylock(rw)) arch_read_lock()
156 static inline void arch_write_lock(arch_rwlock_t *rw) arch_write_lock() argument
158 while (!arch_write_trylock(rw)) arch_write_lock()
162 static inline void arch_read_unlock(arch_rwlock_t *rw) arch_read_unlock() argument
164 arch_spin_lock(&(rw->lock_mutex)); arch_read_unlock()
165 rw->counter++; arch_read_unlock()
166 arch_spin_unlock(&(rw->lock_mutex)); arch_read_unlock()
169 static inline void arch_write_unlock(arch_rwlock_t *rw) arch_write_unlock() argument
171 arch_spin_lock(&(rw->lock_mutex)); arch_write_unlock()
172 rw->counter = __ARCH_RW_LOCK_UNLOCKED__; arch_write_unlock()
173 arch_spin_unlock(&(rw->lock_mutex)); arch_write_unlock()
/linux-4.1.27/arch/sparc/include/asm/
H A Dspinlock_32.h80 static inline void __arch_read_lock(arch_rwlock_t *rw) __arch_read_lock() argument
83 lp = rw; __arch_read_lock()
100 static inline void __arch_read_unlock(arch_rwlock_t *rw) __arch_read_unlock() argument
103 lp = rw; __arch_read_unlock()
120 static inline void arch_write_lock(arch_rwlock_t *rw) arch_write_lock() argument
123 lp = rw; arch_write_lock()
143 static inline int arch_write_trylock(arch_rwlock_t *rw) arch_write_trylock() argument
149 : "r" (&rw->lock) arch_write_trylock()
153 val = rw->lock & ~0xff; arch_write_trylock()
155 ((volatile u8*)&rw->lock)[3] = 0; arch_write_trylock()
157 *(volatile u32*)&rw->lock = ~0U; arch_write_trylock()
163 static inline int __arch_read_trylock(arch_rwlock_t *rw) __arch_read_trylock() argument
167 lp = rw; __arch_read_trylock()
188 #define arch_read_lock_flags(rw, flags) arch_read_lock(rw)
189 #define arch_write_lock_flags(rw, flags) arch_write_lock(rw)
195 #define arch_read_can_lock(rw) (!((rw)->lock & 0xff))
196 #define arch_write_can_lock(rw) (!(rw)->lock)
H A Dspinlock_64.h216 #define arch_read_can_lock(rw) (!((rw)->lock & 0x80000000UL))
217 #define arch_write_can_lock(rw) (!(rw)->lock)
H A Ddma.h17 #define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
18 #define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
19 #define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
20 #define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
/linux-4.1.27/arch/tile/include/asm/
H A Dspinlock_64.h99 static inline int arch_read_can_lock(arch_rwlock_t *rw) arch_read_can_lock() argument
101 return !arch_write_val_locked(rw->lock); arch_read_can_lock()
108 static inline int arch_write_can_lock(arch_rwlock_t *rw) arch_write_can_lock() argument
110 return rw->lock == 0; arch_write_can_lock()
113 extern void __read_lock_failed(arch_rwlock_t *rw);
115 static inline void arch_read_lock(arch_rwlock_t *rw) arch_read_lock() argument
117 u32 val = __insn_fetchaddgez4(&rw->lock, 1); arch_read_lock()
119 __read_lock_failed(rw); arch_read_lock()
122 extern void __write_lock_failed(arch_rwlock_t *rw, u32 val);
124 static inline void arch_write_lock(arch_rwlock_t *rw) arch_write_lock() argument
126 u32 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT); arch_write_lock()
128 __write_lock_failed(rw, val); arch_write_lock()
131 static inline void arch_read_unlock(arch_rwlock_t *rw) arch_read_unlock() argument
134 __insn_fetchadd4(&rw->lock, -1); arch_read_unlock()
137 static inline void arch_write_unlock(arch_rwlock_t *rw) arch_write_unlock() argument
140 __insn_exch4(&rw->lock, 0); /* Avoid waiting in the write buffer. */ arch_write_unlock()
143 static inline int arch_read_trylock(arch_rwlock_t *rw) arch_read_trylock() argument
145 return !arch_write_val_locked(__insn_fetchaddgez4(&rw->lock, 1)); arch_read_trylock()
148 static inline int arch_write_trylock(arch_rwlock_t *rw) arch_write_trylock() argument
150 u32 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT); arch_write_trylock()
154 __insn_fetchand4(&rw->lock, ~__WRITE_LOCK_BIT); arch_write_trylock()
/linux-4.1.27/arch/mips/include/asm/
H A Dspinlock.h216 #define arch_read_can_lock(rw) ((rw)->lock >= 0)
222 #define arch_write_can_lock(rw) (!(rw)->lock)
224 static inline void arch_read_lock(arch_rwlock_t *rw) arch_read_lock() argument
238 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) arch_read_lock()
239 : GCC_OFF_SMALL_ASM() (rw->lock) arch_read_lock()
248 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) arch_read_lock()
249 : GCC_OFF_SMALL_ASM() (rw->lock) arch_read_lock()
257 static inline void arch_read_unlock(arch_rwlock_t *rw) arch_read_unlock() argument
269 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) arch_read_unlock()
270 : GCC_OFF_SMALL_ASM() (rw->lock) arch_read_unlock()
278 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) arch_read_unlock()
279 : GCC_OFF_SMALL_ASM() (rw->lock) arch_read_unlock()
285 static inline void arch_write_lock(arch_rwlock_t *rw) arch_write_lock() argument
299 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) arch_write_lock()
300 : GCC_OFF_SMALL_ASM() (rw->lock) arch_write_lock()
309 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) arch_write_lock()
310 : GCC_OFF_SMALL_ASM() (rw->lock) arch_write_lock()
318 static inline void arch_write_unlock(arch_rwlock_t *rw) arch_write_unlock() argument
325 : "=m" (rw->lock) arch_write_unlock()
326 : "m" (rw->lock) arch_write_unlock()
330 static inline int arch_read_trylock(arch_rwlock_t *rw) arch_read_trylock() argument
349 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret) arch_read_trylock()
350 : GCC_OFF_SMALL_ASM() (rw->lock) arch_read_trylock()
366 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret) arch_read_trylock()
367 : GCC_OFF_SMALL_ASM() (rw->lock) arch_read_trylock()
374 static inline int arch_write_trylock(arch_rwlock_t *rw) arch_write_trylock() argument
393 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret) arch_write_trylock()
394 : GCC_OFF_SMALL_ASM() (rw->lock) arch_write_trylock()
406 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), arch_write_trylock()
408 : GCC_OFF_SMALL_ASM() (rw->lock) arch_write_trylock()
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/
H A Ddma_defs.h87 /* Register rw_data, scope dma, type rw */
92 /* Register rw_data_next, scope dma, type rw */
97 /* Register rw_data_buf, scope dma, type rw */
102 /* Register rw_data_ctrl, scope dma, type rw */
114 /* Register rw_data_stat, scope dma, type rw */
123 /* Register rw_data_md, scope dma, type rw */
131 /* Register rw_data_md_s, scope dma, type rw */
139 /* Register rw_data_after, scope dma, type rw */
144 /* Register rw_ctxt, scope dma, type rw */
149 /* Register rw_ctxt_next, scope dma, type rw */
154 /* Register rw_ctxt_ctrl, scope dma, type rw */
167 /* Register rw_ctxt_stat, scope dma, type rw */
176 /* Register rw_ctxt_md0, scope dma, type rw */
184 /* Register rw_ctxt_md0_s, scope dma, type rw */
192 /* Register rw_ctxt_md1, scope dma, type rw */
197 /* Register rw_ctxt_md1_s, scope dma, type rw */
202 /* Register rw_ctxt_md2, scope dma, type rw */
207 /* Register rw_ctxt_md2_s, scope dma, type rw */
212 /* Register rw_ctxt_md3, scope dma, type rw */
217 /* Register rw_ctxt_md3_s, scope dma, type rw */
222 /* Register rw_ctxt_md4, scope dma, type rw */
227 /* Register rw_ctxt_md4_s, scope dma, type rw */
232 /* Register rw_saved_data, scope dma, type rw */
237 /* Register rw_saved_data_buf, scope dma, type rw */
242 /* Register rw_group, scope dma, type rw */
247 /* Register rw_group_next, scope dma, type rw */
252 /* Register rw_group_ctrl, scope dma, type rw */
266 /* Register rw_group_stat, scope dma, type rw */
275 /* Register rw_group_md, scope dma, type rw */
283 /* Register rw_group_md_s, scope dma, type rw */
291 /* Register rw_group_up, scope dma, type rw */
296 /* Register rw_group_down, scope dma, type rw */
301 /* Register rw_cmd, scope dma, type rw */
309 /* Register rw_cfg, scope dma, type rw */
318 /* Register rw_stat, scope dma, type rw */
329 /* Register rw_intr_mask, scope dma, type rw */
341 /* Register rw_ack_intr, scope dma, type rw */
375 /* Register rw_stream_cmd, scope dma, type rw */
H A Dbif_dma_defs.h87 /* Register rw_ch0_ctrl, scope bif_dma, type rw */
106 /* Register rw_ch0_addr, scope bif_dma, type rw */
113 /* Register rw_ch0_start, scope bif_dma, type rw */
121 /* Register rw_ch0_cnt, scope bif_dma, type rw */
137 /* Register rw_ch1_ctrl, scope bif_dma, type rw */
155 /* Register rw_ch1_addr, scope bif_dma, type rw */
162 /* Register rw_ch1_start, scope bif_dma, type rw */
170 /* Register rw_ch1_cnt, scope bif_dma, type rw */
186 /* Register rw_ch2_ctrl, scope bif_dma, type rw */
205 /* Register rw_ch2_addr, scope bif_dma, type rw */
212 /* Register rw_ch2_start, scope bif_dma, type rw */
220 /* Register rw_ch2_cnt, scope bif_dma, type rw */
236 /* Register rw_ch3_ctrl, scope bif_dma, type rw */
254 /* Register rw_ch3_addr, scope bif_dma, type rw */
261 /* Register rw_ch3_start, scope bif_dma, type rw */
269 /* Register rw_ch3_cnt, scope bif_dma, type rw */
285 /* Register rw_intr_mask, scope bif_dma, type rw */
296 /* Register rw_ack_intr, scope bif_dma, type rw */
327 /* Register rw_pin0_cfg, scope bif_dma, type rw */
338 /* Register rw_pin1_cfg, scope bif_dma, type rw */
349 /* Register rw_pin2_cfg, scope bif_dma, type rw */
360 /* Register rw_pin3_cfg, scope bif_dma, type rw */
371 /* Register rw_pin4_cfg, scope bif_dma, type rw */
382 /* Register rw_pin5_cfg, scope bif_dma, type rw */
393 /* Register rw_pin6_cfg, scope bif_dma, type rw */
404 /* Register rw_pin7_cfg, scope bif_dma, type rw */
H A Dextmem_defs.h87 /* Register rw_cse0_cfg, scope extmem, type rw */
106 /* Register rw_cse1_cfg, scope extmem, type rw */
125 /* Register rw_csr0_cfg, scope extmem, type rw */
144 /* Register rw_csr1_cfg, scope extmem, type rw */
163 /* Register rw_csp0_cfg, scope extmem, type rw */
182 /* Register rw_csp1_cfg, scope extmem, type rw */
201 /* Register rw_csp2_cfg, scope extmem, type rw */
220 /* Register rw_csp3_cfg, scope extmem, type rw */
239 /* Register rw_csp4_cfg, scope extmem, type rw */
258 /* Register rw_csp5_cfg, scope extmem, type rw */
277 /* Register rw_csp6_cfg, scope extmem, type rw */
296 /* Register rw_css_cfg, scope extmem, type rw */
315 /* Register rw_status_handle, scope extmem, type rw */
322 /* Register rw_wait_pin, scope extmem, type rw */
331 /* Register rw_gated_csp, scope extmem, type rw */
H A Deth_defs.h87 /* Register rw_ma0_lo, scope eth, type rw */
94 /* Register rw_ma0_hi, scope eth, type rw */
102 /* Register rw_ma1_lo, scope eth, type rw */
109 /* Register rw_ma1_hi, scope eth, type rw */
117 /* Register rw_ga_lo, scope eth, type rw */
124 /* Register rw_ga_hi, scope eth, type rw */
131 /* Register rw_gen_ctrl, scope eth, type rw */
145 /* Register rw_rec_ctrl, scope eth, type rw */
161 /* Register rw_tr_ctrl, scope eth, type rw */
176 /* Register rw_clr_err, scope eth, type rw */
184 /* Register rw_mgm_ctrl, scope eth, type rw */
256 /* Register rw_test_ctrl, scope eth, type rw */
266 /* Register rw_intr_mask, scope eth, type rw */
287 /* Register rw_ack_intr, scope eth, type rw */
H A Dbif_slave_defs.h87 /* Register rw_slave_cfg, scope bif_slave, type rw */
109 /* Register rw_ch0_cfg, scope bif_slave, type rw */
120 /* Register rw_ch1_cfg, scope bif_slave, type rw */
131 /* Register rw_ch2_cfg, scope bif_slave, type rw */
142 /* Register rw_ch3_cfg, scope bif_slave, type rw */
153 /* Register rw_arb_cfg, scope bif_slave, type rw */
178 /* Register rw_intr_mask, scope bif_slave, type rw */
187 /* Register rw_ack_intr, scope bif_slave, type rw */
H A Dser_defs.h87 /* Register rw_tr_ctrl, scope ser, type rw */
106 /* Register rw_tr_dma_en, scope ser, type rw */
114 /* Register rw_rec_ctrl, scope ser, type rw */
134 /* Register rw_tr_baud_div, scope ser, type rw */
142 /* Register rw_rec_baud_div, scope ser, type rw */
150 /* Register rw_xoff, scope ser, type rw */
159 /* Register rw_xoff_clr, scope ser, type rw */
167 /* Register rw_dout, scope ser, type rw */
217 /* Register rw_rec_eop, scope ser, type rw */
225 /* Register rw_intr_mask, scope ser, type rw */
236 /* Register rw_ack_intr, scope ser, type rw */
H A Data_defs.h87 /* Register rw_ctrl0, scope ata, type rw */
100 /* Register rw_ctrl1, scope ata, type rw */
109 /* Register rw_ctrl2, scope ata, type rw */
117 unsigned int rw : 1; member in struct:__anon348
144 /* Register rw_trf_cnt, scope ata, type rw */
159 /* Register rw_intr_mask, scope ata, type rw */
170 /* Register rw_ack_intr, scope ata, type rw */
H A Dmarb_defs.h88 /* Register rw_int_slots, scope marb, type rw */
97 /* Register rw_ext_slots, scope marb, type rw */
106 /* Register rw_regs_slots, scope marb, type rw */
114 /* Register rw_intr_mask, scope marb, type rw */
125 /* Register rw_ack_intr, scope marb, type rw */
156 /* Register rw_stop_mask, scope marb, type rw */
197 /* Register rw_no_snoop, scope marb, type rw */
218 /* Register rw_no_snoop_rq, scope marb, type rw */
346 /* Register rw_first_addr, scope marb_bp, type rw */
351 /* Register rw_last_addr, scope marb_bp, type rw */
356 /* Register rw_op, scope marb_bp, type rw */
371 /* Register rw_clients, scope marb_bp, type rw */
392 /* Register rw_options, scope marb_bp, type rw */
462 /* Register rw_ack, scope marb_bp, type rw */
H A Dmarb_bp_defs.h76 /* Register rw_first_addr, scope marb_bp, type rw */
81 /* Register rw_last_addr, scope marb_bp, type rw */
86 /* Register rw_op, scope marb_bp, type rw */
101 /* Register rw_clients, scope marb_bp, type rw */
122 /* Register rw_options, scope marb_bp, type rw */
192 /* Register rw_ack, scope marb_bp, type rw */
H A Drt_trace_defs.h87 /* Register rw_cfg, scope rt_trace, type rw */
103 /* Register rw_tap_ctrl, scope rt_trace, type rw */
120 /* Register rw_tap_data, scope rt_trace, type rw */
125 /* Register rw_tap_hdata, scope rt_trace, type rw */
H A Dbif_core_defs.h87 /* Register rw_grp1_cfg, scope bif_core, type rw */
104 /* Register rw_grp2_cfg, scope bif_core, type rw */
121 /* Register rw_grp3_cfg, scope bif_core, type rw */
142 /* Register rw_grp4_cfg, scope bif_core, type rw */
162 /* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
177 /* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
191 /* Register rw_sdram_timing, scope bif_core, type rw */
208 /* Register rw_sdram_cmd, scope bif_core, type rw */
H A Dsser_defs.h87 /* Register rw_cfg, scope sser, type rw */
107 /* Register rw_frm_cfg, scope sser, type rw */
129 /* Register rw_tr_cfg, scope sser, type rw */
155 /* Register rw_rec_cfg, scope sser, type rw */
179 /* Register rw_tr_data, scope sser, type rw */
202 /* Register rw_extra, scope sser, type rw */
213 /* Register rw_intr_mask, scope sser, type rw */
229 /* Register rw_ack_intr, scope sser, type rw */
H A Dconfig_defs.h98 /* Register rw_clk_ctrl, scope config, type rw */
115 /* Register rw_pad_ctrl, scope config, type rw */
/linux-4.1.27/fs/btrfs/
H A Dlocking.h33 void btrfs_set_lock_blocking_rw(struct extent_buffer *eb, int rw);
34 void btrfs_clear_lock_blocking_rw(struct extent_buffer *eb, int rw);
41 static inline void btrfs_tree_unlock_rw(struct extent_buffer *eb, int rw) btrfs_tree_unlock_rw() argument
43 if (rw == BTRFS_WRITE_LOCK || rw == BTRFS_WRITE_LOCK_BLOCKING) btrfs_tree_unlock_rw()
45 else if (rw == BTRFS_READ_LOCK_BLOCKING) btrfs_tree_unlock_rw()
47 else if (rw == BTRFS_READ_LOCK) btrfs_tree_unlock_rw()
H A Dcheck-integrity.h23 int btrfsic_submit_bh(int rw, struct buffer_head *bh);
24 void btrfsic_submit_bio(int rw, struct bio *bio);
25 int btrfsic_submit_bio_wait(int rw, struct bio *bio);
H A Dlocking.c31 * (indicated by the rw flag) this will bump the count
34 void btrfs_set_lock_blocking_rw(struct extent_buffer *eb, int rw) btrfs_set_lock_blocking_rw() argument
44 if (rw == BTRFS_WRITE_LOCK) { btrfs_set_lock_blocking_rw()
52 } else if (rw == BTRFS_READ_LOCK) { btrfs_set_lock_blocking_rw()
66 void btrfs_clear_lock_blocking_rw(struct extent_buffer *eb, int rw) btrfs_clear_lock_blocking_rw() argument
77 if (rw == BTRFS_WRITE_LOCK_BLOCKING) { btrfs_clear_lock_blocking_rw()
85 } else if (rw == BTRFS_READ_LOCK_BLOCKING) { btrfs_clear_lock_blocking_rw()
/linux-4.1.27/arch/xtensa/include/asm/
H A Dspinlock.h101 static inline void arch_write_lock(arch_rwlock_t *rw) arch_write_lock() argument
113 : "a" (&rw->lock) arch_write_lock()
119 static inline int arch_write_trylock(arch_rwlock_t *rw) arch_write_trylock() argument
130 : "a" (&rw->lock) arch_write_trylock()
136 static inline void arch_write_unlock(arch_rwlock_t *rw) arch_write_unlock() argument
144 : "a" (&rw->lock) arch_write_unlock()
148 static inline void arch_read_lock(arch_rwlock_t *rw) arch_read_lock() argument
161 : "a" (&rw->lock) arch_read_lock()
167 static inline int arch_read_trylock(arch_rwlock_t *rw) arch_read_trylock() argument
181 : "a" (&rw->lock) arch_read_trylock()
187 static inline void arch_read_unlock(arch_rwlock_t *rw) arch_read_unlock() argument
198 : "a" (&rw->lock) arch_read_unlock()
/linux-4.1.27/arch/sh/include/asm/
H A Dspinlock.h111 static inline void arch_read_lock(arch_rwlock_t *rw) arch_read_lock() argument
124 : "r" (&rw->lock) arch_read_lock()
129 static inline void arch_read_unlock(arch_rwlock_t *rw) arch_read_unlock() argument
140 : "r" (&rw->lock) arch_read_unlock()
145 static inline void arch_write_lock(arch_rwlock_t *rw) arch_write_lock() argument
158 : "r" (&rw->lock), "r" (RW_LOCK_BIAS) arch_write_lock()
163 static inline void arch_write_unlock(arch_rwlock_t *rw) arch_write_unlock() argument
168 : "r" (&rw->lock), "r" (RW_LOCK_BIAS) arch_write_unlock()
173 static inline int arch_read_trylock(arch_rwlock_t *rw) arch_read_trylock() argument
189 : "r" (&rw->lock) arch_read_trylock()
196 static inline int arch_write_trylock(arch_rwlock_t *rw) arch_write_trylock() argument
212 : "r" (&rw->lock), "r" (RW_LOCK_BIAS) arch_write_trylock()
/linux-4.1.27/arch/arm/include/asm/
H A Dspinlock.h141 static inline void arch_write_lock(arch_rwlock_t *rw) arch_write_lock() argument
145 prefetchw(&rw->lock); arch_write_lock()
154 : "r" (&rw->lock), "r" (0x80000000) arch_write_lock()
160 static inline int arch_write_trylock(arch_rwlock_t *rw) arch_write_trylock() argument
164 prefetchw(&rw->lock); arch_write_trylock()
172 : "r" (&rw->lock), "r" (0x80000000) arch_write_trylock()
184 static inline void arch_write_unlock(arch_rwlock_t *rw) arch_write_unlock() argument
191 : "r" (&rw->lock), "r" (0) arch_write_unlock()
212 static inline void arch_read_lock(arch_rwlock_t *rw) arch_read_lock() argument
216 prefetchw(&rw->lock); arch_read_lock()
225 : "r" (&rw->lock) arch_read_lock()
231 static inline void arch_read_unlock(arch_rwlock_t *rw) arch_read_unlock() argument
237 prefetchw(&rw->lock); arch_read_unlock()
245 : "r" (&rw->lock) arch_read_unlock()
252 static inline int arch_read_trylock(arch_rwlock_t *rw) arch_read_trylock() argument
256 prefetchw(&rw->lock); arch_read_trylock()
264 : "r" (&rw->lock) arch_read_trylock()
/linux-4.1.27/kernel/trace/
H A Dtrace_mmiotrace.c174 struct mmiotrace_rw *rw; mmio_print_rw() local
181 rw = &field->rw; mmio_print_rw()
183 switch (rw->opcode) { mmio_print_rw()
187 rw->width, secs, usec_rem, rw->map_id, mmio_print_rw()
188 (unsigned long long)rw->phys, mmio_print_rw()
189 rw->value, rw->pc, 0); mmio_print_rw()
194 rw->width, secs, usec_rem, rw->map_id, mmio_print_rw()
195 (unsigned long long)rw->phys, mmio_print_rw()
196 rw->value, rw->pc, 0); mmio_print_rw()
202 secs, usec_rem, rw->map_id, mmio_print_rw()
203 (unsigned long long)rw->phys, mmio_print_rw()
204 (rw->value >> 16) & 0xff, (rw->value >> 8) & 0xff, mmio_print_rw()
205 (rw->value >> 0) & 0xff, rw->pc, 0); mmio_print_rw()
208 trace_seq_puts(s, "rw what?\n"); mmio_print_rw()
299 struct mmiotrace_rw *rw) __trace_mmiotrace_rw()
314 entry->rw = *rw; __trace_mmiotrace_rw()
320 void mmio_trace_rw(struct mmiotrace_rw *rw) mmio_trace_rw() argument
324 __trace_mmiotrace_rw(tr, data, rw); mmio_trace_rw()
297 __trace_mmiotrace_rw(struct trace_array *tr, struct trace_array_cpu *data, struct mmiotrace_rw *rw) __trace_mmiotrace_rw() argument
H A Dtrace_entries.h267 __field_struct( struct mmiotrace_rw, rw )
268 __field_desc( resource_size_t, rw, phys )
269 __field_desc( unsigned long, rw, value )
270 __field_desc( unsigned long, rw, pc )
271 __field_desc( int, rw, map_id )
272 __field_desc( unsigned char, rw, opcode )
273 __field_desc( unsigned char, rw, width )
H A Dblktrace.c194 #define MASK_TC_BIT(rw, __name) ((rw & REQ_ ## __name) << \
202 int rw, u32 what, int error, int pdu_len, void *pdu_data) __blk_add_trace()
217 what |= ddir_act[rw & WRITE]; __blk_add_trace()
218 what |= MASK_TC_BIT(rw, SYNC); __blk_add_trace()
219 what |= MASK_TC_BIT(rw, RAHEAD); __blk_add_trace()
220 what |= MASK_TC_BIT(rw, META); __blk_add_trace()
221 what |= MASK_TC_BIT(rw, DISCARD); __blk_add_trace()
222 what |= MASK_TC_BIT(rw, FLUSH); __blk_add_trace()
223 what |= MASK_TC_BIT(rw, FUA); __blk_add_trace()
827 struct bio *bio, int rw) blk_add_trace_getrq()
835 __blk_add_trace(bt, 0, 0, rw, BLK_TA_GETRQ, 0, 0, NULL); blk_add_trace_getrq()
842 struct bio *bio, int rw) blk_add_trace_sleeprq()
850 __blk_add_trace(bt, 0, 0, rw, BLK_TA_SLEEPRQ, blk_add_trace_sleeprq()
1787 void blk_fill_rwbs(char *rwbs, u32 rw, int bytes) blk_fill_rwbs() argument
1791 if (rw & REQ_FLUSH) blk_fill_rwbs()
1794 if (rw & WRITE) blk_fill_rwbs()
1796 else if (rw & REQ_DISCARD) blk_fill_rwbs()
1803 if (rw & REQ_FUA) blk_fill_rwbs()
1805 if (rw & REQ_RAHEAD) blk_fill_rwbs()
1807 if (rw & REQ_SYNC) blk_fill_rwbs()
1809 if (rw & REQ_META) blk_fill_rwbs()
1811 if (rw & REQ_SECURE) blk_fill_rwbs()
201 __blk_add_trace(struct blk_trace *bt, sector_t sector, int bytes, int rw, u32 what, int error, int pdu_len, void *pdu_data) __blk_add_trace() argument
825 blk_add_trace_getrq(void *ignore, struct request_queue *q, struct bio *bio, int rw) blk_add_trace_getrq() argument
840 blk_add_trace_sleeprq(void *ignore, struct request_queue *q, struct bio *bio, int rw) blk_add_trace_sleeprq() argument
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/
H A Dpio_defs_asm.h53 /* Register rw_data, scope pio, type rw */
56 /* Register rw_io_access0, scope pio, type rw */
61 /* Register rw_io_access1, scope pio, type rw */
66 /* Register rw_io_access2, scope pio, type rw */
71 /* Register rw_io_access3, scope pio, type rw */
76 /* Register rw_io_access4, scope pio, type rw */
81 /* Register rw_io_access5, scope pio, type rw */
86 /* Register rw_io_access6, scope pio, type rw */
91 /* Register rw_io_access7, scope pio, type rw */
96 /* Register rw_io_access8, scope pio, type rw */
101 /* Register rw_io_access9, scope pio, type rw */
106 /* Register rw_io_access10, scope pio, type rw */
111 /* Register rw_io_access11, scope pio, type rw */
116 /* Register rw_io_access12, scope pio, type rw */
121 /* Register rw_io_access13, scope pio, type rw */
126 /* Register rw_io_access14, scope pio, type rw */
131 /* Register rw_io_access15, scope pio, type rw */
136 /* Register rw_ce0_cfg, scope pio, type rw */
149 /* Register rw_ce1_cfg, scope pio, type rw */
162 /* Register rw_ce2_cfg, scope pio, type rw */
175 /* Register rw_dout, scope pio, type rw */
204 /* Register rw_oe, scope pio, type rw */
233 /* Register rw_man_ctrl, scope pio, type rw */
297 /* Register rw_intr_mask, scope pio, type rw */
303 /* Register rw_ack_intr, scope pio, type rw */
H A Dgio_defs_asm.h58 /* Register rw_pa_dout, scope gio, type rw */
63 /* Register rw_pa_oe, scope gio, type rw */
68 /* Register rw_pa_byte0_dout, scope gio, type rw */
73 /* Register rw_pa_byte0_oe, scope gio, type rw */
78 /* Register rw_pa_byte1_dout, scope gio, type rw */
83 /* Register rw_pa_byte1_oe, scope gio, type rw */
88 /* Register rw_pa_byte2_dout, scope gio, type rw */
93 /* Register rw_pa_byte2_oe, scope gio, type rw */
98 /* Register rw_pa_byte3_dout, scope gio, type rw */
103 /* Register rw_pa_byte3_oe, scope gio, type rw */
113 /* Register rw_pb_dout, scope gio, type rw */
118 /* Register rw_pb_oe, scope gio, type rw */
123 /* Register rw_pb_byte0_dout, scope gio, type rw */
128 /* Register rw_pb_byte0_oe, scope gio, type rw */
133 /* Register rw_pb_byte1_dout, scope gio, type rw */
138 /* Register rw_pb_byte1_oe, scope gio, type rw */
143 /* Register rw_pb_byte2_dout, scope gio, type rw */
148 /* Register rw_pb_byte2_oe, scope gio, type rw */
153 /* Register rw_pb_byte3_dout, scope gio, type rw */
158 /* Register rw_pb_byte3_oe, scope gio, type rw */
168 /* Register rw_pc_dout, scope gio, type rw */
173 /* Register rw_pc_oe, scope gio, type rw */
178 /* Register rw_pc_byte0_dout, scope gio, type rw */
183 /* Register rw_pc_byte0_oe, scope gio, type rw */
188 /* Register rw_pc_byte1_dout, scope gio, type rw */
193 /* Register rw_pc_byte1_oe, scope gio, type rw */
203 /* Register rw_intr_cfg, scope gio, type rw */
222 /* Register rw_intr_pins, scope gio, type rw */
241 /* Register rw_intr_mask, scope gio, type rw */
274 /* Register rw_ack_intr, scope gio, type rw */
373 /* Register rw_i2c0_start, scope gio, type rw */
379 /* Register rw_i2c0_cfg, scope gio, type rw */
400 /* Register rw_i2c0_ctrl, scope gio, type rw */
441 /* Register rw_i2c0_data, scope gio, type rw */
452 /* Register rw_i2c0_data2, scope gio, type rw */
463 /* Register rw_i2c1_start, scope gio, type rw */
469 /* Register rw_i2c1_cfg, scope gio, type rw */
518 /* Register rw_i2c1_ctrl, scope gio, type rw */
559 /* Register rw_i2c1_data, scope gio, type rw */
570 /* Register rw_i2c1_data2, scope gio, type rw */
586 /* Register rw_ppwm_data, scope gio, type rw */
591 /* Register rw_pwm0_ctrl, scope gio, type rw */
602 /* Register rw_pwm0_var, scope gio, type rw */
609 /* Register rw_pwm0_data, scope gio, type rw */
614 /* Register rw_pwm1_ctrl, scope gio, type rw */
625 /* Register rw_pwm1_var, scope gio, type rw */
632 /* Register rw_pwm1_data, scope gio, type rw */
637 /* Register rw_pwm2_ctrl, scope gio, type rw */
648 /* Register rw_pwm2_var, scope gio, type rw */
655 /* Register rw_pwm2_data, scope gio, type rw */
660 /* Register rw_pwm_in_cfg, scope gio, type rw */
H A Dtimer_defs_asm.h53 /* Register rw_tmr0_div, scope timer, type rw */
59 /* Register rw_tmr0_ctrl, scope timer, type rw */
66 /* Register rw_tmr1_div, scope timer, type rw */
72 /* Register rw_tmr1_ctrl, scope timer, type rw */
93 /* Register rw_cnt_cfg, scope timer, type rw */
98 /* Register rw_trig, scope timer, type rw */
101 /* Register rw_trig_cfg, scope timer, type rw */
109 /* Register rw_out, scope timer, type rw */
114 /* Register rw_wd_ctrl, scope timer, type rw */
132 /* Register rw_intr_mask, scope timer, type rw */
147 /* Register rw_ack_intr, scope timer, type rw */
192 /* Register rw_test, scope timer, type rw */
H A Dddr2_defs_asm.h53 /* Register rw_cfg, scope ddr2, type rw */
85 /* Register rw_timing, scope ddr2, type rw */
106 /* Register rw_latency, scope ddr2, type rw */
113 /* Register rw_phy_cfg, scope ddr2, type rw */
119 /* Register rw_phy_ctrl, scope ddr2, type rw */
131 /* Register rw_ctrl, scope ddr2, type rw */
138 /* Register rw_pwr_down, scope ddr2, type rw */
164 /* Register rw_imp_ctrl, scope ddr2, type rw */
172 /* Register rw_dll_ctrl, scope ddr2, type rw */
181 /* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
H A Dpinmux_defs_asm.h53 /* Register rw_hwprot, scope pinmux, type rw */
128 /* Register rw_gio_pa, scope pinmux, type rw */
227 /* Register rw_gio_pb, scope pinmux, type rw */
326 /* Register rw_gio_pc, scope pinmux, type rw */
377 /* Register rw_iop_pa, scope pinmux, type rw */
476 /* Register rw_iop_pb, scope pinmux, type rw */
503 /* Register rw_iop_pio, scope pinmux, type rw */
554 /* Register rw_iop_usb, scope pinmux, type rw */
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
H A Dpio_defs.h84 /* Register rw_data, scope pio, type rw */
89 /* Register rw_io_access0, scope pio, type rw */
97 /* Register rw_io_access1, scope pio, type rw */
105 /* Register rw_io_access2, scope pio, type rw */
113 /* Register rw_io_access3, scope pio, type rw */
121 /* Register rw_io_access4, scope pio, type rw */
129 /* Register rw_io_access5, scope pio, type rw */
137 /* Register rw_io_access6, scope pio, type rw */
145 /* Register rw_io_access7, scope pio, type rw */
153 /* Register rw_io_access8, scope pio, type rw */
161 /* Register rw_io_access9, scope pio, type rw */
169 /* Register rw_io_access10, scope pio, type rw */
177 /* Register rw_io_access11, scope pio, type rw */
185 /* Register rw_io_access12, scope pio, type rw */
193 /* Register rw_io_access13, scope pio, type rw */
201 /* Register rw_io_access14, scope pio, type rw */
209 /* Register rw_io_access15, scope pio, type rw */
217 /* Register rw_ce0_cfg, scope pio, type rw */
229 /* Register rw_ce1_cfg, scope pio, type rw */
241 /* Register rw_ce2_cfg, scope pio, type rw */
253 /* Register rw_dout, scope pio, type rw */
269 /* Register rw_oe, scope pio, type rw */
285 /* Register rw_man_ctrl, scope pio, type rw */
323 /* Register rw_intr_mask, scope pio, type rw */
331 /* Register rw_ack_intr, scope pio, type rw */
H A Dgio_defs.h90 /* Register rw_pa_dout, scope gio, type rw */
97 /* Register rw_pa_oe, scope gio, type rw */
104 /* Register rw_pa_byte0_dout, scope gio, type rw */
112 /* Register rw_pa_byte0_oe, scope gio, type rw */
120 /* Register rw_pa_byte1_dout, scope gio, type rw */
128 /* Register rw_pa_byte1_oe, scope gio, type rw */
136 /* Register rw_pa_byte2_dout, scope gio, type rw */
144 /* Register rw_pa_byte2_oe, scope gio, type rw */
152 /* Register rw_pa_byte3_dout, scope gio, type rw */
160 /* Register rw_pa_byte3_oe, scope gio, type rw */
174 /* Register rw_pb_dout, scope gio, type rw */
181 /* Register rw_pb_oe, scope gio, type rw */
188 /* Register rw_pb_byte0_dout, scope gio, type rw */
196 /* Register rw_pb_byte0_oe, scope gio, type rw */
204 /* Register rw_pb_byte1_dout, scope gio, type rw */
212 /* Register rw_pb_byte1_oe, scope gio, type rw */
220 /* Register rw_pb_byte2_dout, scope gio, type rw */
228 /* Register rw_pb_byte2_oe, scope gio, type rw */
236 /* Register rw_pb_byte3_dout, scope gio, type rw */
244 /* Register rw_pb_byte3_oe, scope gio, type rw */
259 /* Register rw_pc_dout, scope gio, type rw */
267 /* Register rw_pc_oe, scope gio, type rw */
275 /* Register rw_pc_byte0_dout, scope gio, type rw */
283 /* Register rw_pc_byte0_oe, scope gio, type rw */
291 /* Register rw_pc_byte1_dout, scope gio, type rw */
299 /* Register rw_pc_byte1_oe, scope gio, type rw */
313 /* Register rw_intr_cfg, scope gio, type rw */
328 /* Register rw_intr_pins, scope gio, type rw */
342 /* Register rw_intr_mask, scope gio, type rw */
359 /* Register rw_ack_intr, scope gio, type rw */
408 /* Register rw_i2c0_start, scope gio, type rw */
416 /* Register rw_i2c0_cfg, scope gio, type rw */
429 /* Register rw_i2c0_ctrl, scope gio, type rw */
450 /* Register rw_i2c0_data, scope gio, type rw */
460 /* Register rw_i2c0_data2, scope gio, type rw */
471 /* Register rw_i2c1_start, scope gio, type rw */
479 /* Register rw_i2c1_cfg, scope gio, type rw */
502 /* Register rw_i2c1_ctrl, scope gio, type rw */
523 /* Register rw_i2c1_data, scope gio, type rw */
533 /* Register rw_i2c1_data2, scope gio, type rw */
551 /* Register rw_ppwm_data, scope gio, type rw */
559 /* Register rw_pwm0_ctrl, scope gio, type rw */
569 /* Register rw_pwm0_var, scope gio, type rw */
578 /* Register rw_pwm0_data, scope gio, type rw */
586 /* Register rw_pwm1_ctrl, scope gio, type rw */
596 /* Register rw_pwm1_var, scope gio, type rw */
605 /* Register rw_pwm1_data, scope gio, type rw */
613 /* Register rw_pwm2_ctrl, scope gio, type rw */
623 /* Register rw_pwm2_var, scope gio, type rw */
632 /* Register rw_pwm2_data, scope gio, type rw */
640 /* Register rw_pwm_in_cfg, scope gio, type rw */
H A Dmarb_foo_defs.h85 /* Register rw_intm_slots, scope marb_foo, type rw */
94 /* Register rw_l2_slots, scope marb_foo, type rw */
103 /* Register rw_regs_slots, scope marb_foo, type rw */
111 /* Register rw_sclr_burst, scope marb_foo, type rw */
120 /* Register rw_dma0_burst, scope marb_foo, type rw */
129 /* Register rw_dma1_burst, scope marb_foo, type rw */
138 /* Register rw_dma2_burst, scope marb_foo, type rw */
147 /* Register rw_dma3_burst, scope marb_foo, type rw */
156 /* Register rw_dma4_burst, scope marb_foo, type rw */
165 /* Register rw_dma5_burst, scope marb_foo, type rw */
174 /* Register rw_dma6_burst, scope marb_foo, type rw */
183 /* Register rw_dma7_burst, scope marb_foo, type rw */
192 /* Register rw_dma9_burst, scope marb_foo, type rw */
201 /* Register rw_dma11_burst, scope marb_foo, type rw */
210 /* Register rw_cpui_burst, scope marb_foo, type rw */
219 /* Register rw_cpud_burst, scope marb_foo, type rw */
228 /* Register rw_iop_burst, scope marb_foo, type rw */
237 /* Register rw_ccdstat_burst, scope marb_foo, type rw */
246 /* Register rw_intr_mask, scope marb_foo, type rw */
257 /* Register rw_ack_intr, scope marb_foo, type rw */
288 /* Register rw_stop_mask, scope marb_foo, type rw */
331 /* Register rw_no_snoop, scope marb_foo, type rw */
353 /* Register rw_no_snoop_rq, scope marb_foo, type rw */
494 /* Register rw_first_addr, scope marb_foo_bp, type rw */
499 /* Register rw_last_addr, scope marb_foo_bp, type rw */
504 /* Register rw_op, scope marb_foo_bp, type rw */
519 /* Register rw_clients, scope marb_foo_bp, type rw */
541 /* Register rw_options, scope marb_foo_bp, type rw */
613 /* Register rw_ack, scope marb_foo_bp, type rw */
H A Dmarb_bar_defs.h85 /* Register rw_ddr2_slots, scope marb_bar, type rw */
93 /* Register rw_h264_rd_burst, scope marb_bar, type rw */
101 /* Register rw_h264_wr_burst, scope marb_bar, type rw */
109 /* Register rw_ccd_burst, scope marb_bar, type rw */
117 /* Register rw_vin_wr_burst, scope marb_bar, type rw */
125 /* Register rw_vin_rd_burst, scope marb_bar, type rw */
133 /* Register rw_sclr_rd_burst, scope marb_bar, type rw */
141 /* Register rw_vout_burst, scope marb_bar, type rw */
149 /* Register rw_sclr_fifo_burst, scope marb_bar, type rw */
157 /* Register rw_l2cache_burst, scope marb_bar, type rw */
165 /* Register rw_intr_mask, scope marb_bar, type rw */
176 /* Register rw_ack_intr, scope marb_bar, type rw */
207 /* Register rw_stop_mask, scope marb_bar, type rw */
238 /* Register rw_no_snoop, scope marb_bar, type rw */
368 /* Register rw_first_addr, scope marb_bar_bp, type rw */
373 /* Register rw_last_addr, scope marb_bar_bp, type rw */
378 /* Register rw_op, scope marb_bar_bp, type rw */
393 /* Register rw_clients, scope marb_bar_bp, type rw */
409 /* Register rw_options, scope marb_bar_bp, type rw */
469 /* Register rw_ack, scope marb_bar_bp, type rw */
H A Dtimer_defs.h84 /* Register rw_tmr0_div, scope timer, type rw */
93 /* Register rw_tmr0_ctrl, scope timer, type rw */
102 /* Register rw_tmr1_div, scope timer, type rw */
111 /* Register rw_tmr1_ctrl, scope timer, type rw */
134 /* Register rw_cnt_cfg, scope timer, type rw */
142 /* Register rw_trig, scope timer, type rw */
147 /* Register rw_trig_cfg, scope timer, type rw */
159 /* Register rw_out, scope timer, type rw */
167 /* Register rw_wd_ctrl, scope timer, type rw */
185 /* Register rw_intr_mask, scope timer, type rw */
196 /* Register rw_ack_intr, scope timer, type rw */
227 /* Register rw_test, scope timer, type rw */
H A Dl2cache_defs.h84 /* Register rw_cfg, scope l2cache, type rw */
92 /* Register rw_ctrl, scope l2cache, type rw */
103 /* Register rw_idxop, scope l2cache, type rw */
114 /* Register rw_addrop_addr, scope l2cache, type rw */
121 /* Register rw_addrop_ctrl, scope l2cache, type rw */
H A Dddr2_defs.h84 /* Register rw_cfg, scope ddr2, type rw */
102 /* Register rw_timing, scope ddr2, type rw */
117 /* Register rw_latency, scope ddr2, type rw */
126 /* Register rw_phy_cfg, scope ddr2, type rw */
134 /* Register rw_phy_ctrl, scope ddr2, type rw */
144 /* Register rw_ctrl, scope ddr2, type rw */
153 /* Register rw_pwr_down, scope ddr2, type rw */
174 /* Register rw_imp_ctrl, scope ddr2, type rw */
184 /* Register rw_dll_ctrl, scope ddr2, type rw */
194 /* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
H A Dpinmux_defs.h84 /* Register rw_hwprot, scope pinmux, type rw */
115 /* Register rw_gio_pa, scope pinmux, type rw */
153 /* Register rw_gio_pb, scope pinmux, type rw */
191 /* Register rw_gio_pc, scope pinmux, type rw */
214 /* Register rw_iop_pa, scope pinmux, type rw */
252 /* Register rw_iop_pb, scope pinmux, type rw */
267 /* Register rw_iop_pio, scope pinmux, type rw */
290 /* Register rw_iop_usb, scope pinmux, type rw */
H A Dintr_vect_defs.h86 /* Register rw_mask0, scope intr_vect, type rw */
208 /* Register rw_xmask0, scope intr_vect, type rw */
249 /* Register rw_mask1, scope intr_vect, type rw */
286 /* Register rw_xmask1, scope intr_vect, type rw */
299 /* Register rw_xmask_ctrl, scope intr_vect, type rw */
323 /* Register rw_ipi, scope intr_vect, type rw */
/linux-4.1.27/arch/powerpc/include/asm/
H A Dspinlock.h185 #define arch_read_can_lock(rw) ((rw)->lock >= 0)
186 #define arch_write_can_lock(rw) (!(rw)->lock)
200 static inline long __arch_read_trylock(arch_rwlock_t *rw) __arch_read_trylock() argument
214 : "r" (&rw->lock) __arch_read_trylock()
224 static inline long __arch_write_trylock(arch_rwlock_t *rw) __arch_write_trylock() argument
238 : "r" (token), "r" (&rw->lock) __arch_write_trylock()
244 static inline void arch_read_lock(arch_rwlock_t *rw) arch_read_lock() argument
247 if (likely(__arch_read_trylock(rw) > 0)) arch_read_lock()
252 __rw_yield(rw); arch_read_lock()
253 } while (unlikely(rw->lock < 0)); arch_read_lock()
258 static inline void arch_write_lock(arch_rwlock_t *rw) arch_write_lock() argument
261 if (likely(__arch_write_trylock(rw) == 0)) arch_write_lock()
266 __rw_yield(rw); arch_write_lock()
267 } while (unlikely(rw->lock != 0)); arch_write_lock()
272 static inline int arch_read_trylock(arch_rwlock_t *rw) arch_read_trylock() argument
274 return __arch_read_trylock(rw) > 0; arch_read_trylock()
277 static inline int arch_write_trylock(arch_rwlock_t *rw) arch_write_trylock() argument
279 return __arch_write_trylock(rw) == 0; arch_write_trylock()
282 static inline void arch_read_unlock(arch_rwlock_t *rw) arch_read_unlock() argument
295 : "r"(&rw->lock) arch_read_unlock()
299 static inline void arch_write_unlock(arch_rwlock_t *rw) arch_write_unlock() argument
303 rw->lock = 0; arch_write_unlock()
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/
H A Diop_sw_cfg_defs.h84 /* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */
92 /* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */
100 /* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */
108 /* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */
116 /* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */
124 /* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */
132 /* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */
140 /* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
148 /* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
156 /* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */
164 /* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */
172 /* Register rw_spu_owner, scope iop_sw_cfg, type rw */
180 /* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
188 /* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
196 /* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
204 /* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
212 /* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
220 /* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
228 /* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
236 /* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
244 /* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
252 /* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
260 /* Register rw_bus_mask, scope iop_sw_cfg, type rw */
270 /* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */
281 /* Register rw_gio_mask, scope iop_sw_cfg, type rw */
288 /* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
295 /* Register rw_pinmapping, scope iop_sw_cfg, type rw */
314 /* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
325 /* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
340 /* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
355 /* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
370 /* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
385 /* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
400 /* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
415 /* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
430 /* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
445 /* Register rw_spu_cfg, scope iop_sw_cfg, type rw */
454 /* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
470 /* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
486 /* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
509 /* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */
521 /* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
H A Diop_sw_spu_defs.h88 /* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
99 /* Register rw_mc_data, scope iop_sw_spu, type rw */
106 /* Register rw_mc_addr, scope iop_sw_spu, type rw */
131 /* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */
141 /* Register rw_bus_set_mask, scope iop_sw_spu, type rw */
151 /* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */
162 /* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */
177 /* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
184 /* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
191 /* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
198 /* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
209 /* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */
218 /* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */
227 /* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */
236 /* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */
245 /* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
253 /* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
261 /* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
269 /* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
277 /* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
285 /* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
293 /* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
301 /* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
309 /* Register rw_cpu_intr, scope iop_sw_spu, type rw */
376 /* Register rw_mpu_intr, scope iop_sw_spu, type rw */
H A Diop_sw_mpu_defs.h84 /* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
100 /* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
111 /* Register rw_mc_data, scope iop_sw_mpu, type rw */
118 /* Register rw_mc_addr, scope iop_sw_mpu, type rw */
143 /* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */
153 /* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */
163 /* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */
174 /* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */
189 /* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
196 /* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
203 /* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
210 /* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
221 /* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
296 /* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
319 /* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
377 /* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
400 /* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
458 /* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
481 /* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
539 /* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
562 /* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
H A Diop_sw_cpu_defs.h96 /* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
107 /* Register rw_mc_data, scope iop_sw_cpu, type rw */
114 /* Register rw_mc_addr, scope iop_sw_cpu, type rw */
139 /* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */
149 /* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */
159 /* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */
170 /* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */
185 /* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
192 /* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
199 /* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
206 /* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
217 /* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
255 /* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
367 /* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
405 /* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
H A Diop_sap_out_defs.h84 /* Register rw_gen_gated, scope iop_sap_out, type rw */
97 /* Register rw_bus, scope iop_sap_out, type rw */
124 /* Register rw_bus_lo_oe, scope iop_sap_out, type rw */
145 /* Register rw_bus_hi_oe, scope iop_sap_out, type rw */
167 /* Register rw_gio, scope iop_sap_out, type rw */
H A Diop_sap_in_defs.h85 /* Register rw_bus_byte, scope iop_sap_in, type rw */
97 /* Register rw_gio, scope iop_sap_in, type rw */
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/iop/
H A Diop_sw_cfg_defs.h87 /* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */
95 /* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */
103 /* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */
111 /* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */
119 /* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */
127 /* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */
135 /* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */
143 /* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */
151 /* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */
159 /* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */
167 /* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */
175 /* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */
183 /* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */
191 /* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */
199 /* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
207 /* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
215 /* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */
223 /* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */
231 /* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */
239 /* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */
247 /* Register rw_spu0_owner, scope iop_sw_cfg, type rw */
255 /* Register rw_spu1_owner, scope iop_sw_cfg, type rw */
263 /* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
271 /* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
279 /* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */
287 /* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */
295 /* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
303 /* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
311 /* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
319 /* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
327 /* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
335 /* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
343 /* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
351 /* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
359 /* Register rw_bus0_mask, scope iop_sw_cfg, type rw */
369 /* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */
380 /* Register rw_bus1_mask, scope iop_sw_cfg, type rw */
390 /* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */
401 /* Register rw_gio_mask, scope iop_sw_cfg, type rw */
408 /* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
415 /* Register rw_pinmapping, scope iop_sw_cfg, type rw */
437 /* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
452 /* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
467 /* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
482 /* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
497 /* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
512 /* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
527 /* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
542 /* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
557 /* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
572 /* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */
581 /* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */
590 /* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
606 /* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
622 /* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */
638 /* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */
654 /* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
677 /* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */
691 /* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */
705 /* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
H A Diop_crc_par_defs.h87 /* Register rw_cfg, scope iop_crc_par, type rw */
100 /* Register rw_init_crc, scope iop_crc_par, type rw */
105 /* Register rw_correct_crc, scope iop_crc_par, type rw */
110 /* Register rw_ctrl, scope iop_crc_par, type rw */
118 /* Register rw_set_last, scope iop_crc_par, type rw */
126 /* Register rw_wr1byte, scope iop_crc_par, type rw */
134 /* Register rw_wr2byte, scope iop_crc_par, type rw */
142 /* Register rw_wr3byte, scope iop_crc_par, type rw */
150 /* Register rw_wr4byte, scope iop_crc_par, type rw */
157 /* Register rw_wr1byte_last, scope iop_crc_par, type rw */
165 /* Register rw_wr2byte_last, scope iop_crc_par, type rw */
173 /* Register rw_wr3byte_last, scope iop_crc_par, type rw */
181 /* Register rw_wr4byte_last, scope iop_crc_par, type rw */
204 /* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */
H A Diop_sw_spu_defs.h87 /* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
99 /* Register rw_mc_data, scope iop_sw_spu, type rw */
106 /* Register rw_mc_addr, scope iop_sw_spu, type rw */
133 /* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */
143 /* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */
153 /* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */
164 /* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */
179 /* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */
189 /* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */
199 /* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */
210 /* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */
225 /* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
232 /* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
239 /* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
246 /* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
257 /* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */
266 /* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */
275 /* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */
284 /* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */
293 /* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */
302 /* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */
311 /* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */
320 /* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */
329 /* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
337 /* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
345 /* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
353 /* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
361 /* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
369 /* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
377 /* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
385 /* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
393 /* Register rw_cpu_intr, scope iop_sw_spu, type rw */
468 /* Register rw_mpu_intr, scope iop_sw_spu, type rw */
H A Diop_fifo_out_defs.h87 /* Register rw_cfg, scope iop_fifo_out, type rw */
101 /* Register rw_ctrl, scope iop_fifo_out, type rw */
121 /* Register rw_wr1byte, scope iop_fifo_out, type rw */
129 /* Register rw_wr2byte, scope iop_fifo_out, type rw */
137 /* Register rw_wr3byte, scope iop_fifo_out, type rw */
145 /* Register rw_wr4byte, scope iop_fifo_out, type rw */
152 /* Register rw_wr1byte_last, scope iop_fifo_out, type rw */
160 /* Register rw_wr2byte_last, scope iop_fifo_out, type rw */
168 /* Register rw_wr3byte_last, scope iop_fifo_out, type rw */
176 /* Register rw_wr4byte_last, scope iop_fifo_out, type rw */
183 /* Register rw_set_last, scope iop_fifo_out, type rw */
196 /* Register rw_strb_dif_out, scope iop_fifo_out, type rw */
201 /* Register rw_intr_mask, scope iop_fifo_out, type rw */
213 /* Register rw_ack_intr, scope iop_fifo_out, type rw */
H A Diop_scrc_in_defs.h87 /* Register rw_cfg, scope iop_scrc_in, type rw */
95 /* Register rw_ctrl, scope iop_scrc_in, type rw */
110 /* Register rw_init_crc, scope iop_scrc_in, type rw */
123 /* Register rw_crc, scope iop_scrc_in, type rw */
128 /* Register rw_correct_crc, scope iop_scrc_in, type rw */
133 /* Register rw_wr1bit, scope iop_scrc_in, type rw */
H A Diop_spu_defs.h88 /* Register rw_r, scope iop_spu, type rw */
93 /* Register rw_seq_pc, scope iop_spu, type rw */
101 /* Register rw_fsm_pc, scope iop_spu, type rw */
109 /* Register rw_ctrl, scope iop_spu, type rw */
118 /* Register rw_fsm_inputs3_0, scope iop_spu, type rw */
132 /* Register rw_fsm_inputs7_4, scope iop_spu, type rw */
146 /* Register rw_gio_out, scope iop_spu, type rw */
151 /* Register rw_bus0_out, scope iop_spu, type rw */
156 /* Register rw_bus1_out, scope iop_spu, type rw */
173 /* Register rw_gio_out_set, scope iop_spu, type rw */
178 /* Register rw_gio_out_clr, scope iop_spu, type rw */
289 /* Register rw_reg_access, scope iop_spu, type rw */
299 /* Register rw_event_cfg, scope iop_spu, type rw */
313 /* Register rw_event_mask, scope iop_spu, type rw */
319 /* Register rw_event_val, scope iop_spu, type rw */
324 /* Register rw_event_ret, scope iop_spu, type rw */
366 /* Register rw_brp, scope iop_spu, type rw */
H A Diop_dmc_in_defs.h87 /* Register rw_cfg, scope iop_dmc_in, type rw */
96 /* Register rw_ctrl, scope iop_dmc_in, type rw */
113 /* Register rw_stream_cmd, scope iop_dmc_in, type rw */
123 /* Register rw_stream_wr_data, scope iop_dmc_in, type rw */
128 /* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */
133 /* Register rw_stream_ctrl, scope iop_dmc_in, type rw */
191 /* Register rw_data_descr, scope iop_dmc_in, type rw */
199 /* Register rw_ctxt_descr, scope iop_dmc_in, type rw */
207 /* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */
212 /* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */
217 /* Register rw_group_descr, scope iop_dmc_in, type rw */
225 /* Register rw_intr_mask, scope iop_dmc_in, type rw */
238 /* Register rw_ack_intr, scope iop_dmc_in, type rw */
H A Diop_timer_grp_defs.h87 /* Register rw_cfg, scope iop_timer_grp, type rw */
98 /* Register rw_half_period, scope iop_timer_grp, type rw */
108 /* Register rw_half_period_len, scope iop_timer_grp, type rw */
114 /* Register rw_tmr_cfg, scope iop_timer_grp, type rw */
133 /* Register rw_tmr_len, scope iop_timer_grp, type rw */
141 /* Register rw_cmd, scope iop_timer_grp, type rw */
172 /* Register rw_intr_mask, scope iop_timer_grp, type rw */
183 /* Register rw_ack_intr, scope iop_timer_grp, type rw */
H A Diop_scrc_out_defs.h87 /* Register rw_cfg, scope iop_scrc_out, type rw */
96 /* Register rw_ctrl, scope iop_scrc_out, type rw */
105 /* Register rw_init_crc, scope iop_scrc_out, type rw */
110 /* Register rw_crc, scope iop_scrc_out, type rw */
115 /* Register rw_data, scope iop_scrc_out, type rw */
H A Diop_dmc_out_defs.h87 /* Register rw_cfg, scope iop_dmc_out, type rw */
97 /* Register rw_ctrl, scope iop_dmc_out, type rw */
113 /* Register rw_stream_cmd, scope iop_dmc_out, type rw */
181 /* Register rw_data_descr, scope iop_dmc_out, type rw */
189 /* Register rw_ctxt_descr, scope iop_dmc_out, type rw */
197 /* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */
202 /* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */
207 /* Register rw_group_descr, scope iop_dmc_out, type rw */
215 /* Register rw_intr_mask, scope iop_dmc_out, type rw */
231 /* Register rw_ack_intr, scope iop_dmc_out, type rw */
H A Diop_sw_mpu_defs.h87 /* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
95 /* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
107 /* Register rw_mc_data, scope iop_sw_mpu, type rw */
114 /* Register rw_mc_addr, scope iop_sw_mpu, type rw */
141 /* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */
151 /* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */
161 /* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */
172 /* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */
187 /* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */
197 /* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */
207 /* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */
218 /* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */
233 /* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
240 /* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
247 /* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
254 /* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
265 /* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
340 /* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
378 /* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
470 /* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
508 /* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
600 /* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
638 /* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
730 /* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
768 /* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
H A Diop_fifo_in_defs.h87 /* Register rw_cfg, scope iop_fifo_in, type rw */
99 /* Register rw_ctrl, scope iop_fifo_in, type rw */
172 /* Register rw_set_last, scope iop_fifo_in, type rw */
177 /* Register rw_strb_dif_in, scope iop_fifo_in, type rw */
185 /* Register rw_intr_mask, scope iop_fifo_in, type rw */
197 /* Register rw_ack_intr, scope iop_fifo_in, type rw */
H A Diop_mpu_defs.h88 /* Register rw_r, scope iop_mpu, type rw */
93 /* Register rw_ctrl, scope iop_mpu, type rw */
117 /* Register rw_instr, scope iop_mpu, type rw */
122 /* Register rw_immediate, scope iop_mpu, type rw */
161 /* Register rw_thread, scope iop_mpu, type rw */
170 /* Register rw_intr, scope iop_mpu, type rw */
H A Diop_fifo_in_extra_defs.h87 /* Register rw_wr_data, scope iop_fifo_in_extra, type rw */
102 /* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */
110 /* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */
122 /* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */
H A Diop_trigger_grp_defs.h88 /* Register rw_cfg, scope iop_trigger_grp, type rw */
100 /* Register rw_cmd, scope iop_trigger_grp, type rw */
109 /* Register rw_intr_mask, scope iop_trigger_grp, type rw */
120 /* Register rw_ack_intr, scope iop_trigger_grp, type rw */
H A Diop_sw_cpu_defs.h87 /* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
99 /* Register rw_mc_data, scope iop_sw_cpu, type rw */
106 /* Register rw_mc_addr, scope iop_sw_cpu, type rw */
133 /* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */
143 /* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */
153 /* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */
164 /* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */
179 /* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */
189 /* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */
199 /* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */
210 /* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */
225 /* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
232 /* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
239 /* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
246 /* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
257 /* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
295 /* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
407 /* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
445 /* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
557 /* Register rw_intr2_mask, scope iop_sw_cpu, type rw */
595 /* Register rw_ack_intr2, scope iop_sw_cpu, type rw */
692 /* Register rw_intr3_mask, scope iop_sw_cpu, type rw */
730 /* Register rw_ack_intr3, scope iop_sw_cpu, type rw */
H A Diop_sap_out_defs.h87 /* Register rw_gen_gated, scope iop_sap_out, type rw */
106 /* Register rw_bus0, scope iop_sap_out, type rw */
125 /* Register rw_bus1, scope iop_sap_out, type rw */
144 /* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */
161 /* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */
178 /* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */
195 /* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */
213 /* Register rw_gio, scope iop_sap_out, type rw */
H A Diop_fifo_out_extra_defs.h106 /* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */
111 /* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */
123 /* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */
H A Diop_sap_in_defs.h87 /* Register rw_bus0_sync, scope iop_sap_in, type rw */
109 /* Register rw_bus1_sync, scope iop_sap_in, type rw */
132 /* Register rw_gio, scope iop_sap_in, type rw */
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/iop/asm/
H A Diop_crc_par_defs_asm.h56 /* Register rw_cfg, scope iop_crc_par, type rw */
75 /* Register rw_init_crc, scope iop_crc_par, type rw */
78 /* Register rw_correct_crc, scope iop_crc_par, type rw */
81 /* Register rw_ctrl, scope iop_crc_par, type rw */
87 /* Register rw_set_last, scope iop_crc_par, type rw */
93 /* Register rw_wr1byte, scope iop_crc_par, type rw */
98 /* Register rw_wr2byte, scope iop_crc_par, type rw */
103 /* Register rw_wr3byte, scope iop_crc_par, type rw */
108 /* Register rw_wr4byte, scope iop_crc_par, type rw */
113 /* Register rw_wr1byte_last, scope iop_crc_par, type rw */
118 /* Register rw_wr2byte_last, scope iop_crc_par, type rw */
123 /* Register rw_wr3byte_last, scope iop_crc_par, type rw */
128 /* Register rw_wr4byte_last, scope iop_crc_par, type rw */
148 /* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */
H A Diop_sw_spu_defs_asm.h56 /* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
72 /* Register rw_mc_data, scope iop_sw_spu, type rw */
77 /* Register rw_mc_addr, scope iop_sw_spu, type rw */
113 /* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */
124 /* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */
135 /* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */
150 /* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */
168 /* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */
179 /* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */
190 /* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */
205 /* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */
223 /* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
228 /* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
233 /* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
238 /* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
246 /* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */
253 /* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */
260 /* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */
267 /* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */
274 /* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */
281 /* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */
288 /* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */
295 /* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */
302 /* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
307 /* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
312 /* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
317 /* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
322 /* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
327 /* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
332 /* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
337 /* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
342 /* Register rw_cpu_intr, scope iop_sw_spu, type rw */
519 /* Register rw_mpu_intr, scope iop_sw_spu, type rw */
H A Diop_scrc_out_defs_asm.h56 /* Register rw_cfg, scope iop_scrc_out, type rw */
64 /* Register rw_ctrl, scope iop_scrc_out, type rw */
73 /* Register rw_init_crc, scope iop_scrc_out, type rw */
76 /* Register rw_crc, scope iop_scrc_out, type rw */
79 /* Register rw_data, scope iop_scrc_out, type rw */
H A Diop_sw_cfg_defs_asm.h56 /* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */
61 /* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */
66 /* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */
71 /* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */
76 /* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */
81 /* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */
86 /* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */
91 /* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */
96 /* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */
101 /* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */
106 /* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */
111 /* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */
116 /* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */
121 /* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */
126 /* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
131 /* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
136 /* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */
141 /* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */
146 /* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */
151 /* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */
156 /* Register rw_spu0_owner, scope iop_sw_cfg, type rw */
161 /* Register rw_spu1_owner, scope iop_sw_cfg, type rw */
166 /* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
171 /* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
176 /* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */
181 /* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */
186 /* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
191 /* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
196 /* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
201 /* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
206 /* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
211 /* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
216 /* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
221 /* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
226 /* Register rw_bus0_mask, scope iop_sw_cfg, type rw */
237 /* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */
252 /* Register rw_bus1_mask, scope iop_sw_cfg, type rw */
263 /* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */
278 /* Register rw_gio_mask, scope iop_sw_cfg, type rw */
283 /* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
288 /* Register rw_pinmapping, scope iop_sw_cfg, type rw */
323 /* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
342 /* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
361 /* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
380 /* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
399 /* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
418 /* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
437 /* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
456 /* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
475 /* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
494 /* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */
501 /* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */
508 /* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
537 /* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
566 /* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */
595 /* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */
624 /* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
675 /* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */
694 /* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */
713 /* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
H A Diop_fifo_out_defs_asm.h56 /* Register rw_cfg, scope iop_fifo_out, type rw */
76 /* Register rw_ctrl, scope iop_fifo_out, type rw */
101 /* Register rw_wr1byte, scope iop_fifo_out, type rw */
106 /* Register rw_wr2byte, scope iop_fifo_out, type rw */
111 /* Register rw_wr3byte, scope iop_fifo_out, type rw */
116 /* Register rw_wr4byte, scope iop_fifo_out, type rw */
121 /* Register rw_wr1byte_last, scope iop_fifo_out, type rw */
126 /* Register rw_wr2byte_last, scope iop_fifo_out, type rw */
131 /* Register rw_wr3byte_last, scope iop_fifo_out, type rw */
136 /* Register rw_wr4byte_last, scope iop_fifo_out, type rw */
141 /* Register rw_set_last, scope iop_fifo_out, type rw */
150 /* Register rw_strb_dif_out, scope iop_fifo_out, type rw */
153 /* Register rw_intr_mask, scope iop_fifo_out, type rw */
171 /* Register rw_ack_intr, scope iop_fifo_out, type rw */
H A Diop_scrc_in_defs_asm.h56 /* Register rw_cfg, scope iop_scrc_in, type rw */
61 /* Register rw_ctrl, scope iop_scrc_in, type rw */
73 /* Register rw_init_crc, scope iop_scrc_in, type rw */
82 /* Register rw_crc, scope iop_scrc_in, type rw */
85 /* Register rw_correct_crc, scope iop_scrc_in, type rw */
88 /* Register rw_wr1bit, scope iop_scrc_in, type rw */
H A Diop_dmc_in_defs_asm.h56 /* Register rw_cfg, scope iop_dmc_in, type rw */
64 /* Register rw_ctrl, scope iop_dmc_in, type rw */
82 /* Register rw_stream_cmd, scope iop_dmc_in, type rw */
89 /* Register rw_stream_wr_data, scope iop_dmc_in, type rw */
92 /* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */
95 /* Register rw_stream_ctrl, scope iop_dmc_in, type rw */
168 /* Register rw_data_descr, scope iop_dmc_in, type rw */
173 /* Register rw_ctxt_descr, scope iop_dmc_in, type rw */
178 /* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */
181 /* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */
184 /* Register rw_group_descr, scope iop_dmc_in, type rw */
189 /* Register rw_intr_mask, scope iop_dmc_in, type rw */
210 /* Register rw_ack_intr, scope iop_dmc_in, type rw */
H A Diop_timer_grp_defs_asm.h56 /* Register rw_cfg, scope iop_timer_grp, type rw */
68 /* Register rw_half_period, scope iop_timer_grp, type rw */
78 /* Register rw_half_period_len, scope iop_timer_grp, type rw */
82 /* Register rw_tmr_cfg, scope iop_timer_grp, type rw */
113 /* Register rw_tmr_len, scope iop_timer_grp, type rw */
118 /* Register rw_cmd, scope iop_timer_grp, type rw */
144 /* Register rw_intr_mask, scope iop_timer_grp, type rw */
159 /* Register rw_ack_intr, scope iop_timer_grp, type rw */
H A Diop_dmc_out_defs_asm.h56 /* Register rw_cfg, scope iop_dmc_out, type rw */
66 /* Register rw_ctrl, scope iop_dmc_out, type rw */
81 /* Register rw_stream_cmd, scope iop_dmc_out, type rw */
161 /* Register rw_data_descr, scope iop_dmc_out, type rw */
166 /* Register rw_ctxt_descr, scope iop_dmc_out, type rw */
171 /* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */
174 /* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */
177 /* Register rw_group_descr, scope iop_dmc_out, type rw */
182 /* Register rw_intr_mask, scope iop_dmc_out, type rw */
212 /* Register rw_ack_intr, scope iop_dmc_out, type rw */
H A Diop_spu_defs_asm.h57 /* Register rw_r, scope iop_spu, type rw */
60 /* Register rw_seq_pc, scope iop_spu, type rw */
65 /* Register rw_fsm_pc, scope iop_spu, type rw */
70 /* Register rw_ctrl, scope iop_spu, type rw */
79 /* Register rw_fsm_inputs3_0, scope iop_spu, type rw */
98 /* Register rw_fsm_inputs7_4, scope iop_spu, type rw */
117 /* Register rw_gio_out, scope iop_spu, type rw */
120 /* Register rw_bus0_out, scope iop_spu, type rw */
123 /* Register rw_bus1_out, scope iop_spu, type rw */
135 /* Register rw_gio_out_set, scope iop_spu, type rw */
138 /* Register rw_gio_out_clr, scope iop_spu, type rw */
381 /* Register rw_reg_access, scope iop_spu, type rw */
389 /* Register rw_event_cfg, scope iop_spu, type rw */
409 /* Register rw_event_mask, scope iop_spu, type rw */
413 /* Register rw_event_val, scope iop_spu, type rw */
416 /* Register rw_event_ret, scope iop_spu, type rw */
487 /* Register rw_brp, scope iop_spu, type rw */
H A Diop_fifo_in_defs_asm.h56 /* Register rw_cfg, scope iop_fifo_in, type rw */
70 /* Register rw_ctrl, scope iop_fifo_in, type rw */
132 /* Register rw_set_last, scope iop_fifo_in, type rw */
135 /* Register rw_strb_dif_in, scope iop_fifo_in, type rw */
140 /* Register rw_intr_mask, scope iop_fifo_in, type rw */
158 /* Register rw_ack_intr, scope iop_fifo_in, type rw */
H A Diop_mpu_defs_asm.h57 /* Register rw_r, scope iop_mpu, type rw */
60 /* Register rw_ctrl, scope iop_mpu, type rw */
82 /* Register rw_instr, scope iop_mpu, type rw */
85 /* Register rw_immediate, scope iop_mpu, type rw */
156 /* Register rw_thread, scope iop_mpu, type rw */
162 /* Register rw_intr, scope iop_mpu, type rw */
H A Diop_fifo_in_extra_defs_asm.h56 /* Register rw_wr_data, scope iop_fifo_in_extra, type rw */
72 /* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */
77 /* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */
95 /* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */
H A Diop_trigger_grp_defs_asm.h57 /* Register rw_cfg, scope iop_trigger_grp, type rw */
73 /* Register rw_cmd, scope iop_trigger_grp, type rw */
80 /* Register rw_intr_mask, scope iop_trigger_grp, type rw */
95 /* Register rw_ack_intr, scope iop_trigger_grp, type rw */
H A Diop_sap_out_defs_asm.h56 /* Register rw_gen_gated, scope iop_sap_out, type rw */
83 /* Register rw_bus0, scope iop_sap_out, type rw */
114 /* Register rw_bus1, scope iop_sap_out, type rw */
145 /* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */
170 /* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */
195 /* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */
220 /* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */
246 /* Register rw_gio, scope iop_sap_out, type rw */
H A Diop_fifo_out_extra_defs_asm.h78 /* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */
81 /* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */
99 /* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */
H A Diop_sw_mpu_defs_asm.h56 /* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
61 /* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
77 /* Register rw_mc_data, scope iop_sw_mpu, type rw */
82 /* Register rw_mc_addr, scope iop_sw_mpu, type rw */
118 /* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */
129 /* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */
140 /* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */
155 /* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */
173 /* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */
184 /* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */
195 /* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */
210 /* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */
228 /* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
233 /* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
238 /* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
243 /* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
251 /* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
449 /* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
548 /* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
773 /* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
872 /* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
1097 /* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
1196 /* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
1421 /* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
1520 /* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
H A Diop_sw_cpu_defs_asm.h56 /* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
72 /* Register rw_mc_data, scope iop_sw_cpu, type rw */
77 /* Register rw_mc_addr, scope iop_sw_cpu, type rw */
113 /* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */
124 /* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */
135 /* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */
150 /* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */
168 /* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */
179 /* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */
190 /* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */
205 /* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */
223 /* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
228 /* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
233 /* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
238 /* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
246 /* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
345 /* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
642 /* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
741 /* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
1038 /* Register rw_intr2_mask, scope iop_sw_cpu, type rw */
1137 /* Register rw_ack_intr2, scope iop_sw_cpu, type rw */
1386 /* Register rw_intr3_mask, scope iop_sw_cpu, type rw */
1485 /* Register rw_ack_intr3, scope iop_sw_cpu, type rw */
H A Diop_sap_in_defs_asm.h56 /* Register rw_bus0_sync, scope iop_sap_in, type rw */
95 /* Register rw_bus1_sync, scope iop_sap_in, type rw */
135 /* Register rw_gio, scope iop_sap_in, type rw */
/linux-4.1.27/arch/cris/include/arch-v32/mach-fs/mach/hwregs/
H A Dbif_dma_defs.h87 /* Register rw_ch0_ctrl, scope bif_dma, type rw */
106 /* Register rw_ch0_addr, scope bif_dma, type rw */
113 /* Register rw_ch0_start, scope bif_dma, type rw */
121 /* Register rw_ch0_cnt, scope bif_dma, type rw */
137 /* Register rw_ch1_ctrl, scope bif_dma, type rw */
155 /* Register rw_ch1_addr, scope bif_dma, type rw */
162 /* Register rw_ch1_start, scope bif_dma, type rw */
170 /* Register rw_ch1_cnt, scope bif_dma, type rw */
186 /* Register rw_ch2_ctrl, scope bif_dma, type rw */
205 /* Register rw_ch2_addr, scope bif_dma, type rw */
212 /* Register rw_ch2_start, scope bif_dma, type rw */
220 /* Register rw_ch2_cnt, scope bif_dma, type rw */
236 /* Register rw_ch3_ctrl, scope bif_dma, type rw */
254 /* Register rw_ch3_addr, scope bif_dma, type rw */
261 /* Register rw_ch3_start, scope bif_dma, type rw */
269 /* Register rw_ch3_cnt, scope bif_dma, type rw */
285 /* Register rw_intr_mask, scope bif_dma, type rw */
296 /* Register rw_ack_intr, scope bif_dma, type rw */
327 /* Register rw_pin0_cfg, scope bif_dma, type rw */
338 /* Register rw_pin1_cfg, scope bif_dma, type rw */
349 /* Register rw_pin2_cfg, scope bif_dma, type rw */
360 /* Register rw_pin3_cfg, scope bif_dma, type rw */
371 /* Register rw_pin4_cfg, scope bif_dma, type rw */
382 /* Register rw_pin5_cfg, scope bif_dma, type rw */
393 /* Register rw_pin6_cfg, scope bif_dma, type rw */
404 /* Register rw_pin7_cfg, scope bif_dma, type rw */
H A Dgio_defs.h87 /* Register rw_pa_dout, scope gio, type rw */
102 /* Register rw_pa_oe, scope gio, type rw */
110 /* Register rw_intr_cfg, scope gio, type rw */
125 /* Register rw_intr_mask, scope gio, type rw */
140 /* Register rw_ack_intr, scope gio, type rw */
183 /* Register rw_pb_dout, scope gio, type rw */
198 /* Register rw_pb_oe, scope gio, type rw */
206 /* Register rw_pc_dout, scope gio, type rw */
221 /* Register rw_pc_oe, scope gio, type rw */
229 /* Register rw_pd_dout, scope gio, type rw */
244 /* Register rw_pd_oe, scope gio, type rw */
252 /* Register rw_pe_dout, scope gio, type rw */
267 /* Register rw_pe_oe, scope gio, type rw */
H A Dbif_slave_defs.h87 /* Register rw_slave_cfg, scope bif_slave, type rw */
109 /* Register rw_ch0_cfg, scope bif_slave, type rw */
120 /* Register rw_ch1_cfg, scope bif_slave, type rw */
131 /* Register rw_ch2_cfg, scope bif_slave, type rw */
142 /* Register rw_ch3_cfg, scope bif_slave, type rw */
153 /* Register rw_arb_cfg, scope bif_slave, type rw */
178 /* Register rw_intr_mask, scope bif_slave, type rw */
187 /* Register rw_ack_intr, scope bif_slave, type rw */
H A Dtimer_defs.h87 /* Register rw_tmr0_div, scope timer, type rw */
96 /* Register rw_tmr0_ctrl, scope timer, type rw */
105 /* Register rw_tmr1_div, scope timer, type rw */
114 /* Register rw_tmr1_ctrl, scope timer, type rw */
137 /* Register rw_cnt_cfg, scope timer, type rw */
145 /* Register rw_trig, scope timer, type rw */
150 /* Register rw_trig_cfg, scope timer, type rw */
162 /* Register rw_out, scope timer, type rw */
170 /* Register rw_wd_ctrl, scope timer, type rw */
188 /* Register rw_intr_mask, scope timer, type rw */
199 /* Register rw_ack_intr, scope timer, type rw */
230 /* Register rw_test, scope timer, type rw */
H A Dpinmux_defs.h87 /* Register rw_pa, scope pinmux, type rw */
110 /* Register rw_hwprot, scope pinmux, type rw */
131 /* Register rw_pb_gio, scope pinmux, type rw */
156 /* Register rw_pb_iop, scope pinmux, type rw */
181 /* Register rw_pc_gio, scope pinmux, type rw */
206 /* Register rw_pc_iop, scope pinmux, type rw */
231 /* Register rw_pd_gio, scope pinmux, type rw */
256 /* Register rw_pd_iop, scope pinmux, type rw */
281 /* Register rw_pe_gio, scope pinmux, type rw */
306 /* Register rw_pe_iop, scope pinmux, type rw */
331 /* Register rw_usb_phy, scope pinmux, type rw */
H A Dmarb_defs.h88 /* Register rw_int_slots, scope marb, type rw */
97 /* Register rw_ext_slots, scope marb, type rw */
106 /* Register rw_regs_slots, scope marb, type rw */
114 /* Register rw_intr_mask, scope marb, type rw */
125 /* Register rw_ack_intr, scope marb, type rw */
156 /* Register rw_stop_mask, scope marb, type rw */
197 /* Register rw_no_snoop, scope marb, type rw */
218 /* Register rw_no_snoop_rq, scope marb, type rw */
346 /* Register rw_first_addr, scope marb_bp, type rw */
351 /* Register rw_last_addr, scope marb_bp, type rw */
356 /* Register rw_op, scope marb_bp, type rw */
371 /* Register rw_clients, scope marb_bp, type rw */
392 /* Register rw_options, scope marb_bp, type rw */
462 /* Register rw_ack, scope marb_bp, type rw */
H A Dmarb_bp_defs.h76 /* Register rw_first_addr, scope marb_bp, type rw */
81 /* Register rw_last_addr, scope marb_bp, type rw */
86 /* Register rw_op, scope marb_bp, type rw */
101 /* Register rw_clients, scope marb_bp, type rw */
122 /* Register rw_options, scope marb_bp, type rw */
192 /* Register rw_ack, scope marb_bp, type rw */
H A Dbif_core_defs.h87 /* Register rw_grp1_cfg, scope bif_core, type rw */
104 /* Register rw_grp2_cfg, scope bif_core, type rw */
121 /* Register rw_grp3_cfg, scope bif_core, type rw */
142 /* Register rw_grp4_cfg, scope bif_core, type rw */
162 /* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
177 /* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
191 /* Register rw_sdram_timing, scope bif_core, type rw */
208 /* Register rw_sdram_cmd, scope bif_core, type rw */
H A Dconfig_defs.h98 /* Register rw_clk_ctrl, scope config, type rw */
115 /* Register rw_pad_ctrl, scope config, type rw */
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/
H A Diop_sw_spu_defs_asm.h56 /* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
69 /* Register rw_mc_data, scope iop_sw_spu, type rw */
74 /* Register rw_mc_addr, scope iop_sw_spu, type rw */
104 /* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */
115 /* Register rw_bus_set_mask, scope iop_sw_spu, type rw */
126 /* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */
141 /* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */
159 /* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
164 /* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
169 /* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
174 /* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
182 /* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */
189 /* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */
196 /* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */
203 /* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */
210 /* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
215 /* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
220 /* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
225 /* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
230 /* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
235 /* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
240 /* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
245 /* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
250 /* Register rw_cpu_intr, scope iop_sw_spu, type rw */
403 /* Register rw_mpu_intr, scope iop_sw_spu, type rw */
H A Diop_sw_cfg_defs_asm.h53 /* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */
58 /* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */
63 /* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */
68 /* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */
73 /* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */
78 /* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */
83 /* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */
88 /* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
93 /* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
98 /* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */
103 /* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */
108 /* Register rw_spu_owner, scope iop_sw_cfg, type rw */
114 /* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
119 /* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
124 /* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
129 /* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
134 /* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
139 /* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
144 /* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
149 /* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
154 /* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
159 /* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
164 /* Register rw_bus_mask, scope iop_sw_cfg, type rw */
175 /* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */
190 /* Register rw_gio_mask, scope iop_sw_cfg, type rw */
195 /* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
200 /* Register rw_pinmapping, scope iop_sw_cfg, type rw */
227 /* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
238 /* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
261 /* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
284 /* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
307 /* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
330 /* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
353 /* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
376 /* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
399 /* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
422 /* Register rw_spu_cfg, scope iop_sw_cfg, type rw */
431 /* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
452 /* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
473 /* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
524 /* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */
537 /* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
H A Diop_sw_mpu_defs_asm.h53 /* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
64 /* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
77 /* Register rw_mc_data, scope iop_sw_mpu, type rw */
82 /* Register rw_mc_addr, scope iop_sw_mpu, type rw */
112 /* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */
123 /* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */
134 /* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */
149 /* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */
167 /* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
172 /* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
177 /* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
182 /* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
190 /* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
388 /* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
439 /* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
556 /* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
607 /* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
724 /* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
775 /* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
892 /* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
943 /* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
H A Diop_sap_in_defs_asm.h54 /* Register rw_bus_byte, scope iop_sap_in, type rw */
66 /* Register rw_gio, scope iop_sap_in, type rw */
H A Diop_sw_cpu_defs_asm.h62 /* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
75 /* Register rw_mc_data, scope iop_sw_cpu, type rw */
80 /* Register rw_mc_addr, scope iop_sw_cpu, type rw */
110 /* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */
121 /* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */
132 /* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */
147 /* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */
165 /* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
170 /* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
175 /* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
180 /* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
188 /* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
287 /* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
584 /* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
683 /* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
H A Diop_sap_out_defs_asm.h53 /* Register rw_gen_gated, scope iop_sap_out, type rw */
68 /* Register rw_bus, scope iop_sap_out, type rw */
123 /* Register rw_bus_lo_oe, scope iop_sap_out, type rw */
160 /* Register rw_bus_hi_oe, scope iop_sap_out, type rw */
198 /* Register rw_gio, scope iop_sap_out, type rw */
/linux-4.1.27/arch/m32r/include/asm/
H A Dspinlock.h136 * Changed to use the same technique as rw semaphores. See
152 static inline void arch_read_lock(arch_rwlock_t *rw) arch_read_lock() argument
157 * rw->lock : >0 : unlock arch_read_lock()
161 * rw->lock -= 1; <-- need atomic operation arch_read_lock()
162 * if (rw->lock >= 0) break; arch_read_lock()
163 * rw->lock += 1; <-- need atomic operation arch_read_lock()
164 * for ( ; rw->lock <= 0 ; ); arch_read_lock()
195 : "r" (&rw->lock) arch_read_lock()
203 static inline void arch_write_lock(arch_rwlock_t *rw) arch_write_lock() argument
208 * rw->lock : =RW_LOCK_BIAS_STR : unlock arch_write_lock()
212 * rw->lock -= RW_LOCK_BIAS_STR; <-- need atomic operation arch_write_lock()
213 * if (rw->lock == 0) break; arch_write_lock()
214 * rw->lock += RW_LOCK_BIAS_STR; <-- need atomic operation arch_write_lock()
215 * for ( ; rw->lock != RW_LOCK_BIAS_STR ; ) ; arch_write_lock()
248 : "r" (&rw->lock) arch_write_lock()
256 static inline void arch_read_unlock(arch_rwlock_t *rw) arch_read_unlock() argument
270 : "r" (&rw->lock) arch_read_unlock()
278 static inline void arch_write_unlock(arch_rwlock_t *rw) arch_write_unlock() argument
294 : "r" (&rw->lock) arch_write_unlock()
/linux-4.1.27/arch/arm64/include/asm/
H A Dspinlock.h122 static inline void arch_write_lock(arch_rwlock_t *rw) arch_write_lock() argument
133 : "=&r" (tmp), "+Q" (rw->lock) arch_write_lock()
138 static inline int arch_write_trylock(arch_rwlock_t *rw) arch_write_trylock() argument
147 : "=&r" (tmp), "+Q" (rw->lock) arch_write_trylock()
154 static inline void arch_write_unlock(arch_rwlock_t *rw) arch_write_unlock() argument
158 : "=Q" (rw->lock) : "r" (0) : "memory"); arch_write_unlock()
176 static inline void arch_read_lock(arch_rwlock_t *rw) arch_read_lock() argument
188 : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock) arch_read_lock()
193 static inline void arch_read_unlock(arch_rwlock_t *rw) arch_read_unlock() argument
202 : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock) arch_read_unlock()
207 static inline int arch_read_trylock(arch_rwlock_t *rw) arch_read_trylock() argument
217 : "=&r" (tmp), "+r" (tmp2), "+Q" (rw->lock) arch_read_trylock()
/linux-4.1.27/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/
H A Dtimer_defs_asm.h56 /* Register rw_tmr0_div, scope timer, type rw */
62 /* Register rw_tmr0_ctrl, scope timer, type rw */
69 /* Register rw_tmr1_div, scope timer, type rw */
75 /* Register rw_tmr1_ctrl, scope timer, type rw */
96 /* Register rw_cnt_cfg, scope timer, type rw */
101 /* Register rw_trig, scope timer, type rw */
104 /* Register rw_trig_cfg, scope timer, type rw */
112 /* Register rw_out, scope timer, type rw */
117 /* Register rw_wd_ctrl, scope timer, type rw */
135 /* Register rw_intr_mask, scope timer, type rw */
150 /* Register rw_ack_intr, scope timer, type rw */
195 /* Register rw_test, scope timer, type rw */
H A Dgio_defs_asm.h56 /* Register rw_pa_dout, scope gio, type rw */
66 /* Register rw_pa_oe, scope gio, type rw */
71 /* Register rw_intr_cfg, scope gio, type rw */
90 /* Register rw_intr_mask, scope gio, type rw */
117 /* Register rw_ack_intr, scope gio, type rw */
198 /* Register rw_pb_dout, scope gio, type rw */
208 /* Register rw_pb_oe, scope gio, type rw */
213 /* Register rw_pc_dout, scope gio, type rw */
223 /* Register rw_pc_oe, scope gio, type rw */
228 /* Register rw_pd_dout, scope gio, type rw */
238 /* Register rw_pd_oe, scope gio, type rw */
243 /* Register rw_pe_dout, scope gio, type rw */
253 /* Register rw_pe_oe, scope gio, type rw */
H A Dbif_core_defs_asm.h56 /* Register rw_grp1_cfg, scope bif_core, type rw */
83 /* Register rw_grp2_cfg, scope bif_core, type rw */
110 /* Register rw_grp3_cfg, scope bif_core, type rw */
145 /* Register rw_grp4_cfg, scope bif_core, type rw */
178 /* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
201 /* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
222 /* Register rw_sdram_timing, scope bif_core, type rw */
249 /* Register rw_sdram_cmd, scope bif_core, type rw */
H A Dpinmux_defs_asm.h56 /* Register rw_pa, scope pinmux, type rw */
107 /* Register rw_hwprot, scope pinmux, type rw */
152 /* Register rw_pb_gio, scope pinmux, type rw */
209 /* Register rw_pb_iop, scope pinmux, type rw */
266 /* Register rw_pc_gio, scope pinmux, type rw */
323 /* Register rw_pc_iop, scope pinmux, type rw */
380 /* Register rw_pd_gio, scope pinmux, type rw */
437 /* Register rw_pd_iop, scope pinmux, type rw */
494 /* Register rw_pe_gio, scope pinmux, type rw */
551 /* Register rw_pe_iop, scope pinmux, type rw */
608 /* Register rw_usb_phy, scope pinmux, type rw */
H A Dconfig_defs_asm.h73 /* Register rw_clk_ctrl, scope config, type rw */
106 /* Register rw_pad_ctrl, scope config, type rw */
/linux-4.1.27/arch/arm/include/asm/hardware/
H A Darm_timer.h18 #define TIMER_LOAD 0x00 /* ACVR rw */
20 #define TIMER_CTRL 0x08 /* ACVR rw */
33 #define TIMER_BGLOAD 0x18 /* CVR rw */
/linux-4.1.27/block/
H A Dblk-throttle.c412 int rw; throtl_pd_init() local
434 for (rw = READ; rw <= WRITE; rw++) { throtl_pd_init()
435 throtl_qnode_init(&tg->qnode_on_self[rw], tg); throtl_pd_init()
436 throtl_qnode_init(&tg->qnode_on_parent[rw], tg); throtl_pd_init()
466 int rw; tg_update_has_rules() local
468 for (rw = READ; rw <= WRITE; rw++) tg_update_has_rules()
469 tg->has_rules[rw] = (parent_tg && parent_tg->has_rules[rw]) || tg_update_has_rules()
470 (tg->bps[rw] != -1 || tg->iops[rw] != -1); tg_update_has_rules()
694 bool rw, unsigned long start) throtl_start_new_slice_with_credit()
696 tg->bytes_disp[rw] = 0; throtl_start_new_slice_with_credit()
697 tg->io_disp[rw] = 0; throtl_start_new_slice_with_credit()
705 if (time_after_eq(start, tg->slice_start[rw])) throtl_start_new_slice_with_credit()
706 tg->slice_start[rw] = start; throtl_start_new_slice_with_credit()
708 tg->slice_end[rw] = jiffies + throtl_slice; throtl_start_new_slice_with_credit()
711 rw == READ ? 'R' : 'W', tg->slice_start[rw], throtl_start_new_slice_with_credit()
712 tg->slice_end[rw], jiffies); throtl_start_new_slice_with_credit()
715 static inline void throtl_start_new_slice(struct throtl_grp *tg, bool rw) throtl_start_new_slice() argument
717 tg->bytes_disp[rw] = 0; throtl_start_new_slice()
718 tg->io_disp[rw] = 0; throtl_start_new_slice()
719 tg->slice_start[rw] = jiffies; throtl_start_new_slice()
720 tg->slice_end[rw] = jiffies + throtl_slice; throtl_start_new_slice()
723 rw == READ ? 'R' : 'W', tg->slice_start[rw], throtl_start_new_slice()
724 tg->slice_end[rw], jiffies); throtl_start_new_slice()
727 static inline void throtl_set_slice_end(struct throtl_grp *tg, bool rw, throtl_set_slice_end() argument
730 tg->slice_end[rw] = roundup(jiffy_end, throtl_slice); throtl_set_slice_end()
733 static inline void throtl_extend_slice(struct throtl_grp *tg, bool rw, throtl_extend_slice() argument
736 tg->slice_end[rw] = roundup(jiffy_end, throtl_slice); throtl_extend_slice()
739 rw == READ ? 'R' : 'W', tg->slice_start[rw], throtl_extend_slice()
740 tg->slice_end[rw], jiffies); throtl_extend_slice()
744 static bool throtl_slice_used(struct throtl_grp *tg, bool rw) throtl_slice_used() argument
746 if (time_in_range(jiffies, tg->slice_start[rw], tg->slice_end[rw])) throtl_slice_used()
753 static inline void throtl_trim_slice(struct throtl_grp *tg, bool rw) throtl_trim_slice() argument
758 BUG_ON(time_before(tg->slice_end[rw], tg->slice_start[rw])); throtl_trim_slice()
765 if (throtl_slice_used(tg, rw)) throtl_trim_slice()
776 throtl_set_slice_end(tg, rw, jiffies + throtl_slice); throtl_trim_slice()
778 time_elapsed = jiffies - tg->slice_start[rw]; throtl_trim_slice()
784 tmp = tg->bps[rw] * throtl_slice * nr_slices; throtl_trim_slice()
788 io_trim = (tg->iops[rw] * throtl_slice * nr_slices)/HZ; throtl_trim_slice()
793 if (tg->bytes_disp[rw] >= bytes_trim) throtl_trim_slice()
794 tg->bytes_disp[rw] -= bytes_trim; throtl_trim_slice()
796 tg->bytes_disp[rw] = 0; throtl_trim_slice()
798 if (tg->io_disp[rw] >= io_trim) throtl_trim_slice()
799 tg->io_disp[rw] -= io_trim; throtl_trim_slice()
801 tg->io_disp[rw] = 0; throtl_trim_slice()
803 tg->slice_start[rw] += nr_slices * throtl_slice; throtl_trim_slice()
807 rw == READ ? 'R' : 'W', nr_slices, bytes_trim, io_trim, throtl_trim_slice()
808 tg->slice_start[rw], tg->slice_end[rw], jiffies); throtl_trim_slice()
814 bool rw = bio_data_dir(bio); tg_with_in_iops_limit() local
819 jiffy_elapsed = jiffy_elapsed_rnd = jiffies - tg->slice_start[rw]; tg_with_in_iops_limit()
834 tmp = (u64)tg->iops[rw] * jiffy_elapsed_rnd; tg_with_in_iops_limit()
842 if (tg->io_disp[rw] + 1 <= io_allowed) { tg_with_in_iops_limit()
849 jiffy_wait = ((tg->io_disp[rw] + 1) * HZ)/tg->iops[rw] + 1; tg_with_in_iops_limit()
864 bool rw = bio_data_dir(bio); tg_with_in_bps_limit() local
868 jiffy_elapsed = jiffy_elapsed_rnd = jiffies - tg->slice_start[rw]; tg_with_in_bps_limit()
876 tmp = tg->bps[rw] * jiffy_elapsed_rnd; tg_with_in_bps_limit()
880 if (tg->bytes_disp[rw] + bio->bi_iter.bi_size <= bytes_allowed) { tg_with_in_bps_limit()
887 extra_bytes = tg->bytes_disp[rw] + bio->bi_iter.bi_size - bytes_allowed; tg_with_in_bps_limit()
888 jiffy_wait = div64_u64(extra_bytes * HZ, tg->bps[rw]); tg_with_in_bps_limit()
910 bool rw = bio_data_dir(bio); tg_may_dispatch() local
919 BUG_ON(tg->service_queue.nr_queued[rw] && tg_may_dispatch()
920 bio != throtl_peek_queued(&tg->service_queue.queued[rw])); tg_may_dispatch()
923 if (tg->bps[rw] == -1 && tg->iops[rw] == -1) { tg_may_dispatch()
934 if (throtl_slice_used(tg, rw)) tg_may_dispatch()
935 throtl_start_new_slice(tg, rw); tg_may_dispatch()
937 if (time_before(tg->slice_end[rw], jiffies + throtl_slice)) tg_may_dispatch()
938 throtl_extend_slice(tg, rw, jiffies + throtl_slice); tg_may_dispatch()
953 if (time_before(tg->slice_end[rw], jiffies + max_wait)) tg_may_dispatch()
954 throtl_extend_slice(tg, rw, jiffies + max_wait); tg_may_dispatch()
960 int rw) throtl_update_dispatch_stats()
979 blkg_rwstat_add(&stats_cpu->serviced, rw, 1); throtl_update_dispatch_stats()
980 blkg_rwstat_add(&stats_cpu->service_bytes, rw, bytes); throtl_update_dispatch_stats()
987 bool rw = bio_data_dir(bio); throtl_charge_bio() local
990 tg->bytes_disp[rw] += bio->bi_iter.bi_size; throtl_charge_bio()
991 tg->io_disp[rw]++; throtl_charge_bio()
1024 bool rw = bio_data_dir(bio); throtl_add_bio_tg() local
1027 qn = &tg->qnode_on_self[rw]; throtl_add_bio_tg()
1035 if (!sq->nr_queued[rw]) throtl_add_bio_tg()
1038 throtl_qnode_add_bio(bio, qn, &sq->queued[rw]); throtl_add_bio_tg()
1040 sq->nr_queued[rw]++; throtl_add_bio_tg()
1069 struct throtl_grp *parent_tg, bool rw) start_parent_slice_with_credit()
1071 if (throtl_slice_used(parent_tg, rw)) { start_parent_slice_with_credit()
1072 throtl_start_new_slice_with_credit(parent_tg, rw, start_parent_slice_with_credit()
1073 child_tg->slice_start[rw]); start_parent_slice_with_credit()
1078 static void tg_dispatch_one_bio(struct throtl_grp *tg, bool rw) tg_dispatch_one_bio() argument
1092 bio = throtl_pop_queued(&sq->queued[rw], &tg_to_put); tg_dispatch_one_bio()
1093 sq->nr_queued[rw]--; tg_dispatch_one_bio()
1105 throtl_add_bio_tg(bio, &tg->qnode_on_parent[rw], parent_tg); tg_dispatch_one_bio()
1106 start_parent_slice_with_credit(tg, parent_tg, rw); tg_dispatch_one_bio()
1108 throtl_qnode_add_bio(bio, &tg->qnode_on_parent[rw], tg_dispatch_one_bio()
1109 &parent_sq->queued[rw]); tg_dispatch_one_bio()
1110 BUG_ON(tg->td->nr_queued[rw] <= 0); tg_dispatch_one_bio()
1111 tg->td->nr_queued[rw]--; tg_dispatch_one_bio()
1114 throtl_trim_slice(tg, rw); tg_dispatch_one_bio()
1270 int rw; blk_throtl_dispatch_work_fn() local
1275 for (rw = READ; rw <= WRITE; rw++) blk_throtl_dispatch_work_fn()
1276 while ((bio = throtl_pop_queued(&td_sq->queued[rw], NULL))) blk_throtl_dispatch_work_fn()
1486 bool rw = bio_data_dir(bio); blk_throtl_bio() local
1503 if (!tg->has_rules[rw]) { blk_throtl_bio()
1523 if (sq->nr_queued[rw]) blk_throtl_bio()
1544 throtl_trim_slice(tg, rw); blk_throtl_bio()
1551 qn = &tg->qnode_on_parent[rw]; blk_throtl_bio()
1560 rw == READ ? 'R' : 'W', blk_throtl_bio()
1561 tg->bytes_disp[rw], bio->bi_iter.bi_size, tg->bps[rw], blk_throtl_bio()
1562 tg->io_disp[rw], tg->iops[rw], blk_throtl_bio()
1566 tg->td->nr_queued[rw]++; blk_throtl_bio()
1631 int rw; variable
1652 for (rw = READ; rw <= WRITE; rw++)
1653 while ((bio = throtl_pop_queued(&td->service_queue.queued[rw],
693 throtl_start_new_slice_with_credit(struct throtl_grp *tg, bool rw, unsigned long start) throtl_start_new_slice_with_credit() argument
959 throtl_update_dispatch_stats(struct blkcg_gq *blkg, u64 bytes, int rw) throtl_update_dispatch_stats() argument
1068 start_parent_slice_with_credit(struct throtl_grp *child_tg, struct throtl_grp *parent_tg, bool rw) start_parent_slice_with_credit() argument
H A Dbounce.c203 int rw = bio_data_dir(*bio_orig); __blk_queue_bounce() local
227 if (rw == WRITE) { bio_for_each_segment_all()
245 if (rw == READ)
249 if (rw == READ)
/linux-4.1.27/drivers/staging/lustre/lustre/llite/
H A DMakefile4 rw.o namei.o symlink.o llite_mmap.o \
H A Drw26.c188 static inline int ll_get_user_pages(int rw, unsigned long user_addr, ll_get_user_pages() argument
206 (rw == READ), *pages); ll_get_user_pages()
229 int rw, struct inode *inode, ll_direct_rw_pages()
277 src_page = (rw == WRITE) ? pages[i] : vmpage; ll_direct_rw_pages()
278 dst_page = (rw == WRITE) ? vmpage : pages[i]; ll_direct_rw_pages()
288 if (rw == WRITE) ll_direct_rw_pages()
291 if (rw == READ) { ll_direct_rw_pages()
320 rw == READ ? CRT_READ : CRT_WRITE, ll_direct_rw_pages()
334 int rw, struct inode *inode, ll_direct_IO_26_seg()
346 return ll_direct_rw_pages(env, io, rw, inode, &pvec); ll_direct_IO_26_seg()
228 ll_direct_rw_pages(const struct lu_env *env, struct cl_io *io, int rw, struct inode *inode, struct ll_dio_pages *pv) ll_direct_rw_pages() argument
333 ll_direct_IO_26_seg(const struct lu_env *env, struct cl_io *io, int rw, struct inode *inode, struct address_space *mapping, size_t size, loff_t file_offset, struct page **pages, int page_count) ll_direct_IO_26_seg() argument
H A Dlloop.c193 int rw; do_bio_lustrebacked() local
215 rw = head->bi_rw; do_bio_lustrebacked()
217 LASSERT(rw == bio->bi_rw); do_bio_lustrebacked()
233 (rw == WRITE) ? LPROC_LL_BRW_WRITE : LPROC_LL_BRW_READ,
261 bytes = ll_direct_rw_pages(env, io, rw, inode, pvec);
296 int rw; loop_get_bio() local
308 rw = first->bi_rw; loop_get_bio()
310 while (*bio && (*bio)->bi_rw == rw) { loop_get_bio()
340 int rw = bio_rw(old_bio); loop_make_request() local
356 if (rw == WRITE) { loop_make_request()
359 } else if (rw == READA) { loop_make_request()
360 rw = READ; loop_make_request()
361 } else if (rw != READ) { loop_make_request()
362 CERROR("lloop: unknown command (%x)\n", rw); loop_make_request()
/linux-4.1.27/arch/ia64/include/asm/
H A Dspinlock.h147 #define arch_read_can_lock(rw) (*(volatile int *)(rw) >= 0)
148 #define arch_write_can_lock(rw) (*(volatile int *)(rw) == 0)
180 #define arch_read_lock_flags(rw, flags) arch_read_lock(rw)
182 #define arch_read_lock(rw) \
184 arch_rwlock_t *__read_lock_ptr = (rw); \
195 #define arch_read_unlock(rw) \
197 arch_rwlock_t *__read_lock_ptr = (rw); \
228 #define arch_write_lock(rw) arch_write_lock_flags(rw, 0)
230 #define arch_write_trylock(rw) \
238 : "=r"(result) : "r"(rw) : "ar.ccv", "r29", "memory"); \
264 #define arch_write_trylock(rw) \
268 ia64_val = ia64_cmpxchg4_acq((__u32 *)(rw), ia64_set_val, 0); \
H A Dsyscall.h63 unsigned long *args, int rw); syscall_get_arguments()
/linux-4.1.27/kernel/power/
H A Dblock_io.c19 * @rw: READ or WRITE.
28 static int submit(int rw, struct block_device *bdev, sector_t sector, submit() argument
31 const int bio_rw = rw | REQ_SYNC; submit()
52 if (rw == READ) submit()
56 if (rw == READ) submit()
/linux-4.1.27/drivers/block/xen-blkback/
H A Dcommon.h114 struct blkif_x86_32_request_rw rw; member in union:blkif_x86_32_request::__anon3645
134 uint32_t _pad1; /* offsetof(blkif_reqest..,u.rw.id)==8 */
178 struct blkif_x86_64_request_rw rw; member in union:blkif_x86_64_request::__anon3646
406 dst->u.rw.nr_segments = src->u.rw.nr_segments; blkif_get_x86_32_req()
407 dst->u.rw.handle = src->u.rw.handle; blkif_get_x86_32_req()
408 dst->u.rw.id = src->u.rw.id; blkif_get_x86_32_req()
409 dst->u.rw.sector_number = src->u.rw.sector_number; blkif_get_x86_32_req()
411 if (n > dst->u.rw.nr_segments) blkif_get_x86_32_req()
412 n = dst->u.rw.nr_segments; blkif_get_x86_32_req()
414 dst->u.rw.seg[i] = src->u.rw.seg[i]; blkif_get_x86_32_req()
454 dst->u.rw.nr_segments = src->u.rw.nr_segments; blkif_get_x86_64_req()
455 dst->u.rw.handle = src->u.rw.handle; blkif_get_x86_64_req()
456 dst->u.rw.id = src->u.rw.id; blkif_get_x86_64_req()
457 dst->u.rw.sector_number = src->u.rw.sector_number; blkif_get_x86_64_req()
459 if (n > dst->u.rw.nr_segments) blkif_get_x86_64_req()
460 n = dst->u.rw.nr_segments; blkif_get_x86_64_req()
462 dst->u.rw.seg[i] = src->u.rw.seg[i]; blkif_get_x86_64_req()
/linux-4.1.27/drivers/scsi/
H A DNCR5380.h67 #define INITIATOR_COMMAND_REG 1 /* rw */
68 #define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */
73 #define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */
74 #define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */
75 #define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */
76 #define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */
77 #define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */
91 #define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */
92 #define MR_TARGET 0x40 /* rw target mode */
93 #define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */
94 #define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */
95 #define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */
96 #define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */
97 #define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */
98 #define MR_ARBITRATE 0x01 /* rw start arbitration */
108 #define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */
109 #define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */
110 #define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */
111 #define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */
161 #define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8 /* rw */
165 #define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */
166 #define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */
167 #define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */
168 #define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */
180 #define C400_BLOCK_COUNTER_REG NCR53C400_register_offset-7 /* rw */
186 #define C400_HOST_BUFFER NCR53C400_register_offset-4 /* rw */
H A Ddtc.c74 #define DTC_CONTROL_REG 0x100 /* rw */
76 #define CSR_DIR_READ 0x40 /* rw direction, 1 = read 0 = write */
80 #define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */
81 #define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */
82 #define CSR_5380_INTR 0x10 /* rw Enable 5380 interrupts */
83 #define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */
90 #define DTC_BLK_CNT 0x101 /* rw
103 #define DTC_DATA_BUF 0x3900 /* rw 128 bytes long */
H A Desp_scsi.h10 #define ESP_TCLOW 0x00UL /* rw Low bits transfer count 0x00 */
11 #define ESP_TCMED 0x01UL /* rw Mid bits transfer count 0x04 */
12 #define ESP_FDATA 0x02UL /* rw FIFO data bits 0x08 */
13 #define ESP_CMD 0x03UL /* rw SCSI command bits 0x0c */
22 #define ESP_CFG1 0x08UL /* rw First cfg register 0x20 */
26 #define ESP_CFG2 0x0bUL /* rw Second cfg register 0x2c */
27 #define ESP_CFG3 0x0cUL /* rw Third cfg register 0x30 */
28 #define ESP_CFG4 0x0dUL /* rw Fourth cfg register 0x34 */
29 #define ESP_TCHI 0x0eUL /* rw High bits transf count 0x38 */
31 #define FAS_RLO ESP_TCHI /* rw HME extended counter 0x38 */
32 #define ESP_FGRND 0x0fUL /* rw Data base for fifo 0x3c */
33 #define FAS_RHI ESP_FGRND /* rw HME extended counter 0x3c */
H A Dt128.h56 #define T_CONTROL_REG_OFFSET 0x1c00 /* rw */
72 #define T_DATA_REG_OFFSET 0x1e00 /* rw 512 bytes long */
H A Dsun3x_esp.c22 #define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
23 #define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
24 #define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
25 #define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
/linux-4.1.27/arch/sparc/kernel/
H A Dprocess_32.c120 struct reg_window32 *rw = (struct reg_window32 *) r->u_regs[14]; show_regs() local
136 rw->locals[0], rw->locals[1], rw->locals[2], rw->locals[3], show_regs()
137 rw->locals[4], rw->locals[5], rw->locals[6], rw->locals[7]); show_regs()
139 rw->ins[0], rw->ins[1], rw->ins[2], rw->ins[3], show_regs()
140 rw->ins[4], rw->ins[5], rw->ins[6], rw->ins[7]); show_regs()
151 struct reg_window32 *rw; show_stack() local
167 rw = (struct reg_window32 *) fp; show_stack()
168 pc = rw->ins[7]; show_stack()
171 fp = rw->ins[6]; show_stack()
470 struct reg_window32 *rw; get_wchan() local
483 rw = (struct reg_window32 *) fp; get_wchan()
484 pc = rw->ins[7]; get_wchan()
489 fp = rw->ins[6] + bias; get_wchan()
H A Dprocess_64.c101 struct reg_window32 __user *rw; show_regwindow32() local
106 rw = compat_ptr((unsigned)regs->u_regs[14]); show_regwindow32()
109 if (copy_from_user (&r_w, rw, sizeof(r_w))) { show_regwindow32()
130 struct reg_window __user *rw; show_regwindow() local
137 rw = (struct reg_window __user *) show_regwindow()
144 if (copy_from_user (&r_w, rw, sizeof(r_w))) { show_regwindow()
209 struct reg_window *rw; __global_reg_self() local
211 rw = (struct reg_window *) __global_reg_self()
213 if (kstack_valid(tp, (unsigned long) rw)) { __global_reg_self()
214 rp->i7 = rw->ins[7]; __global_reg_self()
215 rw = (struct reg_window *) __global_reg_self()
216 (rw->ins[6] + STACK_BIAS); __global_reg_self()
217 if (kstack_valid(tp, (unsigned long) rw)) __global_reg_self()
218 rp->rpc = rw->ins[7]; __global_reg_self()
753 struct reg_window *rw; get_wchan() local
768 rw = (struct reg_window *) fp; get_wchan()
769 pc = rw->ins[7]; get_wchan()
774 fp = rw->ins[6] + bias; get_wchan()
H A Dtraps_32.c69 struct reg_window32 *rw = (struct reg_window32 *)regs->u_regs[UREG_FP]; die_if_kernel() local
75 while(rw && die_if_kernel()
77 (((unsigned long) rw) >= PAGE_OFFSET) && die_if_kernel()
78 !(((unsigned long) rw) & 0x7)) { die_if_kernel()
79 printk("Caller[%08lx]: %pS\n", rw->ins[7], die_if_kernel()
80 (void *) rw->ins[7]); die_if_kernel()
81 rw = (struct reg_window32 *)rw->ins[6]; die_if_kernel()
/linux-4.1.27/include/linux/usb/
H A Dwusb-wa.h95 __le16 wBlocks; /* rw if 0 */
96 __le16 wMaxPacketSize; /* rw */
98 u8 dwa_bHSHubAddress; /* rw: DWA. */
99 u8 hwa_bMaxBurst; /* rw: HWA. */
102 u8 dwa_bHSHubPort; /* rw: DWA. */
103 u8 hwa_bDeviceInfoIndex; /* rw: HWA. */
105 u8 bSpeed; /* rw: xfer rate 'enum uwb_phy_rate' */
107 u8 dwa_bDeviceAddress; /* rw: DWA Target device address. */
108 u8 hwa_reserved; /* rw: HWA. */
110 u8 bEndpointAddress; /* rw: Target EP address */
114 u8 bInterval; /* rw: */
115 u8 bOverTheAirInterval; /* rw: */
118 u8 bmRetryOptions; /* rw? */
119 __le16 wNumTransactionErrors; /* rw */
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dpriv.h10 bool rw; member in struct:nvbios_source
H A Dshadowacpi.c103 .rw = false,
111 .rw = false,
H A Dshadowpci.c82 .rw = true,
108 .rw = true,
/linux-4.1.27/drivers/md/
H A Ddm-io.c280 static void do_region(int rw, unsigned region, struct dm_io_region *where, do_region() argument
297 if (rw & REQ_DISCARD) do_region()
299 else if (rw & REQ_WRITE_SAME) do_region()
301 if ((rw & (REQ_DISCARD | REQ_WRITE_SAME)) && special_cmd_max_sectors == 0) { do_region()
307 * where->count may be zero if rw holds a flush and we need to do_region()
314 if ((rw & REQ_DISCARD) || (rw & REQ_WRITE_SAME)) do_region()
326 if (rw & REQ_DISCARD) { do_region()
330 } else if (rw & REQ_WRITE_SAME) { do_region()
357 submit_bio(rw, bio); do_region()
361 static void dispatch_io(int rw, unsigned int num_regions, dispatch_io() argument
371 rw |= REQ_SYNC; dispatch_io()
379 if (where[i].count || (rw & REQ_FLUSH)) dispatch_io()
380 do_region(rw, i, where + i, dp, io); dispatch_io()
404 struct dm_io_region *where, int rw, struct dpages *dp, sync_io()
410 if (num_regions > 1 && (rw & RW_MASK) != WRITE) { sync_io()
427 dispatch_io(rw, num_regions, where, dp, io, 1); sync_io()
438 struct dm_io_region *where, int rw, struct dpages *dp, async_io()
443 if (num_regions > 1 && (rw & RW_MASK) != WRITE) { async_io()
459 dispatch_io(rw, num_regions, where, dp, io, 0); async_io()
403 sync_io(struct dm_io_client *client, unsigned int num_regions, struct dm_io_region *where, int rw, struct dpages *dp, unsigned long *error_bits) sync_io() argument
437 async_io(struct dm_io_client *client, unsigned int num_regions, struct dm_io_region *where, int rw, struct dpages *dp, io_notify_fn fn, void *context) async_io() argument
H A Ddm-kcopyd.c334 int rw; member in struct:kcopyd_job
468 if (job->rw & WRITE) complete_io()
480 if (job->rw & WRITE) complete_io()
484 job->rw = WRITE; complete_io()
499 .bi_rw = job->rw, run_io_job()
510 if (job->rw == READ) run_io_job()
553 if (job->rw & WRITE) process_jobs()
728 job->rw = READ; dm_kcopyd_copy()
737 job->rw = WRITE | REQ_WRITE_SAME; dm_kcopyd_copy()
740 job->rw = WRITE; dm_kcopyd_copy()
/linux-4.1.27/arch/tile/lib/
H A Dspinlock_64.c77 void __read_lock_failed(arch_rwlock_t *rw) __read_lock_failed() argument
83 val = __insn_fetchaddgez4(&rw->lock, 1); __read_lock_failed()
94 void __write_lock_failed(arch_rwlock_t *rw, u32 val) __write_lock_failed() argument
99 val = __insn_fetchand4(&rw->lock, ~__WRITE_LOCK_BIT); __write_lock_failed()
101 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT); __write_lock_failed()
/linux-4.1.27/drivers/gpu/drm/ttm/
H A Dttm_lock.c49 lock->rw = 0; ttm_lock_init()
59 if (--lock->rw == 0) ttm_read_unlock()
75 if (lock->rw >= 0 && lock->flags == 0) { __ttm_read_lock()
76 ++lock->rw; __ttm_read_lock()
108 if (lock->rw >= 0 && lock->flags == 0) { __ttm_read_trylock()
109 ++lock->rw; __ttm_read_trylock()
142 lock->rw = 0; ttm_write_unlock()
158 if (lock->rw == 0 && ((lock->flags & ~TTM_WRITE_LOCK_PENDING) == 0)) { __ttm_write_lock()
159 lock->rw = -1; __ttm_write_lock()
219 if (lock->rw == 0) { __ttm_vt_lock()
287 if (lock->rw == 0) { __ttm_suspend_lock()
/linux-4.1.27/arch/powerpc/boot/
H A Dgamecube-head.S58 li 9, 0x0002 /* rw */
67 ori 9, 9, 0x002a /* uncached, guarded, rw */
74 ori 9, 9, 0x0002 /* rw */
H A Dwii-head.S68 li 9, 0x0002 /* rw */
77 ori 9, 9, 0x002a /* uncached, guarded, rw */
84 ori 9, 9, 0x0002 /* rw */
93 ori 9, 9, 0x0002 /* rw */
/linux-4.1.27/arch/powerpc/lib/
H A Dlocks.c51 void __rw_yield(arch_rwlock_t *rw) __rw_yield() argument
56 lock_value = rw->lock; __rw_yield()
65 if (rw->lock != lock_value) __rw_yield()
/linux-4.1.27/drivers/net/ethernet/xilinx/
H A Dll_temac.h66 #define TX_CURDESC_PTR 0x03 /* rw */
67 #define TX_TAILDESC_PTR 0x04 /* rw */
68 #define TX_CHNL_CTRL 0x05 /* rw */
87 #define TX_IRQ_REG 0x06 /* rw */
122 #define RX_CURDESC_PTR 0x0b /* rw */
123 #define RX_TAILDESC_PTR 0x0c /* rw */
124 #define RX_CHNL_CTRL 0x0d /* rw */
138 #define RX_IRQ_REG 0x0e /* rw */
185 #define DMA_CONTROL_REG 0x10 /* rw */
/linux-4.1.27/arch/mips/lasat/
H A Dpicvue.h12 u32 rw; member in struct:pvc_defs
H A Dpicvue.c65 data |= picvue->rw; pvc_read_data()
94 data &= ~picvue->rw; pvc_write()
/linux-4.1.27/drivers/block/
H A Dpmem.c43 unsigned int len, unsigned int off, int rw, pmem_do_bvec()
49 if (rw == READ) { pmem_do_bvec()
64 int rw; pmem_make_request() local
77 rw = bio_data_dir(bio); pmem_make_request()
81 rw, sector); bio_for_each_segment()
90 struct page *page, int rw) pmem_rw_page()
94 pmem_do_bvec(pmem, page, PAGE_CACHE_SIZE, 0, rw, sector); pmem_rw_page()
95 page_endio(page, rw & WRITE, 0); pmem_rw_page()
42 pmem_do_bvec(struct pmem_device *pmem, struct page *page, unsigned int len, unsigned int off, int rw, sector_t sector) pmem_do_bvec() argument
89 pmem_rw_page(struct block_device *bdev, sector_t sector, struct page *page, int rw) pmem_rw_page() argument
H A Dbrd.c300 unsigned int len, unsigned int off, int rw, brd_do_bvec()
306 if (rw != READ) { brd_do_bvec()
313 if (rw == READ) { brd_do_bvec()
330 int rw; brd_make_request() local
346 rw = bio_rw(bio); brd_make_request()
347 if (rw == READA) brd_make_request()
348 rw = READ; brd_make_request()
353 bvec.bv_offset, rw, sector); bio_for_each_segment()
364 struct page *page, int rw) brd_rw_page()
367 int err = brd_do_bvec(brd, page, PAGE_CACHE_SIZE, 0, rw, sector); brd_rw_page()
368 page_endio(page, rw & WRITE, err); brd_rw_page()
299 brd_do_bvec(struct brd_device *brd, struct page *page, unsigned int len, unsigned int off, int rw, sector_t sector) brd_do_bvec() argument
363 brd_rw_page(struct block_device *bdev, sector_t sector, struct page *page, int rw) brd_rw_page() argument
/linux-4.1.27/include/uapi/linux/
H A Dtimex.h130 #define STA_PLL 0x0001 /* enable PLL updates (rw) */
131 #define STA_PPSFREQ 0x0002 /* enable PPS freq discipline (rw) */
132 #define STA_PPSTIME 0x0004 /* enable PPS time discipline (rw) */
133 #define STA_FLL 0x0008 /* select frequency-lock mode (rw) */
135 #define STA_INS 0x0010 /* insert leap (rw) */
136 #define STA_DEL 0x0020 /* delete leap (rw) */
137 #define STA_UNSYNC 0x0040 /* clock unsynchronized (rw) */
138 #define STA_FREQHOLD 0x0080 /* hold frequency (rw) */
/linux-4.1.27/drivers/i2c/busses/
H A Di2c-ali1563.c188 union i2c_smbus_data *data, u8 rw) ali1563_block()
196 if (rw == I2C_SMBUS_WRITE) { ali1563_block()
210 if (rw == I2C_SMBUS_WRITE) { ali1563_block()
235 unsigned short flags, char rw, u8 cmd, ali1563_access()
274 outb_p(((addr & 0x7f) << 1) | (rw & 0x01), SMB_HST_ADD); ali1563_access()
282 if (rw == I2C_SMBUS_WRITE) ali1563_access()
288 if (rw == I2C_SMBUS_WRITE) ali1563_access()
293 if (rw == I2C_SMBUS_WRITE) { ali1563_access()
300 error = ali1563_block(a, data, rw); ali1563_access()
308 if ((rw == I2C_SMBUS_WRITE) || (size == HST_CNTL2_QUICK)) ali1563_access()
187 ali1563_block(struct i2c_adapter *a, union i2c_smbus_data *data, u8 rw) ali1563_block() argument
234 ali1563_access(struct i2c_adapter *a, u16 addr, unsigned short flags, char rw, u8 cmd, int size, union i2c_smbus_data *data) ali1563_access() argument
H A Di2c-cbus-gpio.c111 * @rw: read/write flag
114 * @data: if @rw == I2C_SBUS_WRITE data to send otherwise 0
116 static int cbus_transfer(struct cbus_host *host, char rw, unsigned dev, cbus_transfer() argument
134 /* Send the rw flag */ cbus_transfer()
135 cbus_send_bit(host, rw == I2C_SMBUS_READ); cbus_transfer()
140 if (rw == I2C_SMBUS_WRITE) { cbus_transfer()
H A Dscx200_acb.c278 char rw, u8 command, int size, scx200_acb_smbus_xfer()
295 buffer = rw ? &data->byte : &command; scx200_acb_smbus_xfer()
322 size, address, command, len, rw); scx200_acb_smbus_xfer()
324 if (!len && rw == I2C_SMBUS_READ) { scx200_acb_smbus_xfer()
331 iface->address_byte = (address << 1) | rw; scx200_acb_smbus_xfer()
355 if (rc == 0 && size == I2C_SMBUS_WORD_DATA && rw == I2C_SMBUS_READ) scx200_acb_smbus_xfer()
276 scx200_acb_smbus_xfer(struct i2c_adapter *adapter, u16 address, unsigned short flags, char rw, u8 command, int size, union i2c_smbus_data *data) scx200_acb_smbus_xfer() argument
/linux-4.1.27/arch/sparc/include/uapi/asm/
H A Dasi.h37 /* wo = Write Only, rw = Read Write; */
42 #define ASI_M_FLUSH_PROBE 0x03 /* Reference MMU Flush/Probe; rw, ss */
43 #define ASI_M_MMUREGS 0x04 /* MMU Registers; rw, ss */
47 #define ASI_M_USERTXT 0x08 /* Same as ASI_USERTXT; rw, as */
48 #define ASI_M_KERNELTXT 0x09 /* Same as ASI_KERNELTXT; rw, as */
49 #define ASI_M_USERDATA 0x0A /* Same as ASI_USERDATA; rw, as */
50 #define ASI_M_KERNELDATA 0x0B /* Same as ASI_KERNELDATA; rw, as */
51 #define ASI_M_TXTC_TAG 0x0C /* Instruction Cache Tag; rw, ss */
52 #define ASI_M_TXTC_DATA 0x0D /* Instruction Cache Data; rw, ss */
53 #define ASI_M_DATAC_TAG 0x0E /* Data Cache Tag; rw, ss */
54 #define ASI_M_DATAC_DATA 0x0F /* Data Cache Data; rw, ss */
86 #define ASI_M_BYPASS 0x20 /* Reference MMU bypass; rw, as */
103 #define ASI_M_DCDR 0x39 /* Data Cache Diagnostics Register rw, ss */
/linux-4.1.27/net/nfc/
H A Dllcp_commands.c283 pr_debug("sock %p rw %d miu %d\n", sock, nfc_llcp_parse_connection_tlv()
402 u8 *rw_tlv = NULL, rw_tlv_length, rw; nfc_llcp_send_connect() local
424 rw = sock->rw > LLCP_MAX_RW ? local->rw : sock->rw; nfc_llcp_send_connect()
430 rw_tlv = nfc_llcp_build_tlv(LLCP_TLV_RW, &rw, 0, &rw_tlv_length); nfc_llcp_send_connect()
467 u8 *rw_tlv = NULL, rw_tlv_length, rw; nfc_llcp_send_cc() local
481 rw = sock->rw > LLCP_MAX_RW ? local->rw : sock->rw; nfc_llcp_send_cc()
487 rw_tlv = nfc_llcp_build_tlv(LLCP_TLV_RW, &rw, 0, &rw_tlv_length); nfc_llcp_send_cc()
H A Dllcp_sock.c258 llcp_sock->rw = (u8) opt; nfc_llcp_setsockopt()
291 pr_debug("%p rw %d miux %d\n", llcp_sock, nfc_llcp_setsockopt()
292 llcp_sock->rw, llcp_sock->miux); nfc_llcp_setsockopt()
305 u8 rw; nfc_llcp_getsockopt() local
325 rw = llcp_sock->rw > LLCP_MAX_RW ? local->rw : llcp_sock->rw; nfc_llcp_getsockopt()
326 if (put_user(rw, (u32 __user *) optval)) nfc_llcp_getsockopt()
964 llcp_sock->rw = LLCP_MAX_RW + 1; nfc_llcp_sock_alloc()
/linux-4.1.27/arch/x86/kvm/
H A Dtrace.h100 TP_PROTO(unsigned int rw, unsigned int port, unsigned int size,
102 TP_ARGS(rw, port, size, count, data),
105 __field( unsigned int, rw )
113 __entry->rw = rw;
126 __entry->rw ? "write" : "read",
173 TP_PROTO(unsigned int rw, unsigned int reg, unsigned int val),
174 TP_ARGS(rw, reg, val),
177 __field( unsigned int, rw )
183 __entry->rw = rw;
189 __entry->rw ? "write" : "read",
337 TP_PROTO(unsigned int rw, unsigned int cr, unsigned long val),
338 TP_ARGS(rw, cr, val),
341 __field( unsigned int, rw )
347 __entry->rw = rw;
353 __entry->rw ? "write" : "read",
/linux-4.1.27/arch/sh/drivers/pci/
H A Dcommon.c32 #define EARLY_PCI_OP(rw, size, type) \
33 int __init early_##rw##_config_##size(struct pci_channel *hose, \
36 return pci_##rw##_config_##size( \
/linux-4.1.27/fs/f2fs/
H A Dtrace.c32 last_io.fio.rw, last_io.fio.blk_addr, __print_last_io()
103 last_io.fio.rw == fio->rw && f2fs_trace_ios()
H A Ddata.c101 if (is_read_io(fio->rw)) __submit_merged_bio()
106 submit_bio(fio->rw, io->bio); __submit_merged_bio()
111 enum page_type type, int rw) f2fs_submit_merged_bio()
116 io = is_read_io(rw) ? &sbi->read_io : &sbi->write_io[btype]; f2fs_submit_merged_bio()
124 io->fio.rw = WRITE_FLUSH | REQ_META | REQ_PRIO; f2fs_submit_merged_bio()
126 io->fio.rw = WRITE_FLUSH_FUA | REQ_META | REQ_PRIO; f2fs_submit_merged_bio()
145 bio = __bio_alloc(sbi, fio->blk_addr, 1, is_read_io(fio->rw)); f2fs_submit_page_bio()
153 submit_bio(fio->rw, bio); f2fs_submit_page_bio()
162 bool is_read = is_read_io(fio->rw); f2fs_submit_page_mbio()
174 io->fio.rw != fio->rw)) f2fs_submit_page_mbio()
917 .rw = sync ? READ_SYNC : READA, find_data_page()
990 .rw = READ_SYNC, get_lock_data_page()
1084 .rw = READ_SYNC, get_new_data_page()
1211 * get_data_block() now supported readahead/bmap/rw direct_IO with mapped bh.
1429 .rw = (wbc->sync_mode == WB_SYNC_ALL) ? WRITE_SYNC : WRITE, f2fs_write_data_page()
1649 .rw = READ_SYNC, f2fs_write_begin()
110 f2fs_submit_merged_bio(struct f2fs_sb_info *sbi, enum page_type type, int rw) f2fs_submit_merged_bio() argument
/linux-4.1.27/arch/alpha/kernel/
H A Dvmlinux.lds.S51 _sdata = .; /* Start of rw data section */
/linux-4.1.27/drivers/hwmon/
H A Dltc4215.c26 LTC4215_CONTROL = 0x00, /* rw */
27 LTC4215_ALERT = 0x01, /* rw */
29 LTC4215_FAULT = 0x03, /* rw */
30 LTC4215_SENSE = 0x04, /* rw */
31 LTC4215_SOURCE = 0x05, /* rw */
32 LTC4215_ADIN = 0x06, /* rw */
/linux-4.1.27/include/linux/
H A Disdn_ppp.h48 unsigned char valid:1; /* rw Is this structure filled at all ? */
49 unsigned char rsend:1; /* rw Should we send one at all ? */
50 unsigned char idval:1; /* rw Is the id field valid ? */
51 unsigned char dtval:1; /* rw Is the data field valid ? */
52 unsigned char expra:1; /* rw Is an Ack expected for this Req ? */
55 unsigned short dlen; /* rw Bytes stored in data field */
H A Drwsem-spinlock.h17 * the rw-semaphore definition
/linux-4.1.27/include/trace/events/
H A Df2fs.h602 TP_PROTO(struct inode *inode, loff_t offset, unsigned long len, int rw),
604 TP_ARGS(inode, offset, len, rw),
611 __field(int, rw)
619 __entry->rw = rw;
622 TP_printk("dev = (%d,%d), ino = %lu pos = %lld len = %lu rw = %d",
626 __entry->rw)
632 int rw, int ret),
634 TP_ARGS(inode, offset, len, rw, ret),
641 __field(int, rw)
650 __entry->rw = rw;
655 "rw = %d ret = %d",
659 __entry->rw,
698 __field(int, rw)
707 __entry->rw = fio->rw;
712 "blkaddr = 0x%llx, rw = %s%s, type = %s",
716 show_bio_type(__entry->rw),
747 __field(int, rw)
755 __entry->rw = fio->rw;
763 show_bio_type(__entry->rw),
H A Dext3.h641 TP_PROTO(struct inode *inode, loff_t offset, unsigned long len, int rw),
643 TP_ARGS(inode, offset, len, rw),
650 __field( int, rw )
658 __entry->rw = rw;
661 TP_printk("dev %d,%d ino %lu pos %llu len %lu rw %d",
665 __entry->rw)
670 int rw, int ret),
672 TP_ARGS(inode, offset, len, rw, ret),
679 __field( int, rw )
688 __entry->rw = rw;
692 TP_printk("dev %d,%d ino %lu pos %llu len %lu rw %d ret %d",
696 __entry->rw, __entry->ret)
/linux-4.1.27/drivers/ata/
H A Dpata_ixp4xx_cf.c44 unsigned char *buf, unsigned int buflen, int rw) ixp4xx_mmio_data_xfer()
60 if (rw == READ) ixp4xx_mmio_data_xfer()
72 if (rw == READ) { ixp4xx_mmio_data_xfer()
43 ixp4xx_mmio_data_xfer(struct ata_device *dev, unsigned char *buf, unsigned int buflen, int rw) ixp4xx_mmio_data_xfer() argument
/linux-4.1.27/fs/ocfs2/
H A Drefcounttree.h37 int ocfs2_lock_refcount_tree(struct ocfs2_super *osb, u64 ref_blkno, int rw,
42 int rw);
/linux-4.1.27/drivers/net/irda/
H A Dvlsi_ir.h54 /* VLSI_PCI_CLKCTL: Clock Control Register (u8, rw) */
91 /* VLSI_PCI_MSTRPAGE: Master Page Register (u8, rw) and busmastering stuff */
131 /* VLSI_PCIIRMISC: IR Miscellaneous Register (u8, rw) */
176 VLSI_PIO_IRINTR = 0x00, /* interrupt enable/request (u8, rw) */
178 VLSI_PIO_RINGBASE = 0x04, /* [23:10] of ring address (u16, rw) */
179 VLSI_PIO_RINGSIZE = 0x06, /* rx/tx ring size (u16, rw) */
182 VLSI_PIO_IRCFG = 0x10, /* configuration select (u16, rw) */
184 VLSI_PIO_IRENABLE = 0x14, /* enable and status register (u16, rw/ro) */
186 VLSI_PIO_NPHYCTL = 0x18, /* next physical layer select (u16, rw) */
187 VLSI_PIO_MAXPKT = 0x1a, /* [11:0] max len for packet receive (u16, rw) */
194 /* VLSI_PIO_IRINTR: Interrupt Register (u8, rw) */
260 /* VLSI_PIO_RINGSIZE: Ring Size Register (u16, rw) */
295 /* VLSI_PIO_IRCFG: IR Config Register (u16, rw) */
340 /* VLSI_PIO_IRENABLE: IR Enable Register (u16, rw/ro) */
351 IRENABLE_PHYANDCLOCK = 0x8000, /* enable IR phy and gate the mode config (rw) */
374 /* VLSI_PIO_NPHYCTL: IR Physical Layer Next Control Register (u16, rw) */
464 /* VLSI_PIO_MAXPKT: Maximum Packet Length register (u16, rw) */
/linux-4.1.27/drivers/staging/i2o/
H A Dconfig-osm.c28 /* access mode user rw */
/linux-4.1.27/arch/unicore32/include/mach/
H A Dmemory.h53 /* kuser_vecpage (0xbfff0000) is ro, and vectors page (0xffff0000) is rw */
/linux-4.1.27/fs/hfsplus/
H A Dwrapper.c33 * @rw: direction of I/O
47 void *buf, void **data, int rw) hfsplus_submit_bio()
69 if (!(rw & WRITE) && data) hfsplus_submit_bio()
86 ret = submit_bio_wait(rw, bio); hfsplus_submit_bio()
46 hfsplus_submit_bio(struct super_block *sb, sector_t sector, void *buf, void **data, int rw) hfsplus_submit_bio() argument
/linux-4.1.27/arch/mn10300/kernel/
H A Dvmlinux.lds.S47 _sdata = .; /* Start of rw data section */
/linux-4.1.27/arch/cris/include/asm/
H A Daxisflashmap.h28 __u16 flags; /* bit 0: ro/rw = 1/0 */
/linux-4.1.27/drivers/target/
H A Dtarget_core_iblock.c362 static void iblock_submit_bios(struct bio_list *list, int rw) iblock_submit_bios() argument
369 submit_bio(rw, bio); iblock_submit_bios()
686 int rw = 0; iblock_execute_rw() local
698 rw = WRITE_FUA; iblock_execute_rw()
700 rw = WRITE_FUA; iblock_execute_rw()
702 rw = WRITE; iblock_execute_rw()
704 rw = WRITE; iblock_execute_rw()
707 rw = READ; iblock_execute_rw()
759 iblock_submit_bios(&list, rw); for_each_sg()
783 iblock_submit_bios(&list, rw);
/linux-4.1.27/net/llc/
H A Dllc_c_ev.c54 * @rw: receive window size of receiver.
59 static u16 llc_util_ns_inside_rx_window(u8 ns, u8 vr, u8 rw) llc_util_ns_inside_rx_window() argument
62 (vr + rw - 1) % LLC_2_SEQ_NBR_MODULO); llc_util_ns_inside_rx_window()
205 !llc_util_ns_inside_rx_window(ns, vr, llc_sk(sk)->rw) ? 0 : 1; llc_conn_ev_rx_i_cmd_pbit_set_0_unexpd_ns()
217 !llc_util_ns_inside_rx_window(ns, vr, llc_sk(sk)->rw) ? 0 : 1; llc_conn_ev_rx_i_cmd_pbit_set_1_unexpd_ns()
228 llc_util_ns_inside_rx_window(ns, vr, llc_sk(sk)->rw) ? 0 : 1; llc_conn_ev_rx_i_cmd_pbit_set_x_inval_ns()
272 !llc_util_ns_inside_rx_window(ns, vr, llc_sk(sk)->rw) ? 0 : 1; llc_conn_ev_rx_i_rsp_fbit_set_0_unexpd_ns()
284 !llc_util_ns_inside_rx_window(ns, vr, llc_sk(sk)->rw) ? 0 : 1; llc_conn_ev_rx_i_rsp_fbit_set_1_unexpd_ns()
295 !llc_util_ns_inside_rx_window(ns, vr, llc_sk(sk)->rw) ? 0 : 1; llc_conn_ev_rx_i_rsp_fbit_set_x_unexpd_ns()
306 llc_util_ns_inside_rx_window(ns, vr, llc_sk(sk)->rw) ? 0 : 1; llc_conn_ev_rx_i_rsp_fbit_set_x_inval_ns()
/linux-4.1.27/drivers/staging/lustre/lustre/obdecho/
H A Decho_client.c169 static int cl_echo_object_brw(struct echo_object *eco, int rw, u64 offset,
1171 static int cl_echo_object_brw(struct echo_object *eco, int rw, u64 offset, cl_echo_object_brw() argument
1208 rw == READ ? LCK_PR : LCK_PW, &lh.cookie, cl_echo_object_brw()
1241 enum cl_req_type typ = rw == READ ? CRT_READ : CRT_WRITE; cl_echo_object_brw()
1482 struct page *page, int rw, u64 id, echo_client_page_debug_setup()
1496 if (rw == OBD_BRW_WRITE) { echo_client_page_debug_setup()
1545 static int echo_client_kbrw(struct echo_device *ed, int rw, struct obdo *oa, echo_client_kbrw() argument
1568 LASSERT(rw == OBD_BRW_WRITE || rw == OBD_BRW_READ); echo_client_kbrw()
1579 if (rw == OBD_BRW_WRITE) echo_client_kbrw()
1609 echo_client_page_debug_setup(lsm, pgp->pg, rw, echo_client_kbrw()
1616 rc = cl_echo_object_brw(eco, rw, offset, pages, npages, async); echo_client_kbrw()
1619 if (rc != 0 || rw != OBD_BRW_READ) echo_client_kbrw()
1643 struct obd_export *exp, int rw, echo_client_prep_commit()
1672 if (rw == OBD_BRW_WRITE && async) echo_client_prep_commit()
1695 ret = obd_preprw(env, rw, exp, oa, 1, &ioo, rnb, &lpages, echo_client_prep_commit()
1716 if (rw == OBD_BRW_WRITE) echo_client_prep_commit()
1717 echo_client_page_debug_setup(lsm, page, rw, echo_client_prep_commit()
1728 ret = obd_commitrw(env, rw, exp, oa, 1, &ioo, echo_client_prep_commit()
1749 static int echo_client_brw_ioctl(const struct lu_env *env, int rw, echo_client_brw_ioctl() argument
1789 rc = echo_client_kbrw(ed, rw, oa, echo_client_brw_ioctl()
1794 rc = echo_client_prep_commit(env, ec->ec_exp, rw, oa, echo_client_brw_ioctl()
1867 int rw = OBD_BRW_READ; echo_client_iocontrol() local
1957 rw = OBD_BRW_WRITE; echo_client_iocontrol()
1960 rc = echo_client_brw_ioctl(env, rw, exp, data, &dummy_oti); echo_client_iocontrol()
1481 echo_client_page_debug_setup(struct lov_stripe_md *lsm, struct page *page, int rw, u64 id, u64 offset, u64 count) echo_client_page_debug_setup() argument
1642 echo_client_prep_commit(const struct lu_env *env, struct obd_export *exp, int rw, struct obdo *oa, struct echo_object *eco, u64 offset, u64 count, u64 batch, struct obd_trans_info *oti, int async) echo_client_prep_commit() argument
/linux-4.1.27/drivers/tty/serial/
H A Dsunsab.c424 writeb(up->cached_mode, &up->regs->rw.mode); sunsab_tx_idle()
425 writeb(up->cached_pvr, &up->regs->rw.pvr); sunsab_tx_idle()
429 tmp = readb(&up->regs->rw.ccr2); sunsab_tx_idle()
432 writeb(tmp, &up->regs->rw.ccr2); sunsab_tx_idle()
571 tmp = readb(&up->regs->rw.ccr0); sunsab_startup()
573 writeb(tmp, &up->regs->rw.ccr0); sunsab_startup()
610 up->cached_dafo = readb(&up->regs->rw.dafo); sunsab_shutdown()
612 writeb(up->cached_dafo, &up->regs->rw.dafo); sunsab_shutdown()
616 writeb(up->cached_mode, &up->regs->rw.mode); sunsab_shutdown()
630 tmp = readb(&up->regs->rw.ccr0); sunsab_shutdown()
632 writeb(tmp, &up->regs->rw.ccr0); sunsab_shutdown()
1008 up->cached_mode = readb(&up->regs->rw.mode); sunsab_init_one()
1010 writeb(up->cached_mode, &up->regs->rw.mode); sunsab_init_one()
1012 writeb(up->cached_mode, &up->regs->rw.mode); sunsab_init_one()

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