Searched refs:rv730 (Results 1 - 4 of 4) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
H A Drv730_dpm.c46 u32 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl; rv730_populate_sclk_value()
47 u32 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2; rv730_populate_sclk_value()
48 u32 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3; rv730_populate_sclk_value()
49 u32 cg_spll_spread_spectrum = pi->clk_regs.rv730.cg_spll_spread_spectrum; rv730_populate_sclk_value()
50 u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv730.cg_spll_spread_spectrum_2; rv730_populate_sclk_value()
124 u32 mclk_pwrmgt_cntl = pi->clk_regs.rv730.mclk_pwrmgt_cntl; rv730_populate_mclk_value()
125 u32 dll_cntl = pi->clk_regs.rv730.dll_cntl; rv730_populate_mclk_value()
126 u32 mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl; rv730_populate_mclk_value()
127 u32 mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2; rv730_populate_mclk_value()
128 u32 mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3; rv730_populate_mclk_value()
129 u32 mpll_ss = pi->clk_regs.rv730.mpll_ss; rv730_populate_mclk_value()
130 u32 mpll_ss2 = pi->clk_regs.rv730.mpll_ss2; rv730_populate_mclk_value()
202 pi->clk_regs.rv730.cg_spll_func_cntl = rv730_read_clock_registers()
204 pi->clk_regs.rv730.cg_spll_func_cntl_2 = rv730_read_clock_registers()
206 pi->clk_regs.rv730.cg_spll_func_cntl_3 = rv730_read_clock_registers()
208 pi->clk_regs.rv730.cg_spll_spread_spectrum = rv730_read_clock_registers()
210 pi->clk_regs.rv730.cg_spll_spread_spectrum_2 = rv730_read_clock_registers()
213 pi->clk_regs.rv730.mclk_pwrmgt_cntl = rv730_read_clock_registers()
215 pi->clk_regs.rv730.dll_cntl = rv730_read_clock_registers()
217 pi->clk_regs.rv730.mpll_func_cntl = rv730_read_clock_registers()
219 pi->clk_regs.rv730.mpll_func_cntl2 = rv730_read_clock_registers()
221 pi->clk_regs.rv730.mpll_func_cntl3 = rv730_read_clock_registers()
223 pi->clk_regs.rv730.mpll_ss = rv730_read_clock_registers()
225 pi->clk_regs.rv730.mpll_ss2 = rv730_read_clock_registers()
258 mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl; rv730_populate_smc_acpi_state()
259 mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2; rv730_populate_smc_acpi_state()
260 mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3; rv730_populate_smc_acpi_state()
287 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl; rv730_populate_smc_acpi_state()
288 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2; rv730_populate_smc_acpi_state()
289 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3; rv730_populate_smc_acpi_state()
328 cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl); rv730_populate_smc_initial_state()
330 cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl2); rv730_populate_smc_initial_state()
332 cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl3); rv730_populate_smc_initial_state()
334 cpu_to_be32(pi->clk_regs.rv730.mclk_pwrmgt_cntl); rv730_populate_smc_initial_state()
336 cpu_to_be32(pi->clk_regs.rv730.dll_cntl); rv730_populate_smc_initial_state()
338 cpu_to_be32(pi->clk_regs.rv730.mpll_ss); rv730_populate_smc_initial_state()
340 cpu_to_be32(pi->clk_regs.rv730.mpll_ss2); rv730_populate_smc_initial_state()
346 cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl); rv730_populate_smc_initial_state()
348 cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_2); rv730_populate_smc_initial_state()
350 cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_3); rv730_populate_smc_initial_state()
352 cpu_to_be32(pi->clk_regs.rv730.cg_spll_spread_spectrum); rv730_populate_smc_initial_state()
354 cpu_to_be32(pi->clk_regs.rv730.cg_spll_spread_spectrum_2); rv730_populate_smc_initial_state()
H A Drv770_dpm.h61 struct rv730_clock_registers rv730; member in union:r7xx_clock_registers
178 /* rv730/rv710 */
H A Dradeon_asic.h460 * rv770,rv730,rv710,rv740
H A Dradeon_atombios.c363 /* mac rv630, rv730, others */ radeon_atom_apply_quirks()
427 /* XFX Pine Group device rv730 reports no VGA DDC lines radeon_atom_apply_quirks()

Completed in 190 milliseconds