Searched refs:rtsx_pci_add_cmd (Results 1 - 9 of 9) sorted by relevance

/linux-4.1.27/drivers/memstick/host/
H A Drtsx_pci_ms.c67 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0); ms_print_debug_regs()
69 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0); ms_print_debug_regs()
91 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, MS_MOD_SEL); ms_power_on()
92 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, ms_power_on()
94 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, ms_power_on()
126 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, MS_CLK_EN, 0); ms_power_off()
127 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN, 0); ms_power_off()
165 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); ms_transfer_data()
167 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_SECTOR_CNT_H, ms_transfer_data()
169 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_SECTOR_CNT_L, ms_transfer_data()
172 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); ms_transfer_data()
174 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, ms_transfer_data()
176 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 0xFF, (u8)(length >> 24)); ms_transfer_data()
177 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 0xFF, (u8)(length >> 16)); ms_transfer_data()
178 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 0xFF, (u8)(length >> 8)); ms_transfer_data()
179 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)length); ms_transfer_data()
180 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, ms_transfer_data()
182 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, ms_transfer_data()
185 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANSFER, ms_transfer_data()
187 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, MS_TRANSFER, ms_transfer_data()
225 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ms_write_bytes()
228 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ms_write_bytes()
231 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); ms_write_bytes()
232 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); ms_write_bytes()
233 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); ms_write_bytes()
234 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, ms_write_bytes()
237 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANSFER, ms_write_bytes()
239 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, MS_TRANSFER, ms_write_bytes()
242 rtsx_pci_add_cmd(pcr, READ_REG_CMD, MS_TRANS_CFG, 0, 0); ms_write_bytes()
293 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); ms_read_bytes()
294 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); ms_read_bytes()
295 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); ms_read_bytes()
296 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, ms_read_bytes()
299 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANSFER, ms_read_bytes()
301 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, MS_TRANSFER, ms_read_bytes()
304 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0); ms_read_bytes()
306 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PPBUF_BASE2 + cnt, 0, 0); ms_read_bytes()
308 rtsx_pci_add_cmd(pcr, READ_REG_CMD, ms_read_bytes()
311 rtsx_pci_add_cmd(pcr, READ_REG_CMD, MS_TRANS_CFG, 0, 0); ms_read_bytes()
/linux-4.1.27/drivers/mfd/
H A Drts5227.c53 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL, rts5227_fill_driving()
55 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL, rts5227_fill_driving()
57 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL, rts5227_fill_driving()
103 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02); rts5227_extra_init_hw()
105 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0); rts5227_extra_init_hw()
107 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00); rts5227_extra_init_hw()
108 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01); rts5227_extra_init_hw()
110 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02); rts5227_extra_init_hw()
114 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3); rts5227_extra_init_hw()
116 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03); rts5227_extra_init_hw()
121 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0xB8); rts5227_extra_init_hw()
123 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0x88); rts5227_extra_init_hw()
124 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00); rts5227_extra_init_hw()
166 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, rts5227_card_power_on()
168 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, rts5227_card_power_on()
178 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, rts5227_card_power_on()
180 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, rts5227_card_power_on()
192 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, rts5227_card_power_off()
195 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, rts5227_card_power_off()
H A Drts5229.c68 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02); rts5229_extra_init_hw()
70 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0); rts5229_extra_init_hw()
72 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08); rts5229_extra_init_hw()
74 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00); rts5229_extra_init_hw()
75 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01); rts5229_extra_init_hw()
77 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02); rts5229_extra_init_hw()
79 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL, rts5229_extra_init_hw()
116 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, rts5229_card_power_on()
118 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, rts5229_card_power_on()
128 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, rts5229_card_power_on()
130 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, rts5229_card_power_on()
142 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, rts5229_card_power_off()
145 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, rts5229_card_power_off()
H A Drts5209.c71 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_GPIO, 0xFF, 0x03); rts5209_extra_init_hw()
73 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0); rts5209_extra_init_hw()
75 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08); rts5209_extra_init_hw()
77 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_GPIO_DIR, 0xFF, 0x03); rts5209_extra_init_hw()
79 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL, rts5209_extra_init_hw()
126 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, rts5209_card_power_on()
128 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, rts5209_card_power_on()
138 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, pwr_mask, pwr_on); rts5209_card_power_on()
139 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, rts5209_card_power_on()
161 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, rts5209_card_power_off()
163 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, rts5209_card_power_off()
H A Drts5249.c60 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL, rts5249_fill_driving()
62 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL, rts5249_fill_driving()
64 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL, rts5249_fill_driving()
111 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00); rts5249_extra_init_hw()
113 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02); rts5249_extra_init_hw()
115 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0); rts5249_extra_init_hw()
117 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00); rts5249_extra_init_hw()
118 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01); rts5249_extra_init_hw()
120 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02); rts5249_extra_init_hw()
124 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0); rts5249_extra_init_hw()
126 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80); rts5249_extra_init_hw()
222 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, rtsx_base_card_power_on()
224 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, rtsx_base_card_power_on()
233 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, rtsx_base_card_power_on()
235 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, rtsx_base_card_power_on()
247 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, rtsx_base_card_power_off()
249 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, rtsx_base_card_power_off()
H A Drtsx_pcr.c154 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val); __rtsx_pci_write_phy_register()
155 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8)); __rtsx_pci_write_phy_register()
156 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr); __rtsx_pci_write_phy_register()
157 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81); __rtsx_pci_write_phy_register()
197 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr); __rtsx_pci_read_phy_register()
198 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80); __rtsx_pci_read_phy_register()
220 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0); __rtsx_pci_read_phy_register()
221 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0); __rtsx_pci_read_phy_register()
255 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr, rtsx_pci_add_cmd() function
276 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd); variable
491 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); rtsx_pci_read_ppbuf()
505 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); rtsx_pci_read_ppbuf()
534 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, rtsx_pci_write_ppbuf()
548 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, rtsx_pci_write_ppbuf()
569 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, rtsx_pci_set_pull_ctl()
713 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, rtsx_pci_switch_clock()
715 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, rtsx_pci_switch_clock()
717 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); rtsx_pci_switch_clock()
718 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, rtsx_pci_switch_clock()
720 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); rtsx_pci_switch_clock()
721 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); rtsx_pci_switch_clock()
723 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, rtsx_pci_switch_clock()
725 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, rtsx_pci_switch_clock()
1019 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07); rtsx_pci_init_hw()
1021 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00); rtsx_pci_init_hw()
1023 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0); rtsx_pci_init_hw()
1025 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0); rtsx_pci_init_hw()
1027 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL, rtsx_pci_init_hw()
1030 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, rtsx_pci_init_hw()
1032 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12); rtsx_pci_init_hw()
1034 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10); rtsx_pci_init_hw()
1036 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, rtsx_pci_init_hw()
1041 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80); rtsx_pci_init_hw()
1046 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00); rtsx_pci_init_hw()
1052 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0); rtsx_pci_init_hw()
H A Drtl8411.c98 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL, rtl8411_extra_init_hw()
100 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CD_PAD_CTL, rtl8411_extra_init_hw()
111 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, rtl8411b_extra_init_hw()
113 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL, rtl8411b_extra_init_hw()
115 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CD_PAD_CTL, rtl8411b_extra_init_hw()
117 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, FUNC_FORCE_CTL, rtl8411b_extra_init_hw()
148 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, rtl8411_card_power_on()
150 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_CTL, rtl8411_card_power_on()
/linux-4.1.27/drivers/mmc/host/
H A Drtsx_pci_sdmmc.c110 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, sd_cmd_set_sd_cmd()
117 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks); sd_cmd_set_data_len()
118 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8); sd_cmd_set_data_len()
119 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz); sd_cmd_set_data_len()
120 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8); sd_cmd_set_data_len()
260 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); sd_send_cmd_get_rsp()
261 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, sd_send_cmd_get_rsp()
263 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, sd_send_cmd_get_rsp()
265 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, sd_send_cmd_get_rsp()
272 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); sd_send_cmd_get_rsp()
276 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); sd_send_cmd_get_rsp()
279 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0); sd_send_cmd_get_rsp()
362 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, sd_read_data()
366 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, sd_read_data()
369 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, sd_read_data()
371 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, sd_read_data()
422 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, sd_write_data()
425 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, sd_write_data()
427 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, sd_write_data()
468 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, sd_read_long_data()
470 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, sd_read_long_data()
472 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, sd_read_long_data()
474 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, sd_read_long_data()
476 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); sd_read_long_data()
477 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, sd_read_long_data()
480 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, sd_read_long_data()
482 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type); sd_read_long_data()
483 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, sd_read_long_data()
485 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, sd_read_long_data()
527 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, sd_write_long_data()
529 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, sd_write_long_data()
531 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, sd_write_long_data()
533 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, sd_write_long_data()
535 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); sd_write_long_data()
536 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, sd_write_long_data()
539 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, sd_write_long_data()
541 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); sd_write_long_data()
542 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, sd_write_long_data()
544 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, sd_write_long_data()
630 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK); sd_change_phase()
632 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, sd_change_phase()
635 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, sd_change_phase()
637 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); sd_change_phase()
638 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, sd_change_phase()
640 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0); sd_change_phase()
641 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); sd_change_phase()
917 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL); sd_power_on()
918 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, sd_power_on()
920 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, sd_power_on()
951 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); sd_power_off()
952 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); sd_power_off()
988 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, sd_set_timing()
991 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, sd_set_timing()
993 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, sd_set_timing()
995 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); sd_set_timing()
1000 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, sd_set_timing()
1003 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, sd_set_timing()
1005 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, sd_set_timing()
1007 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); sd_set_timing()
1008 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, sd_set_timing()
1010 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, sd_set_timing()
1017 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, sd_set_timing()
1019 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, sd_set_timing()
1021 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, sd_set_timing()
1023 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); sd_set_timing()
1024 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, sd_set_timing()
1026 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, sd_set_timing()
1031 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, sd_set_timing()
1033 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, sd_set_timing()
1035 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, sd_set_timing()
1037 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); sd_set_timing()
1038 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, sd_set_timing()
1040 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, sd_set_timing()
/linux-4.1.27/include/linux/mfd/
H A Drtsx_pci.h982 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
1026 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg, 0xFF, val >> 24); rtsx_pci_write_be32()
1027 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 1, 0xFF, val >> 16); rtsx_pci_write_be32()
1028 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 2, 0xFF, val >> 8); rtsx_pci_write_be32()
1029 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val); rtsx_pci_write_be32()

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