Searched refs:rtl8192_setBBreg (Results 1 - 10 of 10) sorted by relevance

/linux-4.1.27/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phy.c83 void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask, rtl8192_setBBreg() function
120 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); rtl8192_phy_RFSerialRead()
123 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, rtl8192_phy_RFSerialRead()
130 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, rtl8192_phy_RFSerialRead()
142 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, rtl8192_phy_RFSerialRead()
144 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); rtl8192_phy_RFSerialRead()
145 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); rtl8192_phy_RFSerialRead()
155 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, rtl8192_phy_RFSerialRead()
158 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); rtl8192_phy_RFSerialRead()
176 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); rtl8192_phy_RFSerialWrite()
180 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, rtl8192_phy_RFSerialWrite()
187 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, rtl8192_phy_RFSerialWrite()
201 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); rtl8192_phy_RFSerialWrite()
209 rtl8192_setBBreg( rtl8192_phy_RFSerialWrite()
215 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); rtl8192_phy_RFSerialWrite()
353 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], rtl8192_phy_configmac()
380 rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], rtl8192_phyConfigBB()
390 rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], rtl8192_phyConfigBB()
576 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); rtl8192_BB_Config_ParaFile()
591 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, rtl8192_BB_Config_ParaFile()
596 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, rtl8192_BB_Config_ParaFile()
674 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, rtl8192_phy_setTxPower()
1208 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); rtl8192_SetBWModeWorkItem()
1209 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); rtl8192_SetBWModeWorkItem()
1219 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); rtl8192_SetBWModeWorkItem()
1223 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); rtl8192_SetBWModeWorkItem()
1224 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); rtl8192_SetBWModeWorkItem()
1234 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, rtl8192_SetBWModeWorkItem()
1236 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, rtl8192_SetBWModeWorkItem()
1239 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); rtl8192_SetBWModeWorkItem()
1316 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); InitialGain819xPci()
1365 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); InitialGain819xPci()
1367 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, InitialGain819xPci()
1369 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, InitialGain819xPci()
1371 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, InitialGain819xPci()
1373 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, InitialGain819xPci()
1376 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, InitialGain819xPci()
1400 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); InitialGain819xPci()
1412 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); PHY_SetRtl8192eRfOff()
1413 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0); PHY_SetRtl8192eRfOff()
1414 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); PHY_SetRtl8192eRfOff()
1415 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); PHY_SetRtl8192eRfOff()
1416 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); PHY_SetRtl8192eRfOff()
1417 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); PHY_SetRtl8192eRfOff()
1418 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0); PHY_SetRtl8192eRfOff()
1467 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, SetRFPowerState8190()
1471 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, SetRFPowerState8190()
1473 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, SetRFPowerState8190()
1475 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, SetRFPowerState8190()
1477 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, SetRFPowerState8190()
1479 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, SetRFPowerState8190()
1481 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, SetRFPowerState8190()
H A Dr8190P_rtl8256.c127 rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); phy_RF8256_Config_ParaFile()
129 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); phy_RF8256_Config_ParaFile()
131 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, phy_RF8256_Config_ParaFile()
133 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, phy_RF8256_Config_ParaFile()
219 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, phy_RF8256_Config_ParaFile()
224 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, phy_RF8256_Config_ParaFile()
260 rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); PHY_SetRF8256CCKTxPower()
306 rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); PHY_SetRF8256OFDMTxPower()
H A Drtl_dm.c590 rtl8192_setBBreg(dev, dm_TXPowerTrackingCallback_TSSI()
599 rtl8192_setBBreg(dev, dm_TXPowerTrackingCallback_TSSI()
605 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, dm_TXPowerTrackingCallback_TSSI()
608 rtl8192_setBBreg(dev, dm_TXPowerTrackingCallback_TSSI()
617 rtl8192_setBBreg(dev, dm_TXPowerTrackingCallback_TSSI()
623 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, dm_TXPowerTrackingCallback_TSSI()
635 rtl8192_setBBreg(dev, dm_TXPowerTrackingCallback_TSSI()
642 rtl8192_setBBreg(dev, dm_TXPowerTrackingCallback_TSSI()
647 rtl8192_setBBreg(dev, dm_TXPowerTrackingCallback_TSSI()
651 rtl8192_setBBreg(dev, dm_TXPowerTrackingCallback_TSSI()
659 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, dm_TXPowerTrackingCallback_TSSI()
663 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, dm_TXPowerTrackingCallback_TSSI()
826 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, dm_TXPowerTrackingCallback_ThermalMeter()
1445 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); dm_CCKTxPowerAdjust_TSSI()
1450 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); dm_CCKTxPowerAdjust_TSSI()
1454 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); dm_CCKTxPowerAdjust_TSSI()
1459 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); dm_CCKTxPowerAdjust_TSSI()
1464 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); dm_CCKTxPowerAdjust_TSSI()
1468 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); dm_CCKTxPowerAdjust_TSSI()
1483 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); dm_CCKTxPowerAdjust_ThermalMeter()
1490 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); dm_CCKTxPowerAdjust_ThermalMeter()
1496 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); dm_CCKTxPowerAdjust_ThermalMeter()
1503 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); dm_CCKTxPowerAdjust_ThermalMeter()
1510 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); dm_CCKTxPowerAdjust_ThermalMeter()
1516 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); dm_CCKTxPowerAdjust_ThermalMeter()
1537 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, dm_txpower_reset_recovery()
1549 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, dm_txpower_reset_recovery()
1596 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); dm_bb_initialgain_restore()
1597 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1); dm_bb_initialgain_restore()
1598 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1); dm_bb_initialgain_restore()
1599 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1); dm_bb_initialgain_restore()
1600 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1); dm_bb_initialgain_restore()
1602 rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca); dm_bb_initialgain_restore()
1609 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); dm_bb_initialgain_restore()
1633 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); dm_bb_initialgain_backup()
1782 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); dm_ctrl_initgain_byrssi_by_driverrssi()
1817 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); dm_ctrl_initgain_byrssi_by_fwfalse_alarm()
1836 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); dm_ctrl_initgain_byrssi_by_fwfalse_alarm()
1887 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); dm_ctrl_initgain_byrssi_by_fwfalse_alarm()
2504 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, dm_rxpath_sel_byrssi()
2506 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, dm_rxpath_sel_byrssi()
2521 rtl8192_setBBreg(dev, rCCK0_AFESetting, 0x0f000000, dm_rxpath_sel_byrssi()
2530 rtl8192_setBBreg(dev, dm_rxpath_sel_byrssi()
2533 rtl8192_setBBreg(dev, dm_rxpath_sel_byrssi()
H A Dr8192E_phy.h78 extern void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr,
H A Dr8192E_dev.c878 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); rtl8192_adapter_start()
879 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); rtl8192_adapter_start()
/linux-4.1.27/drivers/staging/rtl8192u/
H A Dr819xU_phy.c89 void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask, rtl8192_setBBreg() function
154 rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0); rtl8192_phy_RFSerialRead()
163 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, rtl8192_phy_RFSerialRead()
172 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, rtl8192_phy_RFSerialRead()
186 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, rtl8192_phy_RFSerialRead()
189 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); rtl8192_phy_RFSerialRead()
190 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); rtl8192_phy_RFSerialRead()
204 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, rtl8192_phy_RFSerialRead()
244 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, rtl8192_phy_RFSerialWrite()
251 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, rtl8192_phy_RFSerialWrite()
268 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); rtl8192_phy_RFSerialWrite()
278 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, rtl8192_phy_RFSerialWrite()
508 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], rtl8192_phy_configmac()
538 rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i], rtl8192_phyConfigBB()
548 rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i], rtl8192_phyConfigBB()
809 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); rtl8192_BB_Config_ParaFile()
828 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), rtl8192_BB_Config_ParaFile()
833 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, rtl8192_BB_Config_ParaFile()
1113 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, rtl8192_SetRFPowerState()
1116 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, rtl8192_SetRFPowerState()
1119 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, rtl8192_SetRFPowerState()
1122 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3); rtl8192_SetRFPowerState()
1124 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3); rtl8192_SetRFPowerState()
1126 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, rtl8192_SetRFPowerState()
1138 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, rtl8192_SetRFPowerState()
1141 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, rtl8192_SetRFPowerState()
1144 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, rtl8192_SetRFPowerState()
1147 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); rtl8192_SetRFPowerState()
1149 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); rtl8192_SetRFPowerState()
1151 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, rtl8192_SetRFPowerState()
1559 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); rtl8192_SetBWModeWorkItem()
1560 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); rtl8192_SetBWModeWorkItem()
1561 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, rtl8192_SetBWModeWorkItem()
1589 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); rtl8192_SetBWModeWorkItem()
1590 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); rtl8192_SetBWModeWorkItem()
1591 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, rtl8192_SetBWModeWorkItem()
1593 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); rtl8192_SetBWModeWorkItem()
1594 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, rtl8192_SetBWModeWorkItem()
1721 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); InitialGainOperateWorkItemCallBack()
1760 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); InitialGainOperateWorkItemCallBack()
1762 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bitmask, InitialGainOperateWorkItemCallBack()
1764 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bitmask, InitialGainOperateWorkItemCallBack()
1766 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bitmask, InitialGainOperateWorkItemCallBack()
1768 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bitmask, InitialGainOperateWorkItemCallBack()
1771 rtl8192_setBBreg(dev, rCCK0_CCA, bitmask, InitialGainOperateWorkItemCallBack()
1789 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); InitialGainOperateWorkItemCallBack()
H A Dr8190_rtl8256.c138 rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); phy_RF8256_Config_ParaFile()
141 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); phy_RF8256_Config_ParaFile()
144 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258 */ phy_RF8256_Config_ParaFile()
145 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ??? */ phy_RF8256_Config_ParaFile()
199 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); phy_RF8256_Config_ParaFile()
203 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); phy_RF8256_Config_ParaFile()
237 rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); PHY_SetRF8256CCKTxPower()
286 rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); PHY_SetRF8256OFDMTxPower()
H A Dr8192U_dm.c605 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value); dm_TXPowerTrackingCallback_TSSI()
612 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value); dm_TXPowerTrackingCallback_TSSI()
756 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[priv->OFDM_index]); dm_TXPowerTrackingCallback_ThermalMeter()
1380 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); dm_CCKTxPowerAdjust_TSSI()
1386 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); dm_CCKTxPowerAdjust_TSSI()
1391 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); dm_CCKTxPowerAdjust_TSSI()
1396 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); dm_CCKTxPowerAdjust_TSSI()
1402 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); dm_CCKTxPowerAdjust_TSSI()
1407 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); dm_CCKTxPowerAdjust_TSSI()
1421 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); dm_CCKTxPowerAdjust_ThermalMeter()
1429 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); dm_CCKTxPowerAdjust_ThermalMeter()
1436 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); dm_CCKTxPowerAdjust_ThermalMeter()
1445 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); dm_CCKTxPowerAdjust_ThermalMeter()
1453 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); dm_CCKTxPowerAdjust_ThermalMeter()
1460 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); dm_CCKTxPowerAdjust_ThermalMeter()
1484 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value); dm_txpower_reset_recovery()
1491 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value); dm_txpower_reset_recovery()
1549 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */ dm_bb_initialgain_restore()
1550 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1); dm_bb_initialgain_restore()
1551 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1); dm_bb_initialgain_restore()
1552 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1); dm_bb_initialgain_restore()
1553 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1); dm_bb_initialgain_restore()
1555 rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca); dm_bb_initialgain_restore()
1564 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); /* Only clear byte 1 and rewrite. */ dm_bb_initialgain_restore()
1589 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */ dm_bb_initialgain_backup()
1763 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */ dm_ctrl_initgain_byrssi_by_driverrssi()
1802 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); /* Only clear byte 1 and rewrite.*/ dm_ctrl_initgain_byrssi_by_fwfalse_alarm()
1835 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); /* Only clear byte 1 and rewrite. */ dm_ctrl_initgain_byrssi_by_fwfalse_alarm()
1929 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); /* Only clear byte 1 and rewrite. */ dm_ctrl_initgain_byrssi_by_fwfalse_alarm()
2616 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<min_rssi_index, 0x0); /* 0xc04[3:0] */ dm_rxpath_sel_byrssi()
2617 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<min_rssi_index, 0x0); /* 0xd04[3:0] */ dm_rxpath_sel_byrssi()
2630 rtl8192_setBBreg(dev, rCCK0_AFESetting, 0x0f000000, DM_RxPathSelTable.cck_Rx_path); dm_rxpath_sel_byrssi()
2639 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<i, 0x1); /* 0xc04[3:0] */ dm_rxpath_sel_byrssi()
2640 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<i, 0x1); /* 0xd04[3:0] */ dm_rxpath_sel_byrssi()
H A Dr819xU_phy.h61 extern void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr,
H A Dr8192U_core.c2804 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); rtl8192_adapter_start()
2805 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); rtl8192_adapter_start()

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