Searched refs:reg_table (Results 1 – 4 of 4) sorted by relevance
553 static bool check_sorted(int ring_id, const u32 *reg_table, int reg_count) in check_sorted() argument560 u32 curr = reg_table[i]; in check_sorted()576 return check_sorted(ring->id, ring->reg_table, ring->reg_count) && in validate_regs_sorted()673 ring->reg_table = gen7_render_regs; in i915_cmd_parser_init_ring()700 ring->reg_table = gen7_blt_regs; in i915_cmd_parser_init_ring()979 if (!valid_reg(ring->reg_table, in check_cmd()
302 const u32 *reg_table; member
3974 struct atom_mc_reg_table *reg_table) in radeon_atom_init_mc_reg_table() argument3982 memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); in radeon_atom_init_mc_reg_table()4011 reg_table->mc_reg_address[i].s1 = in radeon_atom_init_mc_reg_table()4013 reg_table->mc_reg_address[i].pre_reg_data = in radeon_atom_init_mc_reg_table()4019 reg_table->last = i; in radeon_atom_init_mc_reg_table()4025 reg_table->mc_reg_table_entry[num_ranges].mclk_max = in radeon_atom_init_mc_reg_table()4028 for (i = 0, j = 1; i < reg_table->last; i++) { in radeon_atom_init_mc_reg_table()4029 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { in radeon_atom_init_mc_reg_table()4030 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = in radeon_atom_init_mc_reg_table()4033 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { in radeon_atom_init_mc_reg_table()[all …]
338 struct atom_mc_reg_table *reg_table);