Searched refs:reference_divider (Results 1 – 6 of 6) sorted by relevance
53 u32 reference_divider, post_divider; in rv730_populate_sclk_value() local62 reference_divider = 1 + dividers.ref_div; in rv730_populate_sclk_value()70 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv730_populate_sclk_value()97 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv730_populate_sclk_value()132 u32 post_divider, reference_divider; in rv730_populate_mclk_value() local140 reference_divider = dividers.ref_div + 1; in rv730_populate_mclk_value()173 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv730_populate_mclk_value()
133 u32 reference_divider; in rv740_populate_sclk_value() local142 reference_divider = 1 + dividers.ref_div; in rv740_populate_sclk_value()144 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()165 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv740_populate_sclk_value()
325 u32 post_divider, reference_divider, feedback_divider8; in rv770_calculate_fractional_mpll_feedback_divider() local334 reference_divider = dividers->ref_div; in rv770_calculate_fractional_mpll_feedback_divider()337 (8 * fyclk * reference_divider * post_divider) / reference_clock; in rv770_calculate_fractional_mpll_feedback_divider()502 u32 reference_divider, post_divider; in rv770_populate_sclk_value() local511 reference_divider = 1 + dividers.ref_div; in rv770_populate_sclk_value()518 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv770_populate_sclk_value()544 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv770_populate_sclk_value()
2013 u32 reference_divider; in ni_calculate_sclk_params() local2022 reference_divider = 1 + dividers.ref_div; in ni_calculate_sclk_params()2025 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834; in ni_calculate_sclk_params()2046 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in ni_calculate_sclk_params()
4735 u32 reference_divider; in si_calculate_sclk_params() local4744 reference_divider = 1 + dividers.ref_div; in si_calculate_sclk_params()4746 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in si_calculate_sclk_params()4767 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in si_calculate_sclk_params()
3140 u32 reference_divider; in ci_calculate_sclk_params() local3150 reference_divider = 1 + dividers.ref_div; in ci_calculate_sclk_params()3163 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in ci_calculate_sclk_params()