Searched refs:reference_div (Results 1 – 7 of 7) sorted by relevance
117 p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; in radeon_read_clocks_OF()118 if (p1pll->reference_div < 2) in radeon_read_clocks_OF()119 p1pll->reference_div = 12; in radeon_read_clocks_OF()120 p2pll->reference_div = p1pll->reference_div; in radeon_read_clocks_OF()146 spll->reference_div = mpll->reference_div = in radeon_read_clocks_OF()193 if (p1pll->reference_div < 2) { in radeon_get_clock_info()197 p1pll->reference_div = in radeon_get_clock_info()200 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; in radeon_get_clock_info()201 if (p1pll->reference_div < 2) in radeon_get_clock_info()202 p1pll->reference_div = 12; in radeon_get_clock_info()[all …]
741 uint32_t reference_div = 0; in radeon_set_pll() local820 &reference_div, &post_divider); in radeon_set_pll()833 reference_div, in radeon_set_pll()836 pll_ref_div = reference_div; in radeon_set_pll()
956 ref_div_min = pll->reference_div; in radeon_compute_pll_avivo()962 ref_div_max = pll->reference_div; in radeon_compute_pll_avivo()1121 min_ref_div = max_ref_div = pll->reference_div; in radeon_compute_pll_legacy()
170 uint32_t reference_div; member
747 p1pll->reference_div = RBIOS16(pll_info + 0x10); in radeon_combios_get_clock_info()764 spll->reference_div = RBIOS16(pll_info + 0x1c); in radeon_combios_get_clock_info()779 mpll->reference_div = RBIOS16(pll_info + 0x28); in radeon_combios_get_clock_info()
1156 p1pll->reference_div = 0; in radeon_atom_get_clock_info()1202 spll->reference_div = 0; in radeon_atom_get_clock_info()1229 mpll->reference_div = 0; in radeon_atom_get_clock_info()
1089 pll->reference_div = radeon_crtc->pll_reference_div; in atombios_crtc_set_pll()