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Searched refs:radeon_get_ib_value (Results 1 – 9 of 9) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
Devergreen_cs.c760 texdw[0] = radeon_get_ib_value(p, idx + 0); in evergreen_cs_track_validate_texture()
761 texdw[1] = radeon_get_ib_value(p, idx + 1); in evergreen_cs_track_validate_texture()
762 texdw[2] = radeon_get_ib_value(p, idx + 2); in evergreen_cs_track_validate_texture()
763 texdw[3] = radeon_get_ib_value(p, idx + 3); in evergreen_cs_track_validate_texture()
764 texdw[4] = radeon_get_ib_value(p, idx + 4); in evergreen_cs_track_validate_texture()
765 texdw[5] = radeon_get_ib_value(p, idx + 5); in evergreen_cs_track_validate_texture()
766 texdw[6] = radeon_get_ib_value(p, idx + 6); in evergreen_cs_track_validate_texture()
767 texdw[7] = radeon_get_ib_value(p, idx + 7); in evergreen_cs_track_validate_texture()
1172 track->db_depth_control = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1190 track->db_z_info = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
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Dr600_cs.c850 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); in r600_cs_common_vline_parse()
866 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) { in r600_cs_common_vline_parse()
871 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) { in r600_cs_common_vline_parse()
885 header = radeon_get_ib_value(p, h_idx); in r600_cs_common_vline_parse()
886 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); in r600_cs_common_vline_parse()
1026 track->sq_config = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1029 track->db_depth_control = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1041 track->db_depth_info = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1052 track->db_depth_info = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1057 track->db_depth_view = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
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Dradeon_vce.c461 offset = radeon_get_ib_value(p, lo); in radeon_vce_cs_reloc()
462 idx = radeon_get_ib_value(p, hi); in radeon_vce_cs_reloc()
548 uint32_t len = radeon_get_ib_value(p, p->idx); in radeon_vce_cs_parse()
549 uint32_t cmd = radeon_get_ib_value(p, p->idx + 1); in radeon_vce_cs_parse()
565 handle = radeon_get_ib_value(p, p->idx + 2); in radeon_vce_cs_parse()
584 *size = radeon_get_ib_value(p, p->idx + 8) * in radeon_vce_cs_parse()
585 radeon_get_ib_value(p, p->idx + 10) * in radeon_vce_cs_parse()
621 tmp = radeon_get_ib_value(p, p->idx + 4); in radeon_vce_cs_parse()
Dr300.c617 idx_value = radeon_get_ib_value(p, idx); in r300_packet0_check()
1173 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r300_packet3_check()
1184 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { in r300_packet3_check()
1188 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r300_packet3_check()
1199 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { in r300_packet3_check()
1203 track->vap_vf_cntl = radeon_get_ib_value(p, idx); in r300_packet3_check()
1211 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r300_packet3_check()
1218 track->vap_vf_cntl = radeon_get_ib_value(p, idx); in r300_packet3_check()
1225 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r300_packet3_check()
1232 track->vap_vf_cntl = radeon_get_ib_value(p, idx); in r300_packet3_check()
Dr100.c1278 value = radeon_get_ib_value(p, idx); in r100_reloc_pitch_offset()
1314 c = radeon_get_ib_value(p, idx++) & 0x1F; in r100_packet3_load_vbpntr()
1330 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
1331 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1343 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1356 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
1357 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1448 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { in r100_cs_packet_parse_vline()
1462 header = radeon_get_ib_value(p, h_idx); in r100_cs_packet_parse_vline()
1463 crtc_id = radeon_get_ib_value(p, h_idx + 5); in r100_cs_packet_parse_vline()
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Dradeon_cs.c727 header = radeon_get_ib_value(p, idx); in radeon_cs_packet_parse()
763 printk("\t0x%08x <---\n", radeon_get_ib_value(p, i)); in radeon_cs_packet_parse()
765 printk("\t0x%08x\n", radeon_get_ib_value(p, i)); in radeon_cs_packet_parse()
848 idx = radeon_get_ib_value(p, p3reloc.idx + 1); in radeon_cs_packet_next_reloc()
Dradeon_uvd.c539 offset = radeon_get_ib_value(p, data0); in radeon_uvd_cs_reloc()
540 idx = radeon_get_ib_value(p, data1); in radeon_uvd_cs_reloc()
555 cmd = radeon_get_ib_value(p, p->idx) >> 1; in radeon_uvd_cs_reloc()
Dr200.c161 idx_value = radeon_get_ib_value(p, idx); in r200_packet0_check()
Dradeon.h1101 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) in radeon_get_ib_value() function