Searched refs:rG0 (Results 1 – 2 of 2) sorted by relevance
| /linux-4.1.27/arch/powerpc/crypto/ |
| D | aes-spe-modes.S | 72 stw rG0,112(r1); /* save 32 bit registers */ \
79 lwz rG0,112(r1); /* restore 32 bit registers */ \
521 ENDIAN_SWAP(rG0, rG1, rI0, rI1)
548 GF128_MUL(rG0, rG1, rG2, rG3, rW0)
549 ENDIAN_SWAP(rI0, rI1, rG0, rG1)
591 ENDIAN_SWAP(rG0, rG1, rI0, rI1)
618 GF128_MUL(rG0, rG1, rG2, rG3, rW0)
619 ENDIAN_SWAP(rI0, rI1, rG0, rG1)
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| D | aes-spe-regs.h | 39 #define rG0 r28 /* endian reversed tweak (XTS mode) */ macro
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