| /linux-4.1.27/include/linux/ |
| H A D | prefetch.h | 28 prefetch(x) - prefetches the cacheline at "x" for read
29 prefetchw(x) - prefetches the cacheline at "x" for write
30 spin_lock_prefetch(x) - prefetches the spinlock *x for taking
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| /linux-4.1.27/arch/sh/lib64/ |
| H A D | copy_page.S | 22 prefetches for the same cache set, so it's better to have the numbers
34 Do prefetches 4 lines ahead.
65 because they overlap with the time spent waiting for prefetches to
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| H A D | copy_user_memcpy.S | 50 * erratum. The first two prefetches are nop-ed out to avoid upsetting the
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| /linux-4.1.27/arch/alpha/lib/ |
| H A D | ev6-copy_page.S | 39 The solution is to schedule the prefetches to avoid the memory
40 conflicts. I schedule the wh64 prefetches farther ahead of the
41 read prefetches to avoid this problem.
52 further by unrolling the loop and doing multiple prefetches per cycle.
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| /linux-4.1.27/drivers/md/persistent-data/ |
| H A D | dm-transaction-manager.c | 98 struct prefetch_set prefetches; member in struct:dm_transaction_manager
179 prefetch_init(&tm->prefetches); dm_tm_create()
336 prefetch_add(&tm->real->prefetches, b); dm_tm_read_lock()
389 prefetch_issue(&tm->prefetches, tm->bm); dm_tm_issue_prefetches()
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| /linux-4.1.27/arch/sparc/include/asm/ |
| H A D | processor_64.h | 232 * prefetches into the prefetch-cache which only is accessible prefetch()
234 * By contrast, "#one_write" prefetches into the L2 cache prefetch()
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| /linux-4.1.27/drivers/md/ |
| H A D | dm-thin-metadata.h | 215 * Issue any prefetches that may be useful.
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| H A D | dm-verity.c | 544 * fills them. Then it issues prefetches and the I/O.
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| /linux-4.1.27/arch/mips/include/asm/octeon/ |
| H A D | cvmx-asm.h | 113 /* complete prefetches, invalidate entire dcache */
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| /linux-4.1.27/drivers/crypto/ |
| H A D | padlock-aes.c | 211 * Padlock prefetches extra data so we must provide mapped input buffers. ecb_crypt_copy()
225 * Padlock prefetches extra data so we must provide mapped input buffers. cbc_crypt_copy()
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| /linux-4.1.27/arch/powerpc/platforms/cell/ |
| H A D | ras.c | 138 * page, in order to avoid prefetches in memcpy and similar cbe_ptcal_enable_on_node()
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| /linux-4.1.27/arch/ia64/lib/ |
| H A D | copy_page_mck.S | 31 * the prefetches. The four relevant points in the pipelined are called A, B, C, D:
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| /linux-4.1.27/arch/x86/kernel/ |
| H A D | amd_gart_64.c | 813 * automatic prefetches from the CPU allocating cache lines in gart_iommu_init()
841 * Any prefetches that hit unmapped entries won't get an bus abort gart_iommu_init()
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| /linux-4.1.27/arch/tile/lib/ |
| H A D | memcpy_32.S | 246 * prefetch that line more than once, or subsequent prefetches
406 /* Kick off two prefetches, but don't go past the end. */
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| /linux-4.1.27/arch/powerpc/perf/ |
| H A D | power8-pmu.c | 37 /* L1 cache data prefetches */
55 /* Total HW L3 prefetches(Load+store) */
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| /linux-4.1.27/arch/powerpc/platforms/powermac/ |
| H A D | sleep.S | 178 /* Flush any pending L2 data prefetches to work around HW bug */
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| /linux-4.1.27/arch/sparc/lib/ |
| H A D | U3memcpy.S | 69 * 3) This code never prefetches cachelines past the end
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| /linux-4.1.27/arch/sparc/mm/ |
| H A D | fault_64.c | 372 * have to avoid prefetches which also have bit 21 set. do_sparc64_fault()
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| /linux-4.1.27/arch/mips/mm/ |
| H A D | uasm.c | 346 * As per erratum Core-14449, replace prefetches 0-4, I_u3u1u2()
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| /linux-4.1.27/drivers/infiniband/hw/mlx5/ |
| H A D | odp.c | 621 * prefetches more pages. The second operation cannot use the pfault mlx5_ib_mr_rdma_pfault_handler()
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| /linux-4.1.27/arch/arm/mm/ |
| H A D | dma-mapping.c | 51 * speculative prefetches. We model our approach on the assumption that
52 * the CPU does do speculative prefetches, which means we clean caches
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| /linux-4.1.27/arch/x86/include/asm/ |
| H A D | processor.h | 804 * It's not worth to care about 3dnow prefetches for the K6
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| /linux-4.1.27/arch/mips/cavium-octeon/executive/ |
| H A D | cvmx-l2c.c | 646 * Make sure core is quiet (no prefetches, etc.) before __read_l2_tag()
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| /linux-4.1.27/arch/parisc/kernel/ |
| H A D | perf_images.h | 1570 * or not, but does *not* include I-cache prefetches, which are generated by
1579 * should be between 1 and 2. If it is close to 1, most prefetches are
1580 * eventually called for by the IFU; if it is close to 2, almost no prefetches
3093 * prefetches).
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| /linux-4.1.27/arch/sh/kernel/cpu/sh5/ |
| H A D | entry.S | 960 /* Do prefetches */
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| /linux-4.1.27/arch/ia64/hp/common/ |
| H A D | sba_iommu.c | 80 ** If a device prefetches beyond the end of a valid pdir entry, it will cause
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| /linux-4.1.27/tools/perf/util/ |
| H A D | evsel.c | 385 { "prefetch", "prefetches", "speculative-read", "speculative-load", },
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| /linux-4.1.27/drivers/net/wireless/ath/ath9k/ |
| H A D | hw.c | 1163 * set AHB_MODE not to do cacheline prefetches ath9k_hw_set_dma()
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| /linux-4.1.27/drivers/gpu/drm/i915/ |
| H A D | i915_gem_gtt.c | 2022 * There are a number of places where the hardware apparently prefetches i915_gem_setup_global_gtt()
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| /linux-4.1.27/arch/x86/kernel/cpu/ |
| H A D | perf_event_intel.c | 442 * - prefetches are not included in the counts because they are not
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| /linux-4.1.27/drivers/scsi/ |
| H A D | ncr53c8xx.c | 1787 ** between CPU and 53c720 does prefetches, which causes
3400 ** between CPU and 53c720 does prefetches, which causes
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| /linux-4.1.27/drivers/net/ethernet/chelsio/cxgb3/ |
| H A D | sge.c | 1827 * receive handler. Batches need to be of modest size as we do prefetches
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