Searched refs:ppll (Results 1 - 5 of 5) sorted by relevance
| /linux-4.1.27/drivers/clk/samsung/ |
| H A D | clk-exynos5440.c | 41 FRATE(0, "ppll", NULL, CLK_IS_ROOT, 1000000000),
50 FFACTOR(0, "div250", "ppll", 1, 4, 0),
51 FFACTOR(0, "div200", "ppll", 1, 5, 0),
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| /linux-4.1.27/arch/arm/mach-imx/ |
| H A D | clk-imx35.c | 50 static const char *std_sel[] = {"ppll", "arm"};
54 ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg, enumerator in enum:mx35_clks
93 clk[ppll] = imx_clk_pllv1("ppll", "ckih", base + MX35_CCM_PPCTL); mx35_clocks_init()
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| /linux-4.1.27/drivers/gpu/drm/radeon/ |
| H A D | radeon_encoders.c | 55 /* DVO requires 2x ppll clocks depending on tmds chip */ radeon_encoder_clones()
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| H A D | atombios_crtc.c | 2172 /* disable the ppll */ atombios_crtc_disable()
2177 /* disable the ppll */ atombios_crtc_disable()
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| H A D | atombios.h | 1783 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
1784 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
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