Searched refs:postdiv2 (Results 1 – 3 of 3) sorted by relevance
| /linux-4.1.27/drivers/clk/pistachio/ |
| D | clk-pll.c | 177 (params->postdiv2 << PLL_FRAC_CTRL2_POSTDIV2_SHIFT); in pll_gf40lp_frac_set_rate()
193 u32 val, prediv, fbdiv, frac, postdiv1, postdiv2; in pll_gf40lp_frac_recalc_rate() local
203 postdiv2 = (val >> PLL_FRAC_CTRL2_POSTDIV2_SHIFT) & in pll_gf40lp_frac_recalc_rate()
208 rate = do_div_round_closest(rate, (prediv * postdiv1 * postdiv2) << 24); in pll_gf40lp_frac_recalc_rate()
287 (params->postdiv2 << PLL_INT_CTRL1_POSTDIV2_SHIFT); in pll_gf40lp_laint_set_rate()
303 u32 val, prediv, fbdiv, postdiv1, postdiv2; in pll_gf40lp_laint_recalc_rate() local
311 postdiv2 = (val >> PLL_INT_CTRL1_POSTDIV2_SHIFT) & in pll_gf40lp_laint_recalc_rate()
315 rate = do_div_round_closest(rate, prediv * postdiv1 * postdiv2); in pll_gf40lp_laint_recalc_rate()
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| D | clk.h | 103 unsigned int postdiv2; member
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| /linux-4.1.27/arch/mips/ar7/ |
| D | clock.c | 86 u32 postdiv2; member
275 int prediv, int postdiv, int postdiv2, int mul, u32 frequency) in tnetd7200_set_clock() argument
280 base, frequency, prediv, postdiv, postdiv2, mul); in tnetd7200_set_clock()
297 writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2); in tnetd7200_set_clock()
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