Searched refs:pm_readl (Results 1 - 3 of 3) sorted by relevance

/linux-4.1.27/arch/avr32/mach-at32ap/
H A Dclock.c264 seq_printf(s, "MCCTRL = %8x\n", pm_readl(MCCTRL)); clk_show()
265 seq_printf(s, "CKSEL = %8x\n", pm_readl(CKSEL)); clk_show()
266 seq_printf(s, "CPUMASK = %8x\n", pm_readl(CPU_MASK)); clk_show()
267 seq_printf(s, "HSBMASK = %8x\n", pm_readl(HSB_MASK)); clk_show()
268 seq_printf(s, "PBAMASK = %8x\n", pm_readl(PBA_MASK)); clk_show()
269 seq_printf(s, "PBBMASK = %8x\n", pm_readl(PBB_MASK)); clk_show()
270 seq_printf(s, "PLL0 = %8x\n", pm_readl(PLL0)); clk_show()
271 seq_printf(s, "PLL1 = %8x\n", pm_readl(PLL1)); clk_show()
272 seq_printf(s, "IMR = %8x\n", pm_readl(IMR)); clk_show()
276 seq_printf(s, "GCCTRL%d = %8x\n", i, pm_readl(GCCTRL(i))); clk_show()
H A Dat32ap700x.c198 control = pm_readl(PLL0); pll0_get_rate()
209 ctrl = pm_readl(PLL1); pll1_mode()
223 status = pm_readl(ISR); pll1_mode()
242 control = pm_readl(PLL1); pll1_get_rate()
274 ctrl = pm_readl(PLL1); pll1_set_parent()
349 mask = pm_readl(CPU_MASK); cpu_clk_mode()
362 cksel = pm_readl(CKSEL); cpu_clk_get_rate()
375 control = pm_readl(CKSEL); cpu_clk_set_rate()
410 mask = pm_readl(HSB_MASK); hsb_clk_mode()
423 cksel = pm_readl(CKSEL); hsb_clk_get_rate()
436 mask = pm_readl(PBA_MASK); pba_clk_mode()
449 cksel = pm_readl(CKSEL); pba_clk_get_rate()
462 mask = pm_readl(PBB_MASK); pbb_clk_mode()
475 cksel = pm_readl(CKSEL); pbb_clk_get_rate()
517 control = pm_readl(GCCTRL(clk->index)); genclk_mode()
530 control = pm_readl(GCCTRL(clk->index)); genclk_get_rate()
543 control = pm_readl(GCCTRL(clk->index)); genclk_set_rate()
570 control = pm_readl(GCCTRL(clk->index)); genclk_set_parent()
597 control = pm_readl(GCCTRL(clk->index)); genclk_init_parent()
2289 if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) { setup_platform()
2297 if (pm_readl(PLL0) & PM_BIT(PLLOSC)) setup_platform()
2299 if (pm_readl(PLL1) & PM_BIT(PLLOSC)) setup_platform()
H A Dpm.h107 #define pm_readl(reg) \ macro

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