| /linux-4.1.27/Documentation/devicetree/bindings/clock/st/ |
| D | st,clkgen-pll.txt | 15 "st,clkgena-plls-c65"
16 "st,plls-c32-a1x-0", "st,clkgen-plls-c32"
17 "st,plls-c32-a1x-1", "st,clkgen-plls-c32"
18 "st,stih415-plls-c32-a9", "st,clkgen-plls-c32"
19 "st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
20 "st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
21 "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
22 "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
23 "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
24 "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
[all …]
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| D | st,clkgen.txt | 66 compatible = "st,clkgena-plls-c65";
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| /linux-4.1.27/arch/arm/boot/dts/ |
| D | stih415-clock.dtsi | 34 compatible = "st,clkgena-plls-c65";
92 compatible = "st,clkgena-plls-c65";
155 compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
167 compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
269 compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
281 compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
391 compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
403 compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
502 compatible = "st,stih415-plls-c32-a9", "st,clkgen-plls-c32";
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| D | stih407-clock.dtsi | 45 compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
99 compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
137 compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
146 compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
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| D | stih416-clock.dtsi | 35 compatible = "st,clkgena-plls-c65";
93 compatible = "st,clkgena-plls-c65";
157 compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
169 compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
271 compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
283 compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
393 compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
405 compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
505 compatible = "st,stih416-plls-c32-a9", "st,clkgen-plls-c32";
733 compatible = "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32";
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| D | stih410-clock.dtsi | 47 compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
101 compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
140 compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
149 compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
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| D | stih418-clock.dtsi | 47 compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
101 compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
140 compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
149 compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
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| /linux-4.1.27/Documentation/devicetree/bindings/clock/ |
| D | samsung,s3c2410-clock.txt | 27 The xti clock used as input for the plls is generated outside the SoC. It is
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| /linux-4.1.27/arch/arm/plat-samsung/include/plat/ |
| D | cpu-freq-core.h | 196 extern int s3c_plltab_register(struct cpufreq_frequency_table *plls,
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| /linux-4.1.27/drivers/cpufreq/ |
| D | s3c24xx-cpufreq.c | 651 int __init s3c_plltab_register(struct cpufreq_frequency_table *plls, in s3c_plltab_register() argument
661 memcpy(vals, plls, size); in s3c_plltab_register()
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| /linux-4.1.27/drivers/video/fbdev/intelfb/ |
| D | intelfbhw.c | 53 static struct pll_min_max plls[PLLS_MAX] = { variable
661 return plls[index].ref_clk * m / n / p; in calc_vclock3()
667 struct pll_min_max *pll = &plls[index]; in calc_vclock()
883 struct pll_min_max *pll = &plls[index]; in splitm()
904 struct pll_min_max *pll = &plls[index]; in splitp()
943 struct pll_min_max *pll = &plls[index]; in calc_pll_params()
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