Searched refs:pllcfg (Results 1 - 3 of 3) sorted by relevance
| /linux-4.1.27/arch/arm/mach-lpc32xx/ |
| H A D | clock.c | 210 struct clk_pll_setup pllcfg; clk_get_pllrate_from_reg() local
212 pllcfg.cco_bypass_b15 = 0; clk_get_pllrate_from_reg()
213 pllcfg.direct_output_b14 = 0; clk_get_pllrate_from_reg()
214 pllcfg.fdbk_div_ctrl_b13 = 0; clk_get_pllrate_from_reg()
216 pllcfg.cco_bypass_b15 = 1; clk_get_pllrate_from_reg()
218 pllcfg.direct_output_b14 = 1; clk_get_pllrate_from_reg()
220 pllcfg.fdbk_div_ctrl_b13 = 1; clk_get_pllrate_from_reg()
221 pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF); clk_get_pllrate_from_reg()
222 pllcfg.pll_n = 1 + ((regval >> 9) & 0x3); clk_get_pllrate_from_reg()
223 pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)]; clk_get_pllrate_from_reg()
225 return clk_check_pll_setup(inputclk, &pllcfg); clk_get_pllrate_from_reg()
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| /linux-4.1.27/drivers/tty/serial/ |
| H A D | max310x.c | 532 unsigned int div, clksrc, pllcfg = 0; max310x_set_ref_clk() local
547 pllcfg = (0 << 6) | div; max310x_set_ref_clk()
554 pllcfg = (1 << 6) | div; max310x_set_ref_clk()
561 pllcfg = (2 << 6) | div; max310x_set_ref_clk()
568 pllcfg = (3 << 6) | div; max310x_set_ref_clk()
577 if (pllcfg) { max310x_set_ref_clk()
579 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); max310x_set_ref_clk()
586 if (pllcfg && xtal) max310x_set_ref_clk()
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| /linux-4.1.27/drivers/crypto/ |
| H A D | hifn_795x.c | 976 u32 pllcfg; hifn_init_pll() local
978 pllcfg = HIFN_1_PLL | HIFN_PLL_RESERVED_1; hifn_init_pll()
981 pllcfg |= HIFN_PLL_REF_CLK_PLL; hifn_init_pll()
983 pllcfg |= HIFN_PLL_REF_CLK_HBI; hifn_init_pll()
996 pllcfg |= (m / 2 - 1) << HIFN_PLL_ND_SHIFT; hifn_init_pll()
998 pllcfg |= HIFN_PLL_IS_1_8; hifn_init_pll()
1000 pllcfg |= HIFN_PLL_IS_9_12; hifn_init_pll()
1003 hifn_write_1(dev, HIFN_1_PLL, pllcfg | hifn_init_pll()
1010 hifn_write_1(dev, HIFN_1_PLL, pllcfg | hifn_init_pll()
1014 hifn_write_1(dev, HIFN_1_PLL, pllcfg | hifn_init_pll()
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