Searched refs:pll_base (Results 1 - 6 of 6) sorted by relevance

/linux-4.1.27/arch/arm/mach-imx/
H A Dclk-imx51-imx53.c321 void __iomem *pll_base; mx50_clocks_init() local
324 pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K); mx50_clocks_init()
325 WARN_ON(!pll_base); mx50_clocks_init()
326 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); mx50_clocks_init()
328 pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K); mx50_clocks_init()
329 WARN_ON(!pll_base); mx50_clocks_init()
330 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); mx50_clocks_init()
332 pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K); mx50_clocks_init()
333 WARN_ON(!pll_base); mx50_clocks_init()
334 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); mx50_clocks_init()
383 void __iomem *pll_base; mx51_clocks_init() local
386 pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K); mx51_clocks_init()
387 WARN_ON(!pll_base); mx51_clocks_init()
388 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); mx51_clocks_init()
390 pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K); mx51_clocks_init()
391 WARN_ON(!pll_base); mx51_clocks_init()
392 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); mx51_clocks_init()
394 pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K); mx51_clocks_init()
395 WARN_ON(!pll_base); mx51_clocks_init()
396 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); mx51_clocks_init()
472 void __iomem *pll_base; mx53_clocks_init() local
475 pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K); mx53_clocks_init()
476 WARN_ON(!pll_base); mx53_clocks_init()
477 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); mx53_clocks_init()
479 pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K); mx53_clocks_init()
480 WARN_ON(!pll_base); mx53_clocks_init()
481 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); mx53_clocks_init()
483 pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K); mx53_clocks_init()
484 WARN_ON(!pll_base); mx53_clocks_init()
485 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); mx53_clocks_init()
487 pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K); mx53_clocks_init()
488 WARN_ON(!pll_base); mx53_clocks_init()
489 clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", pll_base); mx53_clocks_init()
/linux-4.1.27/drivers/video/fbdev/omap2/dss/
H A Dvideo-pll.c140 void __iomem *pll_base, *clkctrl_base; dss_video_pll_init() local
154 pll_base = devm_ioremap_resource(&pdev->dev, res); dss_video_pll_init()
155 if (IS_ERR(pll_base)) { dss_video_pll_init()
157 return ERR_CAST(pll_base); dss_video_pll_init()
197 pll->base = pll_base; dss_video_pll_init()
H A Ddsi.c304 void __iomem *pll_base; member in struct:dsi_data
450 case DSI_PLL: base = dsi->pll_base; break; dsi_write_reg()
466 case DSI_PLL: base = dsi->pll_base; break; dsi_read_reg()
5243 pll->base = dsi->pll_base; dsi_init_pll_data()
5369 dsi->pll_base = devm_ioremap(&dsidev->dev, res->start, omap_dsihw_probe()
/linux-4.1.27/drivers/clk/st/
H A Dclkgen-pll.c645 void __iomem *pll_base; clkgen_c32_pll_setup() local
662 pll_base = clkgen_get_register_base(np); clkgen_c32_pll_setup()
663 if (!pll_base) clkgen_c32_pll_setup()
666 clk = clkgen_pll_register(parent_name, data, pll_base, np->name); clkgen_c32_pll_setup()
693 clk = clkgen_odf_register(pll_name, pll_base, data, clkgen_c32_pll_setup()
/linux-4.1.27/arch/arm/mach-tegra/
H A Dsleep-tegra30.S99 .macro pll_enable, rd, r_car_base, pll_base, pll_misc
100 ldr \rd, [\r_car_base, #\pll_base]
103 streq \rd, [\r_car_base, #\pll_base]
116 .macro pll_locked, rd, r_car_base, pll_base
118 ldr \rd, [\r_car_base, #\pll_base]
H A Dsleep-tegra20.S56 .macro pll_enable, rd, r_car_base, pll_base
57 ldr \rd, [\r_car_base, #\pll_base]
60 streq \rd, [\r_car_base, #\pll_base]

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