Searched refs:pin_reg (Results 1 - 2 of 2) sorted by relevance
| /linux-4.1.27/drivers/pinctrl/ |
| H A D | pinctrl-amd.c | 46 u32 pin_reg; amd_gpio_direction_input() local
50 pin_reg = readl(gpio_dev->base + offset * 4); amd_gpio_direction_input()
55 if ((pin_reg & DB_TMR_OUT_MASK) == 0) { amd_gpio_direction_input()
56 pin_reg |= 0xf; amd_gpio_direction_input()
57 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); amd_gpio_direction_input()
58 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; amd_gpio_direction_input()
59 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); amd_gpio_direction_input()
62 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); amd_gpio_direction_input()
63 writel(pin_reg, gpio_dev->base + offset * 4); amd_gpio_direction_input()
72 u32 pin_reg; amd_gpio_direction_output() local
77 pin_reg = readl(gpio_dev->base + offset * 4); amd_gpio_direction_output()
78 pin_reg |= BIT(OUTPUT_ENABLE_OFF); amd_gpio_direction_output()
80 pin_reg |= BIT(OUTPUT_VALUE_OFF); amd_gpio_direction_output()
82 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); amd_gpio_direction_output()
83 writel(pin_reg, gpio_dev->base + offset * 4); amd_gpio_direction_output()
91 u32 pin_reg; amd_gpio_get_value() local
96 pin_reg = readl(gpio_dev->base + offset * 4); amd_gpio_get_value()
99 return !!(pin_reg & BIT(PIN_STS_OFF)); amd_gpio_get_value()
104 u32 pin_reg; amd_gpio_set_value() local
109 pin_reg = readl(gpio_dev->base + offset * 4); amd_gpio_set_value()
111 pin_reg |= BIT(OUTPUT_VALUE_OFF); amd_gpio_set_value()
113 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); amd_gpio_set_value()
114 writel(pin_reg, gpio_dev->base + offset * 4); amd_gpio_set_value()
122 u32 pin_reg; amd_gpio_set_debounce() local
128 pin_reg = readl(gpio_dev->base + offset * 4); amd_gpio_set_debounce()
131 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; amd_gpio_set_debounce()
132 pin_reg &= ~DB_TMR_OUT_MASK; amd_gpio_set_debounce()
144 pin_reg |= 1; amd_gpio_set_debounce()
145 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); amd_gpio_set_debounce()
146 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); amd_gpio_set_debounce()
149 pin_reg |= time & DB_TMR_OUT_MASK; amd_gpio_set_debounce()
150 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); amd_gpio_set_debounce()
151 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); amd_gpio_set_debounce()
154 pin_reg |= time & DB_TMR_OUT_MASK; amd_gpio_set_debounce()
155 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); amd_gpio_set_debounce()
156 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); amd_gpio_set_debounce()
159 pin_reg |= time & DB_TMR_OUT_MASK; amd_gpio_set_debounce()
160 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); amd_gpio_set_debounce()
161 pin_reg |= BIT(DB_TMR_LARGE_OFF); amd_gpio_set_debounce()
164 pin_reg |= time & DB_TMR_OUT_MASK; amd_gpio_set_debounce()
165 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); amd_gpio_set_debounce()
166 pin_reg |= BIT(DB_TMR_LARGE_OFF); amd_gpio_set_debounce()
168 pin_reg &= ~DB_CNTRl_MASK; amd_gpio_set_debounce()
172 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); amd_gpio_set_debounce()
173 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); amd_gpio_set_debounce()
174 pin_reg &= ~DB_TMR_OUT_MASK; amd_gpio_set_debounce()
175 pin_reg &= ~DB_CNTRl_MASK; amd_gpio_set_debounce()
177 writel(pin_reg, gpio_dev->base + offset * 4); amd_gpio_set_debounce()
186 u32 pin_reg; amd_gpio_dbg_show() local
226 pin_reg = readl(gpio_dev->base + i * 4); amd_gpio_dbg_show()
229 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { amd_gpio_dbg_show()
232 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) amd_gpio_dbg_show()
233 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1))) amd_gpio_dbg_show()
235 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) amd_gpio_dbg_show()
236 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1))) amd_gpio_dbg_show()
238 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) amd_gpio_dbg_show()
239 && pin_reg & BIT(ACTIVE_LEVEL_OFF+1)) amd_gpio_dbg_show()
244 if (pin_reg & BIT(LEVEL_TRIG_OFF)) amd_gpio_dbg_show()
256 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) amd_gpio_dbg_show()
263 if (pin_reg & BIT(WAKE_CNTRL_OFF)) amd_gpio_dbg_show()
268 if (pin_reg & BIT(WAKE_CNTRL_OFF)) amd_gpio_dbg_show()
273 if (pin_reg & BIT(WAKE_CNTRL_OFF)) amd_gpio_dbg_show()
278 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { amd_gpio_dbg_show()
280 if (pin_reg & BIT(PULL_UP_SEL_OFF)) amd_gpio_dbg_show()
289 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) amd_gpio_dbg_show()
294 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { amd_gpio_dbg_show()
297 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) amd_gpio_dbg_show()
305 if (pin_reg & BIT(PIN_STS_OFF)) amd_gpio_dbg_show()
317 output_value, output_enable, pin_reg); amd_gpio_dbg_show()
327 u32 pin_reg; amd_gpio_irq_enable() local
333 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); amd_gpio_irq_enable()
338 if ((pin_reg & DB_TMR_OUT_MASK) == 0) { amd_gpio_irq_enable()
339 pin_reg |= 0xf; amd_gpio_irq_enable()
340 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); amd_gpio_irq_enable()
341 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); amd_gpio_irq_enable()
343 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); amd_gpio_irq_enable()
344 pin_reg |= BIT(INTERRUPT_MASK_OFF); amd_gpio_irq_enable()
345 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); amd_gpio_irq_enable()
351 u32 pin_reg; amd_gpio_irq_disable() local
357 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); amd_gpio_irq_disable()
358 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); amd_gpio_irq_disable()
359 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); amd_gpio_irq_disable()
360 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); amd_gpio_irq_disable()
366 u32 pin_reg; amd_gpio_irq_mask() local
372 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); amd_gpio_irq_mask()
373 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); amd_gpio_irq_mask()
374 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); amd_gpio_irq_mask()
380 u32 pin_reg; amd_gpio_irq_unmask() local
386 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); amd_gpio_irq_unmask()
387 pin_reg |= BIT(INTERRUPT_MASK_OFF); amd_gpio_irq_unmask()
388 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); amd_gpio_irq_unmask()
409 u32 pin_reg; amd_gpio_irq_set_type() local
415 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); amd_gpio_irq_set_type()
419 pin_reg &= ~BIT(LEVEL_TRIG_OFF); amd_gpio_irq_set_type()
420 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); amd_gpio_irq_set_type()
421 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; amd_gpio_irq_set_type()
422 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; amd_gpio_irq_set_type()
427 pin_reg &= ~BIT(LEVEL_TRIG_OFF); amd_gpio_irq_set_type()
428 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); amd_gpio_irq_set_type()
429 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; amd_gpio_irq_set_type()
430 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; amd_gpio_irq_set_type()
435 pin_reg &= ~BIT(LEVEL_TRIG_OFF); amd_gpio_irq_set_type()
436 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); amd_gpio_irq_set_type()
437 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; amd_gpio_irq_set_type()
438 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; amd_gpio_irq_set_type()
443 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; amd_gpio_irq_set_type()
444 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); amd_gpio_irq_set_type()
445 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; amd_gpio_irq_set_type()
446 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); amd_gpio_irq_set_type()
447 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; amd_gpio_irq_set_type()
452 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; amd_gpio_irq_set_type()
453 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); amd_gpio_irq_set_type()
454 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; amd_gpio_irq_set_type()
455 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); amd_gpio_irq_set_type()
456 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; amd_gpio_irq_set_type()
468 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; amd_gpio_irq_set_type()
469 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); amd_gpio_irq_set_type()
500 u32 pin_reg; amd_gpio_irq_handler() local
526 pin_reg = readl(gpio_dev->base + amd_gpio_irq_handler()
528 if ((pin_reg & BIT(INTERRUPT_STS_OFF)) || amd_gpio_irq_handler()
529 (pin_reg & BIT(WAKE_STS_OFF))) { amd_gpio_irq_handler()
533 writel(pin_reg, amd_gpio_irq_handler()
595 u32 pin_reg; amd_pinconf_get() local
602 pin_reg = readl(gpio_dev->base + pin*4); amd_pinconf_get()
606 arg = pin_reg & DB_TMR_OUT_MASK; amd_pinconf_get()
610 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); amd_pinconf_get()
614 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); amd_pinconf_get()
618 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; amd_pinconf_get()
638 u32 pin_reg; amd_pinconf_set() local
647 pin_reg = readl(gpio_dev->base + pin*4); amd_pinconf_set()
651 pin_reg &= ~DB_TMR_OUT_MASK; amd_pinconf_set()
652 pin_reg |= arg & DB_TMR_OUT_MASK; amd_pinconf_set()
656 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); amd_pinconf_set()
657 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; amd_pinconf_set()
661 pin_reg &= ~BIT(PULL_UP_SEL_OFF); amd_pinconf_set()
662 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; amd_pinconf_set()
663 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); amd_pinconf_set()
664 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; amd_pinconf_set()
668 pin_reg &= ~(DRV_STRENGTH_SEL_MASK amd_pinconf_set()
670 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) amd_pinconf_set()
680 writel(pin_reg, gpio_dev->base + pin*4); amd_pinconf_set()
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| /linux-4.1.27/drivers/pinctrl/freescale/ |
| H A D | pinctrl-imx.c | 187 const struct imx_pin_reg *pin_reg; imx_pmx_set() local
205 pin_reg = &info->pin_regs[pin_id]; imx_pmx_set()
207 if (pin_reg->mux_reg == -1) { imx_pmx_set()
215 reg = readl(ipctl->base + pin_reg->mux_reg); imx_pmx_set()
218 writel(reg, ipctl->base + pin_reg->mux_reg); imx_pmx_set()
220 writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); imx_pmx_set()
223 pin_reg->mux_reg, pin->mux_mode); imx_pmx_set()
302 const struct imx_pin_reg *pin_reg; imx_pmx_gpio_request_enable() local
312 pin_reg = &info->pin_regs[offset]; imx_pmx_gpio_request_enable()
313 if (pin_reg->mux_reg == -1) imx_pmx_gpio_request_enable()
329 reg = readl(ipctl->base + pin_reg->mux_reg); imx_pmx_gpio_request_enable()
332 writel(reg, ipctl->base + pin_reg->mux_reg); imx_pmx_gpio_request_enable()
342 const struct imx_pin_reg *pin_reg; imx_pmx_gpio_set_direction() local
352 pin_reg = &info->pin_regs[offset]; imx_pmx_gpio_set_direction()
353 if (pin_reg->mux_reg == -1) imx_pmx_gpio_set_direction()
357 reg = readl(ipctl->base + pin_reg->mux_reg); imx_pmx_gpio_set_direction()
362 writel(reg, ipctl->base + pin_reg->mux_reg); imx_pmx_gpio_set_direction()
381 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; imx_pinconf_get() local
383 if (pin_reg->conf_reg == -1) { imx_pinconf_get()
389 *config = readl(ipctl->base + pin_reg->conf_reg); imx_pinconf_get()
403 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; imx_pinconf_set() local
406 if (pin_reg->conf_reg == -1) { imx_pinconf_set()
418 reg = readl(ipctl->base + pin_reg->conf_reg); imx_pinconf_set()
421 writel(reg, ipctl->base + pin_reg->conf_reg); imx_pinconf_set()
423 writel(configs[i], ipctl->base + pin_reg->conf_reg); imx_pinconf_set()
426 pin_reg->conf_reg, configs[i]); imx_pinconf_set()
437 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; imx_pinconf_dbg_show() local
440 if (!pin_reg || pin_reg->conf_reg == -1) { imx_pinconf_dbg_show()
445 config = readl(ipctl->base + pin_reg->conf_reg); imx_pinconf_dbg_show()
542 struct imx_pin_reg *pin_reg; imx_pinctrl_parse_groups() local
554 pin_reg = &info->pin_regs[pin_id]; imx_pinctrl_parse_groups()
557 pin_reg->mux_reg = mux_reg; imx_pinctrl_parse_groups()
558 pin_reg->conf_reg = conf_reg; imx_pinctrl_parse_groups()
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