Searched refs:pbl_addr (Results 1 - 11 of 11) sorted by relevance

/linux-4.1.27/drivers/infiniband/hw/cxgb3/
H A Diwch_mem.c68 mhp->attr.pbl_size, mhp->attr.pbl_addr)) iwch_register_mem()
74 mhp->attr.pbl_addr); iwch_register_mem()
98 mhp->attr.pbl_size, mhp->attr.pbl_addr)) iwch_reregister_mem()
104 mhp->attr.pbl_addr); iwch_reregister_mem()
111 mhp->attr.pbl_addr = cxio_hal_pblpool_alloc(&mhp->rhp->rdev, iwch_alloc_pbl()
114 if (!mhp->attr.pbl_addr) iwch_alloc_pbl()
124 cxio_hal_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, iwch_free_pbl()
131 mhp->attr.pbl_addr + (offset << 3), npages); iwch_write_pbl()
H A Dcxio_hal.h171 u32 pbl_addr, u32 pbl_size);
174 u8 page_size, u32 pbl_size, u32 pbl_addr);
177 u8 page_size, u32 pbl_size, u32 pbl_addr);
179 u32 pbl_addr);
181 int cxio_allocate_stag(struct cxio_rdev *rdev, u32 *stag, u32 pdid, u32 pbl_size, u32 pbl_addr);
204 void cxio_dump_pbl(struct cxio_rdev *rev, u32 pbl_addr, uint len, u8 shift);
H A Diwch_qp.c201 u32 num_sgle, u32 * pbl_addr, u8 * page_size) iwch_sgl2pbl_map()
239 pbl_addr[i] = ((mhp->attr.pbl_addr - iwch_sgl2pbl_map()
251 u32 pbl_addr[T3_MAX_SGE]; build_rdma_recv() local
254 err = iwch_sgl2pbl_map(qhp->rhp, wr->sg_list, wr->num_sge, pbl_addr, build_rdma_recv()
271 /* pbl_addr is the adapters address in the PBL */ build_rdma_recv()
272 wqe->recv.pbl_addr[i] = cpu_to_be32(pbl_addr[i]); build_rdma_recv()
278 wqe->recv.pbl_addr[i] = 0; build_rdma_recv()
283 qhp->wq.rq_size_log2)].pbl_addr = 0; build_rdma_recv()
291 u32 pbl_addr; build_zero_stag_recv() local
301 pbl_addr = cxio_hal_pblpool_alloc(&qhp->rhp->rdev, T3_STAG0_PBL_SIZE); build_zero_stag_recv()
302 if (!pbl_addr) build_zero_stag_recv()
308 pbl_offset = (pbl_addr - qhp->rhp->rdev.rnic_info.pbl_base) >> 3; build_zero_stag_recv()
333 wqe->recv.pbl_addr[i] = cpu_to_be32(pbl_offset); build_zero_stag_recv()
341 wqe->recv.pbl_addr[i] = 0; build_zero_stag_recv()
346 qhp->wq.rq_size_log2)].pbl_addr = pbl_addr; build_zero_stag_recv()
536 u32 pbl_addr; iwch_bind_mw() local
583 err = iwch_sgl2pbl_map(rhp, &sgl, 1, &pbl_addr, &page_size); iwch_bind_mw()
595 wqe->bind.mr_pbl_addr = cpu_to_be32(pbl_addr); iwch_bind_mw()
200 iwch_sgl2pbl_map(struct iwch_dev *rhp, struct ib_sge *sg_list, u32 num_sgle, u32 * pbl_addr, u8 * page_size) iwch_sgl2pbl_map() argument
H A Dcxio_dbg.c73 void cxio_dump_pbl(struct cxio_rdev *rdev, u32 pbl_addr, uint len, u8 shift) cxio_dump_pbl() argument
90 m->addr = pbl_addr; cxio_dump_pbl()
H A Dcxio_hal.c693 /* IN: stag key, pdid, perm, zbva, to, len, page_size, pbl_size and pbl_addr
701 u32 pbl_size, u32 pbl_addr) __cxio_tpt_op()
738 tpt.rsvd_pbl_addr = cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, pbl_addr)>>3)); __cxio_tpt_op()
765 u32 pbl_addr, u32 pbl_size) cxio_write_pbl()
771 __func__, pbl_addr, rdev_p->rnic_info.pbl_base, cxio_write_pbl()
775 err = cxio_hal_ctrl_qp_write_mem(rdev_p, pbl_addr >> 5, pbl_size << 3, cxio_write_pbl()
792 u8 page_size, u32 pbl_size, u32 pbl_addr) cxio_register_phys_mem()
796 zbva, to, len, page_size, pbl_size, pbl_addr); cxio_register_phys_mem()
801 u8 page_size, u32 pbl_size, u32 pbl_addr) cxio_reregister_phys_mem()
804 zbva, to, len, page_size, pbl_size, pbl_addr); cxio_reregister_phys_mem()
808 u32 pbl_addr) cxio_dereg_mem()
811 pbl_size, pbl_addr); cxio_dereg_mem()
827 int cxio_allocate_stag(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid, u32 pbl_size, u32 pbl_addr) cxio_allocate_stag() argument
831 0, 0, 0ULL, 0, 0, pbl_size, pbl_addr); cxio_allocate_stag()
1309 if (wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].pbl_addr) cxio_poll_cq()
1312 wq->rq_size_log2)].pbl_addr, T3_STAG0_PBL_SIZE); cxio_poll_cq()
697 __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry, u32 *stag, u8 stag_state, u32 pdid, enum tpt_mem_type type, enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len, u8 page_size, u32 pbl_size, u32 pbl_addr) __cxio_tpt_op() argument
764 cxio_write_pbl(struct cxio_rdev *rdev_p, __be64 *pbl, u32 pbl_addr, u32 pbl_size) cxio_write_pbl() argument
790 cxio_register_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid, enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len, u8 page_size, u32 pbl_size, u32 pbl_addr) cxio_register_phys_mem() argument
799 cxio_reregister_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid, enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len, u8 page_size, u32 pbl_size, u32 pbl_addr) cxio_reregister_phys_mem() argument
807 cxio_dereg_mem(struct cxio_rdev *rdev_p, u32 stag, u32 pbl_size, u32 pbl_addr) cxio_dereg_mem() argument
H A Diwch_user.h72 __u32 pbl_addr; member in struct:iwch_reg_user_mr_resp
H A Diwch_provider.c460 mhp->attr.pbl_addr); iwch_dereg_mr()
696 uresp.pbl_addr = (mhp->attr.pbl_addr - iwch_reg_user_mr()
698 PDBG("%s user resp pbl_addr 0x%x\n", __func__, iwch_reg_user_mr()
699 uresp.pbl_addr); iwch_reg_user_mr()
811 mhp->attr.pbl_size, mhp->attr.pbl_addr); iwch_alloc_fast_reg_mr()
827 mhp->attr.pbl_addr); iwch_alloc_fast_reg_mr()
H A Diwch_provider.h68 u32 pbl_addr; member in struct:tpt_attributes
H A Dcxio_wr.h275 __be32 pbl_addr[T3_MAX_SGE]; member in struct:t3_receive_wr
685 __u32 pbl_addr; member in struct:t3_swrq
/linux-4.1.27/drivers/infiniband/hw/cxgb4/
H A Dmem.c247 * pbl_size and pbl_addr
254 u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr) write_tpt_entry()
299 FW_RI_TPTE_PBLADDR_V(PBL_OFF(rdev, pbl_addr)>>3)); write_tpt_entry()
320 u32 pbl_addr, u32 pbl_size) write_pbl()
325 __func__, pbl_addr, rdev->lldi.vr->pbl.start, write_pbl()
328 err = write_adapter_mem(rdev, pbl_addr >> 5, pbl_size << 3, pbl); write_pbl()
333 u32 pbl_addr) dereg_mem()
336 pbl_size, pbl_addr); dereg_mem()
353 u32 pbl_size, u32 pbl_addr) allocate_stag()
357 0UL, 0, 0, pbl_size, pbl_addr); allocate_stag()
384 mhp->attr.pbl_size, mhp->attr.pbl_addr); register_mem()
391 mhp->attr.pbl_addr); register_mem()
409 mhp->attr.pbl_size, mhp->attr.pbl_addr); reregister_mem()
416 mhp->attr.pbl_addr); reregister_mem()
423 mhp->attr.pbl_addr = c4iw_pblpool_alloc(&mhp->rhp->rdev, alloc_pbl()
426 if (!mhp->attr.pbl_addr) alloc_pbl()
625 ret = write_pbl(&mhp->rhp->rdev, page_list, mhp->attr.pbl_addr, c4iw_register_phys_mem()
647 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, c4iw_register_phys_mem()
694 mhp->attr.pbl_addr); c4iw_get_dma_mr()
762 mhp->attr.pbl_addr + (n << 3), i); c4iw_reg_user_mr()
773 mhp->attr.pbl_addr + (n << 3), i); c4iw_reg_user_mr()
794 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, c4iw_reg_user_mr()
879 mhp->attr.pbl_size, mhp->attr.pbl_addr); c4iw_alloc_fast_reg_mr()
897 mhp->attr.pbl_addr); c4iw_alloc_fast_reg_mr()
899 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, c4iw_alloc_fast_reg_mr()
968 mhp->attr.pbl_addr); c4iw_dereg_mr()
970 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, c4iw_dereg_mr()
250 write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry, u32 *stag, u8 stag_state, u32 pdid, enum fw_ri_stag_type type, enum fw_ri_mem_perms perm, int bind_enabled, u32 zbva, u64 to, u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr) write_tpt_entry() argument
319 write_pbl(struct c4iw_rdev *rdev, __be64 *pbl, u32 pbl_addr, u32 pbl_size) write_pbl() argument
332 dereg_mem(struct c4iw_rdev *rdev, u32 stag, u32 pbl_size, u32 pbl_addr) dereg_mem() argument
352 allocate_stag(struct c4iw_rdev *rdev, u32 *stag, u32 pdid, u32 pbl_size, u32 pbl_addr) allocate_stag() argument
H A Diw_cxgb4.h374 u32 pbl_addr; member in struct:tpt_attributes

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