Searched refs:pPLL (Results 1 - 2 of 2) sorted by relevance

/linux-4.1.27/drivers/staging/sm750fb/
H A Dddk750_chip.c47 inline unsigned int calcPLL(pll_value_t *pPLL) calcPLL() argument
49 return (pPLL->inputFreq * pPLL->M / pPLL->N / twoToPowerOfx(pPLL->OD) / twoToPowerOfx(pPLL->POD)); calcPLL()
52 unsigned int getPllValue(clock_type_t clockType, pll_value_t *pPLL) getPllValue() argument
56 pPLL->inputFreq = DEFAULT_INPUT_CLOCK; getPllValue()
57 pPLL->clockType = clockType; getPllValue()
77 pPLL->M = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, M); getPllValue()
78 pPLL->N = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, N); getPllValue()
79 pPLL->OD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, OD); getPllValue()
80 pPLL->POD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, POD); getPllValue()
82 return calcPLL(pPLL); getPllValue()
497 pll_value_t *pPLL /* Structure to hold the value to be set in PLL */ calcPllValue2()
504 pPLL->M = 0; calcPllValue2()
505 pPLL->N = 0; calcPllValue2()
506 pPLL->OD = 0; calcPllValue2()
507 pPLL->POD = 0; calcPllValue2()
512 pPLL->inputFreq /= 1000; calcPllValue2()
523 if ((POD > 0) && (pPLL->clockType == MXCLK_PLL)) calcPllValue2()
549 M = ulRequestClk * N * odPower * 1000 / pPLL->inputFreq; calcPllValue2()
555 pllClk = pPLL->inputFreq * M / N / odPower / podPower; calcPllValue2()
564 pPLL->M = M; calcPllValue2()
565 pPLL->N = N; calcPllValue2()
566 pPLL->OD = OD; calcPllValue2()
575 pPLL->POD = POD; calcPllValue2()
583 // pPLL->inputFreq *= 1000; calcPllValue2()
585 pPLL->inputFreq = DEFAULT_INPUT_CLOCK; /* Default reference clock */ calcPllValue2()
589 //DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Input CLK = %dHz, M=%d, N=%d, OD=%d, POD=%d\n", pPLL->inputFreq, pPLL->M, pPLL->N, pPLL->OD, pPLL->POD)); calcPllValue2()
592 ret = calcPLL(pPLL); calcPllValue2()
600 unsigned int formatPllReg(pll_value_t *pPLL) formatPllReg() argument
613 | FIELD_VALUE(0, PANEL_PLL_CTRL, POD, pPLL->POD) formatPllReg()
615 | FIELD_VALUE(0, PANEL_PLL_CTRL, OD, pPLL->OD) formatPllReg()
616 | FIELD_VALUE(0, PANEL_PLL_CTRL, N, pPLL->N) formatPllReg()
617 | FIELD_VALUE(0, PANEL_PLL_CTRL, M, pPLL->M); formatPllReg()
H A Dddk750_chip.h76 unsigned int formatPllReg(pll_value_t *pPLL);
80 unsigned int getPllValue(clock_type_t clockType, pll_value_t *pPLL);

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