Searched refs:osc1 (Results 1 – 10 of 10) sorted by relevance
| /linux-4.1.27/drivers/video/fbdev/ |
| D | pmagb-b-fb.c | 42 unsigned int osc1; member
227 par->osc1 = freq1; in pmagbbfb_osc_setup()
233 par->osc1 = pmagbbfb_freqs[i]; in pmagbbfb_osc_setup()
237 if (par->osc0 - par->osc1 <= (par->osc0 + par->osc1 + 256) / 512 || in pmagbbfb_osc_setup()
238 par->osc1 - par->osc0 <= (par->osc0 + par->osc1 + 256) / 512) in pmagbbfb_osc_setup()
239 par->osc1 = 0; in pmagbbfb_osc_setup()
241 gp0_write(par, par->osc1 != 0); /* reselect OscX */ in pmagbbfb_osc_setup()
243 info->var.pixclock = par->osc1 ? in pmagbbfb_osc_setup()
244 (1000000000 + par->osc1 / 2) / par->osc1 : in pmagbbfb_osc_setup()
329 par->osc1 / 1000, par->osc1 % 1000); in pmagbbfb_probe()
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| /linux-4.1.27/arch/avr32/boards/favr-32/ |
| D | setup.c | 276 struct clk *osc1; in set_abdac_rate() local
283 osc1 = clk_get(NULL, "osc1"); in set_abdac_rate()
284 if (IS_ERR(osc1)) { in set_abdac_rate()
285 retval = PTR_ERR(osc1); in set_abdac_rate()
301 retval = clk_set_parent(pll1, osc1); in set_abdac_rate()
331 clk_put(osc1); in set_abdac_rate()
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| /linux-4.1.27/arch/arm/boot/dts/ |
| D | socfpga.dtsi | 119 osc1: osc1 { label
144 clocks = <&osc1>;
198 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
249 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
697 clocks = <&osc1>;
705 clocks = <&osc1>;
771 clocks = <&osc1>;
779 clocks = <&osc1>;
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| D | socfpga_arria10.dtsi | 101 osc1: osc1 { label
111 clocks = <&osc1>;
119 clocks = <&osc1>;
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| D | socfpga_arria5.dtsi | 26 osc1 {
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| D | socfpga_arria10_socdk.dts | 38 osc1 {
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| D | socfpga_cyclone5.dtsi | 27 osc1 {
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| D | versatile-ab.dts | 37 osc1: cm_aux_osc@24M { label
166 clocks = <&osc1>, <&pclk>;
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| D | socfpga_vt.dts | 38 osc1 {
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| /linux-4.1.27/arch/avr32/mach-at32ap/ |
| D | at32ap700x.c | 108 static struct clk osc1; variable
186 if (clk->parent == &osc1) in pll_set_rate()
279 else if (parent == &osc1) in pll1_set_parent()
306 static struct clk osc1 = { variable
572 if (parent == &osc1 || parent == &pll1) in genclk_set_parent()
599 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1; in genclk_init_parent()
2222 &osc1,
2298 pll0.parent = &osc1; in setup_platform()
2300 pll1.parent = &osc1; in setup_platform()
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