Searched refs:nx_pcibase (Results 1 – 8 of 8) sorted by relevance
362 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); in qla82xx_pci_set_crbwindow_2M()368 (CRB_WINDOW_2M + ha->nx_pcibase)); in qla82xx_pci_set_crbwindow_2M()375 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; in qla82xx_pci_set_crbwindow_2M()429 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; in qla82xx_pci_get_crb_addr_2M()442 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; in qla82xx_pci_get_crb_addr_2M()925 WRT_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase), in qla82xx_md_rw_32()929 RD_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); in qla82xx_md_rw_32()934 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase), in qla82xx_md_rw_32()938 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase)); in qla82xx_md_rw_32()1666 ha->nx_pcibase = in qla82xx_iospace_config()[all …]
22 return readl((void __iomem *) (ha->nx_pcibase + addr)); in qla8044_rd_reg()28 writel(val, (void __iomem *)((ha)->nx_pcibase + addr)); in qla8044_wr_reg()2570 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase)); in qla8044_minidump_process_rdocm()
2913 if (!ha->nx_pcibase) in qla2x00_probe_one()2914 iounmap((device_reg_t *)ha->nx_pcibase); in qla2x00_probe_one()3050 iounmap((device_reg_t *)ha->nx_pcibase); in qla2x00_unmap_iobases()
3423 unsigned long nx_pcibase; /* Base I/O address */ member
43 return (void __iomem *)(ha->nx_pcibase + off); in qla4_8xxx_pci_base_offsetfset()364 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); in qla4_82xx_pci_set_crbwindow_2M()368 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); in qla4_82xx_pci_set_crbwindow_2M()374 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; in qla4_82xx_pci_set_crbwindow_2M()432 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); in qla4_82xx_md_rd_32()438 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); in qla4_82xx_md_rd_32()447 ha->nx_pcibase)); in qla4_82xx_md_rd_32()458 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); in qla4_82xx_md_wr_32()463 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); in qla4_82xx_md_wr_32()472 ha->nx_pcibase)); in qla4_82xx_md_wr_32()[all …]
18 return readl((void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_rd_reg()23 writel(val, (void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_wr_reg()
739 unsigned long nx_pcibase; /* Base I/O address */ member
4167 if (ha->nx_pcibase) in qla4xxx_mem_free()4169 (struct device_reg_82xx __iomem *)ha->nx_pcibase); in qla4xxx_mem_free()4171 if (ha->nx_pcibase) in qla4xxx_mem_free()4173 (struct device_reg_83xx __iomem *)ha->nx_pcibase); in qla4xxx_mem_free()5508 ha->nx_pcibase = (unsigned long)ioremap(mem_base, mem_len); in qla4_8xxx_iospace_config()5509 if (!ha->nx_pcibase) { in qla4_8xxx_iospace_config()5521 ((uint8_t *)ha->nx_pcibase + 0xbc000 + in qla4_8xxx_iospace_config()5527 ((uint8_t *)ha->nx_pcibase); in qla4_8xxx_iospace_config()