| H A D | niu.c | 72 #define nw64(reg, val) writeq((val), np->regs + (reg)) macro
200 nw64(reg, bits); __niu_set_and_wait_clear()
221 nw64(LDG_IMGMT(lp->ldg_num), val); niu_ldg_rearm()
245 nw64(mask_reg, val); niu_ldn_irq_enable()
316 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg)); mdio_read()
321 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev)); mdio_read()
329 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg)); mdio_write()
334 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data)); mdio_write()
344 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg)); mii_read()
352 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data)); mii_write()
798 nw64(ctrl_reg, ctrl_val); serdes_init_10g()
799 nw64(test_cfg_reg, test_cfg_val); serdes_init_10g()
901 nw64(ENET_SERDES_1_PLL_CFG, val); serdes_init_1g()
959 nw64(ENET_SERDES_RESET, reset_val); serdes_init_1g_serdes()
963 nw64(pll_cfg, val); serdes_init_1g_serdes()
964 nw64(ctrl_reg, ctrl_val); serdes_init_1g_serdes()
965 nw64(test_cfg_reg, test_cfg_val); serdes_init_1g_serdes()
966 nw64(ENET_SERDES_RESET, val_rd); serdes_init_1g_serdes()
1568 nw64(MIF_CONFIG, val); xcvr_init_10g_bcm8706()
1625 nw64(MIF_CONFIG, val); xcvr_init_10g()
1678 nw64(MIF_CONFIG, val); xcvr_init_1g_rgmii()
1872 nw64(MIF_CONFIG, val); xcvr_init_1g()
2414 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2); serdes_init_10g_serdes()
2415 nw64(ctrl_reg, ctrl_val); serdes_init_10g_serdes()
2416 nw64(test_cfg_reg, test_cfg_val); serdes_init_10g_serdes()
2779 nw64(ENET_VLAN_TBL(index), reg_val); vlan_tbl_write()
2787 nw64(ENET_VLAN_TBL(i), 0); vlan_tbl_clear()
2807 nw64(TCAM_KEY_0, 0x00); tcam_flush()
2808 nw64(TCAM_KEY_MASK_0, 0xff); tcam_flush()
2809 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index)); tcam_flush()
2820 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2839 nw64(TCAM_KEY_0, key[0]); tcam_write()
2840 nw64(TCAM_KEY_1, key[1]); tcam_write()
2841 nw64(TCAM_KEY_2, key[2]); tcam_write()
2842 nw64(TCAM_KEY_3, key[3]); tcam_write()
2843 nw64(TCAM_KEY_MASK_0, mask[0]); tcam_write()
2844 nw64(TCAM_KEY_MASK_1, mask[1]); tcam_write()
2845 nw64(TCAM_KEY_MASK_2, mask[2]); tcam_write()
2846 nw64(TCAM_KEY_MASK_3, mask[3]); tcam_write()
2847 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index)); tcam_write()
2857 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2868 nw64(TCAM_KEY_1, assoc_data); tcam_assoc_write()
2869 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index)); tcam_assoc_write()
2882 nw64(FFLP_CFG_1, val); tcam_enable()
2894 nw64(FFLP_CFG_1, val); tcam_set_lat_and_ratio()
2898 nw64(FFLP_CFG_1, val); tcam_set_lat_and_ratio()
2917 nw64(reg, val); tcam_user_eth_class_enable()
2938 nw64(reg, val);
2960 nw64(reg, val); tcam_user_ip_class_enable()
2988 nw64(reg, val); tcam_user_ip_class_set()
3045 nw64(HASH_TBL_ADDR(partition), val);
3064 nw64(HASH_TBL_ADDR(partition), val); hash_write()
3066 nw64(HASH_TBL_DATA(partition), data[i]); hash_write()
3075 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST); fflp_reset()
3077 nw64(FFLP_CFG_1, 0); fflp_reset()
3080 nw64(FFLP_CFG_1, val); fflp_reset()
3089 nw64(FFLP_CFG_1, val); fflp_set_timings()
3093 nw64(FFLP_CFG_1, val); fflp_set_timings()
3099 nw64(FCRAM_REF_TMR, val); fflp_set_timings()
3121 nw64(reg, val); fflp_set_partition()
3146 nw64(FFLP_CFG_1, val); fflp_llcsnap_enable()
3157 nw64(FFLP_CFG_1, val); fflp_errors_enable()
3208 nw64(H1POLY, 0); fflp_early_init()
3209 nw64(H2POLY, 0); fflp_early_init()
3242 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key); niu_set_flow_key()
3252 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key); niu_set_tcam_key()
3375 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending); niu_rbr_refill()
3655 * reading nr64() and clearing the counter nw64(). For this niu_sync_rx_discard_stats()
3656 * reason, the number of counter clearings nw64() is niu_sync_rx_discard_stats()
3669 nw64(RXMISC(rx_channel), 0); niu_sync_rx_discard_stats()
3684 nw64(RED_DIS_CNT(rx_channel), 0); niu_sync_rx_discard_stats()
3736 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat); niu_rx_work()
3759 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0); niu_poll_core()
3774 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0); niu_poll_core()
3850 nw64(RX_DMA_CTL_STAT(rp->rx_channel), niu_rx_error()
4100 nw64(RX_DMA_CTL_STAT(rp->rx_channel), niu_slowpath_interrupt()
4151 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write); niu_rxchan_intr()
4182 nw64(LD_IM0(ldn), LD_IM0_MASK); __niu_fastpath_interrupt()
4194 nw64(LD_IM0(ldn), LD_IM0_MASK); __niu_fastpath_interrupt()
4576 nw64(TX_CS(channel), val); niu_tx_channel_stop()
4599 nw64(TX_CS(channel), val); niu_tx_channel_reset()
4603 nw64(TX_RING_KICK(channel), 0); niu_tx_channel_reset()
4612 nw64(TX_LOG_MASK1(channel), 0); niu_tx_channel_lpage_init()
4613 nw64(TX_LOG_VAL1(channel), 0); niu_tx_channel_lpage_init()
4614 nw64(TX_LOG_MASK2(channel), 0); niu_tx_channel_lpage_init()
4615 nw64(TX_LOG_VAL2(channel), 0); niu_tx_channel_lpage_init()
4616 nw64(TX_LOG_PAGE_RELO1(channel), 0); niu_tx_channel_lpage_init()
4617 nw64(TX_LOG_PAGE_RELO2(channel), 0); niu_tx_channel_lpage_init()
4618 nw64(TX_LOG_PAGE_HDL(channel), 0); niu_tx_channel_lpage_init()
4622 nw64(TX_LOG_PAGE_VLD(channel), val); niu_tx_channel_lpage_init()
4644 nw64(TXC_CONTROL, val); niu_txc_enable_port()
4670 nw64(TXC_PORT_DMA(np->port), val); niu_txc_port_dma_enable()
4690 nw64(TXC_DMA_MAX(channel), rp->max_burst); niu_init_one_tx_channel()
4691 nw64(TX_ENT_MSK(channel), 0); niu_init_one_tx_channel()
4709 nw64(TX_RNG_CFIG(channel), val); niu_init_one_tx_channel()
4717 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32); niu_init_one_tx_channel()
4718 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR); niu_init_one_tx_channel()
4720 nw64(TX_CS(channel), 0); niu_init_one_tx_channel()
4738 nw64(RDC_TBL(this_table, slot), niu_init_rdc_groups()
4742 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]); niu_init_rdc_groups()
4760 nw64(PT_DRR_WT(np->port), val); niu_init_drr_weight()
4798 nw64(RX_LOG_MASK1(channel), 0); niu_rx_channel_lpage_init()
4799 nw64(RX_LOG_VAL1(channel), 0); niu_rx_channel_lpage_init()
4800 nw64(RX_LOG_MASK2(channel), 0); niu_rx_channel_lpage_init()
4801 nw64(RX_LOG_VAL2(channel), 0); niu_rx_channel_lpage_init()
4802 nw64(RX_LOG_PAGE_RELO1(channel), 0); niu_rx_channel_lpage_init()
4803 nw64(RX_LOG_PAGE_RELO2(channel), 0); niu_rx_channel_lpage_init()
4804 nw64(RX_LOG_PAGE_HDL(channel), 0); niu_rx_channel_lpage_init()
4808 nw64(RX_LOG_PAGE_VLD(channel), val); niu_rx_channel_lpage_init()
4821 nw64(RDC_RED_PARA(rp->rx_channel), val); niu_rx_channel_wred_init()
4913 nw64(RXDMA_CFIG1(channel), val); niu_enable_rx_channel()
4941 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY); niu_init_one_rx_channel()
4942 nw64(RX_DMA_CTL_STAT(channel), niu_init_one_rx_channel()
4947 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32); niu_init_one_rx_channel()
4948 nw64(RXDMA_CFIG2(channel), niu_init_one_rx_channel()
4951 nw64(RBR_CFIG_A(channel), niu_init_one_rx_channel()
4957 nw64(RBR_CFIG_B(channel), val); niu_init_one_rx_channel()
4958 nw64(RCRCFIG_A(channel), niu_init_one_rx_channel()
4961 nw64(RCRCFIG_B(channel), niu_init_one_rx_channel()
4970 nw64(RBR_KICK(channel), rp->rbr_index); niu_init_one_rx_channel()
4974 nw64(RX_DMA_CTL_STAT(channel), val); niu_init_one_rx_channel()
4986 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider); niu_init_rx_channels()
4987 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL)); niu_init_rx_channels()
5046 nw64(H1POLY, cp->h1_init); niu_init_classifier_hw()
5047 nw64(H2POLY, cp->h2_init); niu_init_classifier_hw()
5091 nw64(ZCP_RAM_DATA0, data[0]); niu_zcp_write()
5092 nw64(ZCP_RAM_DATA1, data[1]); niu_zcp_write()
5093 nw64(ZCP_RAM_DATA2, data[2]); niu_zcp_write()
5094 nw64(ZCP_RAM_DATA3, data[3]); niu_zcp_write()
5095 nw64(ZCP_RAM_DATA4, data[4]); niu_zcp_write()
5096 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL); niu_zcp_write()
5097 nw64(ZCP_RAM_ACC, niu_zcp_write()
5118 nw64(ZCP_RAM_ACC, niu_zcp_read()
5145 nw64(RESET_CFIFO, val); niu_zcp_cfifo_reset()
5149 nw64(RESET_CFIFO, val); niu_zcp_cfifo_reset()
5181 nw64(CFIFO_ECC(np->port), 0); niu_init_zcp()
5182 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL); niu_init_zcp()
5184 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL); niu_init_zcp()
5297 nw64(MIF_CONFIG, val); niu_init_xif_xmac()
5892 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL); niu_reset_one_rx_channel()
5893 nw64(RX_DMA_CTL_STAT(channel), 0); niu_reset_one_rx_channel()
6737 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3)); niu_start_xmit()
7338 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key); niu_set_hash_opts()
7350 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), niu_set_hash_opts()
7362 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key); niu_set_hash_opts()
7945 nw64(LDG_NUM(ldn), ldg); niu_ldg_assign_ldn()
7956 nw64(LDG_TIMER_RES, res); niu_set_ldg_timer_res()
7968 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector); niu_set_ldg_sid()
7983 nw64(ESPC_PIO_STAT, frame); niu_pci_eeprom_read()
7998 nw64(ESPC_PIO_STAT, frame); niu_pci_eeprom_read()
9302 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE); niu_get_invariants()
9308 nw64(ESPC_PIO_EN, 0); niu_get_invariants()
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