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Searched refs:nvif_rd32 (Results 1 – 14 of 14) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/nouveau/
Dnouveau_backlight.c44 int val = (nvif_rd32(device, NV40_PMC_BACKLIGHT) & in nv40_get_intensity()
56 int reg = nvif_rd32(device, NV40_PMC_BACKLIGHT); in nv40_set_intensity()
78 if (!(nvif_rd32(device, NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK)) in nv40_backlight_init()
105 val = nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(or)); in nv50_get_intensity()
140 div = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or)); in nva3_get_intensity()
141 val = nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(or)); in nva3_get_intensity()
158 div = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or)); in nva3_set_intensity()
193 if (!nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(nv_encoder->or))) in nv50_backlight_init()
Dnouveau_dma.c55 val = nvif_rd32(chan, chan->user_get); in READ_GET()
57 val |= (uint64_t)nvif_rd32(chan, chan->user_get_hi) << 32; in READ_GET()
116 uint32_t get = nvif_rd32(chan, 0x88); in nv50_dma_push_wait()
Dnv10_fence.c53 return nvif_rd32(chan, 0x0048); in nv10_fence_read()
Dnouveau_agp.c116 if ((nvif_rd32(device, NV04_PBUS_PCI_NV_19) | in nouveau_agp_reset()
Dnouveau_bios.c241 sel_clk_binding = nvif_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000; in call_lvds_script()
336 return (nvif_rd32(device, NV_PEXTDEV_BOOT_0) >> 24) & 0xf; in get_fp_strap()
338 return (nvif_rd32(device, NV_PEXTDEV_BOOT_0) >> 16) & 0xf; in get_fp_strap()
671 sel_clk_binding = nvif_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000; in run_tmds_table()
1949 nvif_wr32(device, NV_PBUS_DEBUG_4, nvif_rd32(device, NV_PBUS_DEBUG_4) | 0x18); in load_nv17_hwsq_ucode_entry()
Dnv50_display.c416 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4; in evo_wait()
2512 crtcs = nvif_rd32(device, 0x022448); in nv50_display_create()
/linux-4.1.27/drivers/gpu/drm/nouveau/dispnv04/
Darb.c206 uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1); in nv04_update_arb()
224 sim_data.memory_type = nvif_rd32(device, NV04_PFB_CFG0) & 0x1; in nv04_update_arb()
225 sim_data.memory_width = (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64; in nv04_update_arb()
Dhw.h67 val = nvif_rd32(device, reg); in NVReadCRTC()
87 val = nvif_rd32(device, reg); in NVReadRAMDAC()
266 return !!(nvif_rd32(device, NV_PBUS_DEBUG_1) & (1 << 28)); in nv_heads_tied()
Dtvnv17.h140 return nvif_rd32(device, reg); in nv_read_ptv()
Ddac.c259 saved_powerctrl_2 = nvif_rd32(device, NV_PBUS_POWERCTRL_2); in nv17_dac_sample_load()
263 saved_powerctrl_4 = nvif_rd32(device, NV_PBUS_POWERCTRL_4); in nv17_dac_sample_load()
Dhw.c178 pll1 = nvif_rd32(device, reg1); in nouveau_hw_get_pllvals()
180 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
184 pll2 = nvif_rd32(device, reg2); in nouveau_hw_get_pllvals()
Doverlay.c418 nvif_wr32(dev, NV_PVIDEO_SU_STATE, nvif_rd32(dev, NV_PVIDEO_SU_STATE) ^ (1 << 16)); in nv04_update_plane()
Ddfp.c338 if (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT) in nv04_dfp_mode_set()
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvif/
Dobject.h59 #define nvif_rd32(a,b) ({ u32 _v = nvif_rd((a), 32, (b)); _v; }) macro
64 u32 _v = nvif_rd32(nvif_object(a), (b)); \