Searched refs:nv04_display (Results 1 – 12 of 12) sorted by relevance
61 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_set_digital_vibrance()76 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_set_image_sharpening()118 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; in nv_crtc_calc_state_ext()242 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_vga()467 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_regs()468 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_regs()546 …regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TV… in nv_crtc_mode_set_regs()612 struct nv04_display *disp = nv04_display(crtc->dev); in nv_crtc_swap_fbs()658 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); in nv_crtc_mode_set()668 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; in nv_crtc_save()[all …]
95 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg; in nv04_dfp_disable()122 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control; in nv04_dfp_update_fp_control()137 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control; in nv04_dfp_update_fp_control()206 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; in nv04_dfp_prepare_sel_clk()236 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && nv04_display(dev)->saved_reg.sel_clk & 0xf0) { in nv04_dfp_prepare_sel_clk()237 int shift = (nv04_display(dev)->saved_reg.sel_clk & 0x50) ? 0 : 1; in nv04_dfp_prepare_sel_clk()250 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg; in nv04_dfp_prepare()287 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_dfp_mode_set()288 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; in nv04_dfp_mode_set()462 nv04_display(dev)->mode_reg.crtc_reg[head].fp_control = in nv04_dfp_commit()[all …]
43 struct nv04_display *disp; in nv04_display_create()125 struct nv04_display *disp = nv04_display(dev); in nv04_display_destroy()
78 struct nv04_display { struct86 static inline struct nv04_display * argument87 nv04_display(struct drm_device *dev) in nv04_display() function
76 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; in nv04_tv_dpms()104 struct nv04_crtc_reg *state = &nv04_display(dev)->mode_reg.crtc_reg[head]; in nv04_tv_bind()143 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_tv_mode_set()
42 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_cursor_set_offset()
427 uint32_t *dac_users = &nv04_display(dev)->dac_users[ffs(dcb->or) - 1]; in nv04_dac_update_dacclk()452 (nv04_display(dev)->dac_users[ffs(dcb->or) - 1] & ~(1 << dcb->index)); in nv04_dac_in_use()
411 uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[ in nv17_tv_prepare()472 struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head]; in nv17_tv_mode_set()
377 &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]; in nv_show_cursor()
294 nv04_display(dev)->saved_vga_font[plane][i] = in nouveau_vga_font_io()297 iowrite32_native(nv04_display(dev)->saved_vga_font[plane][i], in nouveau_vga_font_io()
548 struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head]; in nv17_ctv_update_rescaler()
761 struct nv04_display *dispnv04 = nv04_display(dev); in nouveau_crtc_page_flip()