Searched refs:mux_val (Results 1 – 5 of 5) sorted by relevance
| /linux-4.1.27/drivers/clk/mmp/ |
| D | clk-mix.c | 134 static int _set_rate(struct mmp_clk_mix *mix, u32 mux_val, u32 div_val, in _set_rate() argument
166 mux_div |= MMP_CLK_BITS_SET_VAL(mux_val, width, shift); in _set_rate()
281 u32 div_val, mux_val; in mmp_clk_mix_set_rate_and_parent() local
285 mux_val = _get_mux_val(mix, index); in mmp_clk_mix_set_rate_and_parent()
287 return _set_rate(mix, mux_val, div_val, 1, 1); in mmp_clk_mix_set_rate_and_parent()
297 u32 mux_val; in mmp_clk_mix_get_parent() local
314 mux_val = MMP_CLK_BITS_GET_VAL(mux_div, width, shift); in mmp_clk_mix_get_parent()
316 return _get_mux(mix, mux_val); in mmp_clk_mix_get_parent()
354 u32 div_val, mux_val; in mmp_clk_set_parent() local
366 mux_val = _get_mux_val(mix, item->parent_index); in mmp_clk_set_parent()
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| /linux-4.1.27/drivers/gpio/ |
| D | gpio-sodaville.c | 199 u32 mux_val; in sdv_gpio_probe() local
225 mux_val = of_read_number(prop, 1); in sdv_gpio_probe()
226 writel(mux_val, sd->gpio_pub_base + GPMUXCTL); in sdv_gpio_probe()
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| /linux-4.1.27/Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx6sx-pinctrl.txt | 9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| D | fsl,imx-pinctrl.txt | 26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| /linux-4.1.27/drivers/pinctrl/ |
| D | pinctrl-zynq.c | 82 unsigned int mux_val; member
714 .mux_val = mval, \
722 .mux_val = mval, \
879 reg |= func->mux_val << ZYNQ_PINMUX_MUX_SHIFT; in zynq_pinmux_set_mux()
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