Searched refs:mtr (Results 1 - 9 of 9) sorted by relevance

/linux-4.1.27/drivers/edac/
H A Di7300_edac.c107 u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */ member in struct:i7300_pvt
174 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8))
175 #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7))
176 #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4)
177 #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4)
178 #define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0)
179 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
181 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
182 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
183 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
592 int mtr, ans, addrBits, channel; decode_mtr() local
596 mtr = pvt->mtr[slot][branch]; decode_mtr()
597 ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0; decode_mtr()
599 edac_dbg(2, "\tMTR%d CH%d: DIMMs are %sPresent (mtr)\n", decode_mtr()
610 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr); decode_mtr()
612 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); decode_mtr()
614 addrBits += MTR_DIMM_RANKS(mtr); decode_mtr()
622 edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr)); decode_mtr()
625 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled"); decode_mtr()
627 edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr)); decode_mtr()
629 MTR_DIMM_RANKS(mtr) ? "double" : "single"); decode_mtr()
631 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" : decode_mtr()
632 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" : decode_mtr()
633 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" : decode_mtr()
636 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" : decode_mtr()
637 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" : decode_mtr()
638 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" : decode_mtr()
659 if (MTR_DRAM_WIDTH(mtr) == 8) decode_mtr()
666 if (MTR_DRAM_WIDTH(mtr) == 8) { decode_mtr()
675 return mtr; decode_mtr()
752 int mtr; i7300_init_csrows() local
795 &pvt->mtr[slot][branch]); i7300_init_csrows()
804 mtr = decode_mtr(pvt, slot, ch, branch, i7300_init_csrows()
808 if (!MTR_DIMMS_PRESENT(mtr)) i7300_init_csrows()
H A Di5400_edac.c285 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 10))
286 #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 9))
287 #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 8)) ? 8 : 4)
288 #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 6)) ? 8 : 4)
289 #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)
290 #define MTR_DIMM_RANK(mtr) (((mtr) >> 5) & 0x1)
291 #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1)
292 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
293 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
294 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
295 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
863 int mtr; determine_mtr() local
878 mtr = pvt->b0_mtr[n]; determine_mtr()
880 mtr = pvt->b1_mtr[n]; determine_mtr()
882 return mtr; determine_mtr()
887 static void decode_mtr(int slot_row, u16 mtr) decode_mtr() argument
891 ans = MTR_DIMMS_PRESENT(mtr); decode_mtr()
894 slot_row, mtr, ans ? "" : "NOT "); decode_mtr()
898 edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr)); decode_mtr()
901 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled"); decode_mtr()
903 edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr)); decode_mtr()
905 MTR_DIMM_RANK(mtr) ? "double" : "single"); decode_mtr()
907 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" : decode_mtr()
908 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" : decode_mtr()
909 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" : decode_mtr()
912 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" : decode_mtr()
913 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" : decode_mtr()
914 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" : decode_mtr()
921 int mtr; handle_channel() local
925 mtr = determine_mtr(pvt, dimm, channel); handle_channel()
926 if (MTR_DIMMS_PRESENT(mtr)) { handle_channel()
933 addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr); handle_channel()
935 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr); handle_channel()
937 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); handle_channel()
939 addrBits += MTR_DIMM_RANK(mtr); handle_channel()
1175 int mtr; i5400_init_dimms() local
1193 mtr = determine_mtr(pvt, slot, channel); i5400_init_dimms()
1196 if (!MTR_DIMMS_PRESENT(mtr)) i5400_init_dimms()
1210 dimm->dtype = MTR_DRAM_WIDTH(mtr) ? DEV_X8 : DEV_X4; i5400_init_dimms()
1216 dimm->edac_mode = MTR_DRAM_WIDTH(mtr) ? i5400_init_dimms()
H A Di5000_edac.c279 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (0x1 << 8))
280 #define MTR_DRAM_WIDTH(mtr) ((((mtr) >> 6) & 0x1) ? 8 : 4)
281 #define MTR_DRAM_BANKS(mtr) ((((mtr) >> 5) & 0x1) ? 8 : 4)
282 #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)
283 #define MTR_DIMM_RANK(mtr) (((mtr) >> 4) & 0x1)
284 #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1)
285 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
286 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
287 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
288 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
953 int mtr; determine_mtr() local
956 mtr = pvt->b0_mtr[slot]; determine_mtr()
958 mtr = pvt->b1_mtr[slot]; determine_mtr()
960 return mtr; determine_mtr()
965 static void decode_mtr(int slot_row, u16 mtr) decode_mtr() argument
969 ans = MTR_DIMMS_PRESENT(mtr); decode_mtr()
972 slot_row, mtr, ans ? "" : "NOT "); decode_mtr()
976 edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr)); decode_mtr()
977 edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr)); decode_mtr()
979 MTR_DIMM_RANK(mtr) ? "double" : "single"); decode_mtr()
981 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" : decode_mtr()
982 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" : decode_mtr()
983 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" : decode_mtr()
986 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" : decode_mtr()
987 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" : decode_mtr()
988 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" : decode_mtr()
995 int mtr; handle_channel() local
999 mtr = determine_mtr(pvt, slot, channel); handle_channel()
1000 if (MTR_DIMMS_PRESENT(mtr)) { handle_channel()
1005 dinfo->dual_rank = MTR_DIMM_RANK(mtr); handle_channel()
1009 addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr); handle_channel()
1011 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr); handle_channel()
1013 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); handle_channel()
1258 int mtr; i5000_init_csrows() local
1280 mtr = determine_mtr(pvt, slot, channel); i5000_init_csrows()
1282 if (!MTR_DIMMS_PRESENT(mtr)) i5000_init_csrows()
1296 if (MTR_DRAM_WIDTH(mtr)) i5000_init_csrows()
H A Dsb_edac.c189 #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
190 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
191 #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
192 #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
193 #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
560 static inline int numrank(enum type type, u32 mtr) numrank() argument
562 int ranks = (1 << RANK_CNT_BITS(mtr)); numrank()
570 ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr); numrank()
577 static inline int numrow(u32 mtr) numrow() argument
579 int rows = (RANK_WIDTH_BITS(mtr) + 12); numrow()
583 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr); numrow()
590 static inline int numcol(u32 mtr) numcol() argument
592 int cols = (COL_WIDTH_BITS(mtr) + 10); numcol()
596 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr); numcol()
913 u32 mtr; get_dimm_config() local
919 mtr_regs[j], &mtr); get_dimm_config()
920 edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr); get_dimm_config()
921 if (IS_DIMM_PRESENT(mtr)) { get_dimm_config()
924 ranks = numrank(pvt->info.type, mtr); get_dimm_config()
925 rows = numrow(mtr); get_dimm_config()
926 cols = numcol(mtr); get_dimm_config()
H A Di5100_edac.c339 } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN]; member in struct:i5100_priv
666 if (!priv->mtr[chan][chan_rank].present) i5100_npages()
671 priv->mtr[chan][chan_rank].numcol + i5100_npages()
672 priv->mtr[chan][chan_rank].numrow + i5100_npages()
673 priv->mtr[chan][chan_rank].numbank; i5100_npages()
697 priv->mtr[i][j].present = i5100_mtr_present(w); i5100_init_mtr()
698 priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w); i5100_init_mtr()
699 priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w); i5100_init_mtr()
700 priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w); i5100_init_mtr()
701 priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w); i5100_init_mtr()
702 priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w); i5100_init_mtr()
868 dimm->dtype = (priv->mtr[chan][rank].width == 4) ? i5100_init_csrows()
/linux-4.1.27/arch/alpha/include/asm/
H A Dcore_titan.h36 titan_64 mtr; member in struct:__anon21
H A Dcore_tsunami.h35 tsunami_64 mtr; member in struct:__anon34
/linux-4.1.27/arch/alpha/kernel/
H A Dcore_tsunami.c396 printk("%s: CSR_MTR 0x%lx\n", __func__, TSUNAMI_cchip.mtr.csr); tsunami_init_arch()
H A Dcore_titan.c374 printk("%s: CSR_MTR 0x%lx\n", __func__, TITAN_cchip->mtr.csr); titan_init_arch()

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