| H A D | axon_msi.c | 81 void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic);
84 struct axon_msic *msic) { }
88 static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val) msic_dcr_write() argument
92 dcr_write(msic->dcr_host, dcr_n, val); msic_dcr_write()
98 struct axon_msic *msic = irq_get_handler_data(irq); axon_msi_cascade() local
103 write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG); axon_msi_cascade()
109 while (msic->read_offset != write_offset && retry < 100) { axon_msi_cascade()
110 idx = msic->read_offset / sizeof(__le32); axon_msi_cascade()
111 msi = le32_to_cpu(msic->fifo_virt[idx]); axon_msi_cascade()
115 write_offset, msic->read_offset, msi); axon_msi_cascade()
117 if (msi < nr_irqs && irq_get_chip_data(msi) == msic) { axon_msi_cascade()
119 msic->fifo_virt[idx] = cpu_to_le32(0xffffffff); axon_msi_cascade()
139 msic->read_offset += MSIC_FIFO_ENTRY_SIZE; axon_msi_cascade()
140 msic->read_offset &= MSIC_FIFO_SIZE_MASK; axon_msi_cascade()
146 msic->read_offset += MSIC_FIFO_ENTRY_SIZE; axon_msi_cascade()
147 msic->read_offset &= MSIC_FIFO_SIZE_MASK; axon_msi_cascade()
158 struct axon_msic *msic = NULL; find_msi_translator() local
194 msic = irq_domain->host_data; find_msi_translator()
199 return msic; find_msi_translator()
261 struct axon_msic *msic; axon_msi_setup_msi_irqs() local
263 msic = find_msi_translator(dev); axon_msi_setup_msi_irqs()
264 if (!msic) axon_msi_setup_msi_irqs()
272 virq = irq_create_direct_mapping(msic->irq_domain); axon_msi_setup_msi_irqs()
325 struct axon_msic *msic = dev_get_drvdata(&device->dev); axon_msi_shutdown() local
329 msic->irq_domain->of_node->full_name); axon_msi_shutdown()
330 tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG); axon_msi_shutdown()
332 msic_dcr_write(msic, MSIC_CTRL_REG, tmp); axon_msi_shutdown()
338 struct axon_msic *msic; axon_msi_probe() local
344 msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL); axon_msi_probe()
345 if (!msic) { axon_msi_probe()
346 printk(KERN_ERR "axon_msi: couldn't allocate msic for %s\n", axon_msi_probe()
361 msic->dcr_host = dcr_map(dn, dcr_base, dcr_len); axon_msi_probe()
362 if (!DCR_MAP_OK(msic->dcr_host)) { axon_msi_probe()
368 msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, axon_msi_probe()
369 &msic->fifo_phys, GFP_KERNEL); axon_msi_probe()
370 if (!msic->fifo_virt) { axon_msi_probe()
382 memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES); axon_msi_probe()
385 msic->irq_domain = irq_domain_add_nomap(dn, 65536, &msic_host_ops, msic); axon_msi_probe()
386 if (!msic->irq_domain) { axon_msi_probe()
392 irq_set_handler_data(virq, msic); axon_msi_probe()
397 msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32); axon_msi_probe()
398 msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG, axon_msi_probe()
399 msic->fifo_phys & 0xFFFFFFFF); axon_msi_probe()
400 msic_dcr_write(msic, MSIC_CTRL_REG, axon_msi_probe()
404 msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG) axon_msi_probe()
407 dev_set_drvdata(&device->dev, msic); axon_msi_probe()
412 axon_msi_debug_setup(dn, msic); axon_msi_probe()
419 dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt, axon_msi_probe()
420 msic->fifo_phys); axon_msi_probe()
422 kfree(msic); axon_msi_probe()
430 .compatible = "ibm,axon-msic"
454 struct axon_msic *msic = data; msic_set() local
455 out_le32(msic->trigger, val); msic_set()
467 void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic) axon_msi_debug_setup() argument
478 msic->trigger = ioremap(addr, 0x4); axon_msi_debug_setup()
479 if (!msic->trigger) { axon_msi_debug_setup()
487 msic, &fops_msic)) { axon_msi_debug_setup()
83 axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic) axon_msi_debug_setup() argument
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