Searched refs:midr (Results 1 – 8 of 8) sorted by relevance
42 #define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK) argument45 #define MIDR_PARTNUM(midr) \ argument46 (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)49 #define MIDR_ARCHITECTURE(midr) \ argument50 (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)53 #define MIDR_VARIANT(midr) \ argument54 (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)57 #define MIDR_IMPLEMENTOR(midr) \ argument58 (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
33 u32 midr = read_cpuid_id(); in is_affected_midr_range() local35 if ((midr & CPU_MODEL_MASK) != entry->midr_model) in is_affected_midr_range()38 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK; in is_affected_midr_range()40 return (midr >= entry->midr_range_min && midr <= entry->midr_range_max); in is_affected_midr_range()
515 u32 midr = cpuinfo->reg_midr; in c_show() local555 MIDR_IMPLEMENTOR(midr)); in c_show()557 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr)); in c_show()558 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr)); in c_show()559 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); in c_show()
92 unsigned int midr = read_cpuid_id(); in erratum_a15_798181_init() local97 if ((midr & 0xff0ffff0) == 0x420f00f0 && midr <= 0x420f00f2) in erratum_a15_798181_init()99 else if ((midr & 0xff0ffff0) == 0x410fc0f0 && midr <= 0x413fc0f2 && in erratum_a15_798181_init()
174 DEFINE(VCPU_MIDR, offsetof(struct kvm_vcpu, arch.midr)); in main()
66 vcpu->arch.midr = read_cpuid_id(); in kvm_reset_vcpu()
20 u32 midr; member
106 u32 midr; member