Searched refs:mfdcr (Results 1 – 8 of 8) sorted by relevance
40 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC)) in l2c_diag()43 return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA); in l2c_diag()48 u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR); in l2c_error_handler()131 mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE); in ppc4xx_l2c_probe()133 mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()135 mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()137 mfdcr(dcrbase_isram + DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()139 mfdcr(dcrbase_isram + DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()142 r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) & in ppc4xx_l2c_probe()151 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC)) in ppc4xx_l2c_probe()[all …]
66 er = mfdcr(uic->dcrbase + UIC_ER); in uic_unmask_irq()80 er = mfdcr(uic->dcrbase + UIC_ER); in uic_mask_irq()106 er = mfdcr(uic->dcrbase + UIC_ER); in uic_mask_ack_irq()154 tr = mfdcr(uic->dcrbase + UIC_TR); in uic_set_irq_type()155 pr = mfdcr(uic->dcrbase + UIC_PR); in uic_set_irq_type()213 msr = mfdcr(uic->dcrbase + UIC_MSR); in uic_irq_cascade()330 msr = mfdcr(primary_uic->dcrbase + UIC_MSR); in uic_get_irq()
36 mfdcr r3,0; blr42 mfdcr r3,dcr; blr
110 banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B0BAS)); in ibm440spe_fixup_memsize()113 banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B1BAS)); in ibm440spe_fixup_memsize()116 banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B2BAS)); in ibm440spe_fixup_memsize()119 banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B3BAS)); in ibm440spe_fixup_memsize()301 while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET) in ibm4xx_quiesce_eth()317 bxcr = mfdcr(DCRN_EBC0_CFGDATA); in ibm4xx_fixup_ebc_ranges()337 u32 sys0 = mfdcr(DCRN_CPC0_SYS0); in ibm440gp_fixup_clocks()338 u32 cr0 = mfdcr(DCRN_CPC0_CR0); in ibm440gp_fixup_clocks()554 u32 pllmr = mfdcr(DCRN_CPC0_PLLMR); in ibm405gp_fixup_clocks()555 u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0); in ibm405gp_fixup_clocks()[all …]
4 #define mfdcr(rn) \ macro29 mfdcr(DCRN_SDRAM0_CFGDATA); })182 mfdcr(DCRN_SDR0_CONFIG_DATA); })200 mfdcr(DCRN_CPR0_CFGDATA); })
29 u32 uart = mfdcr(DCRN_CPC0_UCR) & 0x7f; in hotfoot_fixups()
40 #define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base)64 #define mfdcr(rn) \ macro
68 mfdcr r3,DCRN_PLB4A0_ACR