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Searched refs:mdp5_write (Results 1 – 9 of 9) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/msm/mdp/mdp5/
Dmdp5_encoder.c197 mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_CTL(intf), in mdp5_encoder_mode_set()
200 mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_PERIOD_F0(intf), vsync_period); in mdp5_encoder_mode_set()
201 mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_LEN_F0(intf), vsync_len); in mdp5_encoder_mode_set()
202 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_HCTL(intf), in mdp5_encoder_mode_set()
205 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VSTART_F0(intf), display_v_start); in mdp5_encoder_mode_set()
206 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VEND_F0(intf), display_v_end); in mdp5_encoder_mode_set()
207 mdp5_write(mdp5_kms, REG_MDP5_INTF_BORDER_COLOR(intf), 0); in mdp5_encoder_mode_set()
208 mdp5_write(mdp5_kms, REG_MDP5_INTF_UNDERFLOW_COLOR(intf), 0xff); in mdp5_encoder_mode_set()
209 mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_SKEW(intf), dtv_hsync_skew); in mdp5_encoder_mode_set()
210 mdp5_write(mdp5_kms, REG_MDP5_INTF_POLARITY_CTL(intf), ctrl_pol); in mdp5_encoder_mode_set()
[all …]
Dmdp5_plane.c261 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe), in set_scanout_locked()
265 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe), in set_scanout_locked()
269 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe), in set_scanout_locked()
271 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe), in set_scanout_locked()
273 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe), in set_scanout_locked()
275 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe), in set_scanout_locked()
287 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value); in csc_disable()
305 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode); in csc_enable()
308 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe), in csc_enable()
311 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe), in csc_enable()
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Dmdp5_cmd_encoder.c129 mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_CONFIG_VSYNC(pp_id), cfg); in pingpong_tearcheck_setup()
130 mdp5_write(mdp5_kms, in pingpong_tearcheck_setup()
132 mdp5_write(mdp5_kms, in pingpong_tearcheck_setup()
134 mdp5_write(mdp5_kms, REG_MDP5_PP_RD_PTR_IRQ(pp_id), mode->vdisplay + 1); in pingpong_tearcheck_setup()
135 mdp5_write(mdp5_kms, REG_MDP5_PP_START_POS(pp_id), mode->vdisplay); in pingpong_tearcheck_setup()
136 mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_THRESH(pp_id), in pingpong_tearcheck_setup()
163 mdp5_write(mdp5_kms, REG_MDP5_PP_TEAR_CHECK_EN(pp_id), 1); in pingpong_tearcheck_enable()
173 mdp5_write(mdp5_kms, REG_MDP5_PP_TEAR_CHECK_EN(pp_id), 0); in pingpong_tearcheck_disable()
295 mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, data); in mdp5_cmd_encoder_set_split_display()
297 mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, in mdp5_cmd_encoder_set_split_display()
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Dmdp5_irq.c26 mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_MDP_INTR_EN(0), irqmask); in mdp5_set_irqmask()
38 mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_CLEAR(0), 0xffffffff); in mdp5_irq_preinstall()
39 mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_EN(0), 0x00000000); in mdp5_irq_preinstall()
64 mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_EN(0), 0x00000000); in mdp5_irq_uninstall()
77 mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_CLEAR(0), status); in mdp5_irq_mdp()
Dmdp5_crtc.c218 mdp5_write(mdp5_kms, in blend_setup()
222 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm, in blend_setup()
224 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm, in blend_setup()
261 mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(mdp5_crtc->lm), in mdp5_crtc_mode_set_nofb()
488 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride); in mdp5_crtc_cursor_set()
489 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm), in mdp5_crtc_cursor_set()
491 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm), in mdp5_crtc_cursor_set()
494 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm), in mdp5_crtc_cursor_set()
497 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm), cursor_addr); in mdp5_crtc_cursor_set()
501 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg); in mdp5_crtc_cursor_set()
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Dmdp5_smp.c171 mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(pipe), val * 1); in set_fifo_thresholds()
172 mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(pipe), val * 2); in set_fifo_thresholds()
173 mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(pipe), val * 3); in set_fifo_thresholds()
261 mdp5_write(mdp5_kms, REG_MDP5_MDP_SMP_ALLOC_W_REG(0, idx), val); in update_smp_state()
262 mdp5_write(mdp5_kms, REG_MDP5_MDP_SMP_ALLOC_R_REG(0, idx), val); in update_smp_state()
Dmdp5_ctl.c96 mdp5_write(mdp5_kms, reg, data); in ctl_write()
139 mdp5_write(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0), intf_sel); in set_display_intf()
Dmdp5_kms.h115 static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data) in mdp5_write() function
Dmdp5_kms.c61 mdp5_write(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0), 0); in mdp5_hw_init()
520 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0); in mdp5_kms_init()