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Searched refs:mdp4_write (Results 1 – 8 of 8) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/msm/mdp/mdp4/
Dmdp4_lcdc_encoder.c129 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0), in setup_phy()
134 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(0), in setup_phy()
138 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(1), in setup_phy()
143 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(1), in setup_phy()
147 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(2), in setup_phy()
152 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(2), in setup_phy()
156 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(3), in setup_phy()
161 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(3), in setup_phy()
183 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0), in setup_phy()
188 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(0), in setup_phy()
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Dmdp4_crtc.c96 mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush); in crtc_flush()
188 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg); in setup_mixer()
199 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0); in blend_setup()
200 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0); in blend_setup()
201 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0); in blend_setup()
202 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0); in blend_setup()
226 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff); in blend_setup()
227 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00); in blend_setup()
228 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op); in blend_setup()
229 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1); in blend_setup()
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Dmdp4_plane.c144 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_A(pipe), in mdp4_plane_set_scanout()
148 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_B(pipe), in mdp4_plane_set_scanout()
152 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP0_BASE(pipe), in mdp4_plane_set_scanout()
154 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP1_BASE(pipe), in mdp4_plane_set_scanout()
156 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP2_BASE(pipe), in mdp4_plane_set_scanout()
158 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP3_BASE(pipe), in mdp4_plane_set_scanout()
170 mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_MV(pipe, i), in mdp4_write_csc_config()
175 mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_PRE_BV(pipe, i), in mdp4_write_csc_config()
178 mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_POST_BV(pipe, i), in mdp4_write_csc_config()
183 mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_PRE_LV(pipe, i), in mdp4_write_csc_config()
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Dmdp4_dtv_encoder.c146 mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_CTRL, in mdp4_dtv_encoder_mode_set()
149 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_PERIOD, vsync_period); in mdp4_dtv_encoder_mode_set()
150 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_LEN, vsync_len); in mdp4_dtv_encoder_mode_set()
151 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_HCTRL, in mdp4_dtv_encoder_mode_set()
154 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VSTART, display_v_start); in mdp4_dtv_encoder_mode_set()
155 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VEND, display_v_end); in mdp4_dtv_encoder_mode_set()
156 mdp4_write(mdp4_kms, REG_MDP4_DTV_BORDER_CLR, 0); in mdp4_dtv_encoder_mode_set()
157 mdp4_write(mdp4_kms, REG_MDP4_DTV_UNDERFLOW_CLR, in mdp4_dtv_encoder_mode_set()
160 mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_SKEW, dtv_hsync_skew); in mdp4_dtv_encoder_mode_set()
161 mdp4_write(mdp4_kms, REG_MDP4_DTV_CTRL_POLARITY, ctrl_pol); in mdp4_dtv_encoder_mode_set()
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Dmdp4_kms.c78 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff); in mdp4_hw_init()
79 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f); in mdp4_hw_init()
82 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3); in mdp4_hw_init()
85 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222); in mdp4_hw_init()
99 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg); in mdp4_hw_init()
100 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg); in mdp4_hw_init()
102 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg); in mdp4_hw_init()
103 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg); in mdp4_hw_init()
104 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg); in mdp4_hw_init()
105 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg); in mdp4_hw_init()
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Dmdp4_irq.c24 mdp4_write(to_mdp4_kms(mdp_kms), REG_MDP4_INTR_ENABLE, irqmask); in mdp4_set_irqmask()
36 mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, 0xffffffff); in mdp4_irq_preinstall()
37 mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000); in mdp4_irq_preinstall()
60 mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000); in mdp4_irq_uninstall()
74 mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, status); in mdp4_irq()
Dmdp4_lvds_pll.c80 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_PHY_RESET, 0x33); in mpd4_lvds_pll_enable()
83 mdp4_write(mdp4_kms, pll_rate->conf[i].reg, pll_rate->conf[i].val); in mpd4_lvds_pll_enable()
85 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x01); in mpd4_lvds_pll_enable()
101 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, 0x0); in mpd4_lvds_pll_disable()
102 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x0); in mpd4_lvds_pll_disable()
Dmdp4_kms.h63 static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data) in mdp4_write() function