| /linux-4.1.27/drivers/gpu/drm/msm/mdp/mdp4/ |
| D | mdp4_kms.c | 27 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); in mdp4_hw_init() local
28 struct drm_device *dev = mdp4_kms->dev; in mdp4_hw_init()
35 mdp4_enable(mdp4_kms); in mdp4_hw_init()
36 version = mdp4_read(mdp4_kms, REG_MDP4_VERSION); in mdp4_hw_init()
37 mdp4_disable(mdp4_kms); in mdp4_hw_init()
51 mdp4_kms->rev = minor; in mdp4_hw_init()
53 if (mdp4_kms->dsi_pll_vdda) { in mdp4_hw_init()
54 if ((mdp4_kms->rev == 2) || (mdp4_kms->rev == 4)) { in mdp4_hw_init()
55 ret = regulator_set_voltage(mdp4_kms->dsi_pll_vdda, in mdp4_hw_init()
65 if (mdp4_kms->dsi_pll_vddio) { in mdp4_hw_init()
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| D | mdp4_irq.c | 34 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); in mdp4_irq_preinstall() local
35 mdp4_enable(mdp4_kms); in mdp4_irq_preinstall()
36 mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, 0xffffffff); in mdp4_irq_preinstall()
37 mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000); in mdp4_irq_preinstall()
38 mdp4_disable(mdp4_kms); in mdp4_irq_preinstall()
44 struct mdp4_kms *mdp4_kms = to_mdp4_kms(mdp_kms); in mdp4_irq_postinstall() local
45 struct mdp_irq *error_handler = &mdp4_kms->error_handler; in mdp4_irq_postinstall()
58 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); in mdp4_irq_uninstall() local
59 mdp4_enable(mdp4_kms); in mdp4_irq_uninstall()
60 mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000); in mdp4_irq_uninstall()
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| D | mdp4_crtc.c | 66 static struct mdp4_kms *get_kms(struct drm_crtc *crtc) in get_kms()
83 struct mdp4_kms *mdp4_kms = get_kms(crtc); in crtc_flush() local
96 mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush); in crtc_flush()
127 struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base); in unref_cursor_worker() local
129 msm_gem_put_iova(val, mdp4_kms->id); in unref_cursor_worker()
167 static void setup_mixer(struct mdp4_kms *mdp4_kms) in setup_mixer() argument
169 struct drm_mode_config *config = &mdp4_kms->dev->mode_config; in setup_mixer()
188 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg); in setup_mixer()
194 struct mdp4_kms *mdp4_kms = get_kms(crtc); in blend_setup() local
199 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0); in blend_setup()
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| D | mdp4_plane.c | 45 static struct mdp4_kms *get_kms(struct drm_plane *plane) in get_kms()
90 struct mdp4_kms *mdp4_kms = get_kms(plane); in mdp4_plane_prepare_fb() local
93 return msm_framebuffer_prepare(fb, mdp4_kms->id); in mdp4_plane_prepare_fb()
101 struct mdp4_kms *mdp4_kms = get_kms(plane); in mdp4_plane_cleanup_fb() local
104 msm_framebuffer_cleanup(fb, mdp4_kms->id); in mdp4_plane_cleanup_fb()
141 struct mdp4_kms *mdp4_kms = get_kms(plane); in mdp4_plane_set_scanout() local
144 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_A(pipe), in mdp4_plane_set_scanout()
148 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_B(pipe), in mdp4_plane_set_scanout()
152 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP0_BASE(pipe), in mdp4_plane_set_scanout()
153 msm_framebuffer_iova(fb, mdp4_kms->id, 0)); in mdp4_plane_set_scanout()
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| D | mdp4_lcdc_encoder.c | 35 static struct mdp4_kms *get_kms(struct drm_encoder *encoder) in get_kms()
111 struct mdp4_kms *mdp4_kms = get_kms(encoder); in setup_phy() local
129 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0), in setup_phy()
134 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(0), in setup_phy()
138 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(1), in setup_phy()
143 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(1), in setup_phy()
147 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(2), in setup_phy()
152 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(2), in setup_phy()
156 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(3), in setup_phy()
161 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(3), in setup_phy()
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| D | mdp4_dtv_encoder.c | 35 static struct mdp4_kms *get_kms(struct drm_encoder *encoder) in get_kms()
109 struct mdp4_kms *mdp4_kms = get_kms(encoder); in mdp4_dtv_encoder_mode_set() local
146 mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_CTRL, in mdp4_dtv_encoder_mode_set()
149 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_PERIOD, vsync_period); in mdp4_dtv_encoder_mode_set()
150 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_LEN, vsync_len); in mdp4_dtv_encoder_mode_set()
151 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_HCTRL, in mdp4_dtv_encoder_mode_set()
154 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VSTART, display_v_start); in mdp4_dtv_encoder_mode_set()
155 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VEND, display_v_end); in mdp4_dtv_encoder_mode_set()
156 mdp4_write(mdp4_kms, REG_MDP4_DTV_BORDER_CLR, 0); in mdp4_dtv_encoder_mode_set()
157 mdp4_write(mdp4_kms, REG_MDP4_DTV_UNDERFLOW_CLR, in mdp4_dtv_encoder_mode_set()
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| D | mdp4_lvds_pll.c | 30 static struct mdp4_kms *get_kms(struct mdp4_lvds_pll *lvds_pll) in get_kms()
71 struct mdp4_kms *mdp4_kms = get_kms(lvds_pll); in mpd4_lvds_pll_enable() local
80 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_PHY_RESET, 0x33); in mpd4_lvds_pll_enable()
83 mdp4_write(mdp4_kms, pll_rate->conf[i].reg, pll_rate->conf[i].val); in mpd4_lvds_pll_enable()
85 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x01); in mpd4_lvds_pll_enable()
88 while (!mdp4_read(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_LOCKED)) in mpd4_lvds_pll_enable()
97 struct mdp4_kms *mdp4_kms = get_kms(lvds_pll); in mpd4_lvds_pll_disable() local
101 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, 0x0); in mpd4_lvds_pll_disable()
102 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x0); in mpd4_lvds_pll_disable()
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| D | mdp4_kms.h | 28 struct mdp4_kms { struct
55 #define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base) argument
63 static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data) in mdp4_write() argument
65 msm_writel(data, mdp4_kms->mmio + reg); in mdp4_write()
68 static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg) in mdp4_read() argument
70 return msm_readl(mdp4_kms->mmio + reg); in mdp4_read()
167 int mdp4_disable(struct mdp4_kms *mdp4_kms);
168 int mdp4_enable(struct mdp4_kms *mdp4_kms);
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| /linux-4.1.27/drivers/gpu/drm/msm/ |
| D | Makefile | 29 mdp/mdp4/mdp4_kms.o \
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