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Searched refs:m_reg (Results 1 – 14 of 14) sorted by relevance

/linux-4.1.27/drivers/clk/qcom/
Dclk-pll.c101 regmap_read(pll->clkr.regmap, pll->m_reg, &m); in clk_pll_recalc_rate()
173 regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m); in clk_pll_set_rate()
258 regmap_write(regmap, pll->m_reg, config->m); in clk_pll_configure()
Dclk-pll.h49 u32 m_reg; member
Dlcc-ipq806x.c36 .m_reg = 0x8,
Dmmcc-msm8974.c190 .m_reg = 0x0008,
217 .m_reg = 0x0048,
244 .m_reg = 0x4108,
259 .m_reg = 0x0088,
Dgcc-ipq806x.c37 .m_reg = 0x30c8,
64 .m_reg = 0x3168,
91 .m_reg = 0x3148,
118 .m_reg = 0x31c8,
Dmmcc-apq8084.c225 .m_reg = 0x0008,
252 .m_reg = 0x0048,
279 .m_reg = 0x4108,
294 .m_reg = 0x0088,
310 .m_reg = 0x00a8,
Dlcc-msm8960.c36 .m_reg = 0x8,
Dgcc-msm8916.c197 .m_reg = 0x21008,
224 .m_reg = 0x20008,
251 .m_reg = 0x4a008,
278 .m_reg = 0x23008,
Dgcc-msm8974.c68 .m_reg = 0x0008,
131 .m_reg = 0x0048,
158 .m_reg = 0x1dc8,
Dgcc-apq8084.c112 .m_reg = 0x0008,
175 .m_reg = 0x0048,
202 .m_reg = 0x1dc8,
Dgcc-msm8960.c37 .m_reg = 0x3168,
64 .m_reg = 0x3148,
91 .m_reg = 0x31c8,
Dmmcc-msm8960.c89 .m_reg = 0x324,
105 .m_reg = 0x340,
Dgcc-msm8660.c37 .m_reg = 0x3148,
/linux-4.1.27/drivers/video/fbdev/i810/
Di810_main.c707 u32 m_reg, n_reg, p_divisor, n_target_max; in i810_calc_dclk() local
728 n_reg = m_reg = n_target = 3; in i810_calc_dclk()
730 f_out = (p_divisor * n_reg * 1000000)/(4 * 24 * m_reg); in i810_calc_dclk()
731 mod = (p_divisor * n_reg * 1000000) % (4 * 24 * m_reg); in i810_calc_dclk()
732 m_target = m_reg; in i810_calc_dclk()
738 m_reg++; in i810_calc_dclk()