1 /*
2  * R8A7740 processor support
3  *
4  * Copyright (C) 2011  Renesas Solutions Corp.
5  * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; version 2 of the
10  * License.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
20  */
21 #include <linux/io.h>
22 #include <linux/kernel.h>
23 #include <linux/pinctrl/pinconf-generic.h>
24 
25 #ifndef CONFIG_ARCH_MULTIPLATFORM
26 #include <mach/irqs.h>
27 #endif
28 
29 #include "core.h"
30 #include "sh_pfc.h"
31 
32 #define CPU_ALL_PORT(fn, pfx, sfx)					\
33 	PORT_10(0,  fn, pfx, sfx),	PORT_90(0,   fn, pfx, sfx),	\
34 	PORT_10(100, fn, pfx##10, sfx),	PORT_90(100, fn, pfx##1, sfx),	\
35 	PORT_10(200, fn, pfx##20, sfx),					\
36 	PORT_1(210, fn, pfx##210, sfx),	PORT_1(211, fn, pfx##211, sfx)
37 
38 #define IRQC_PIN_MUX(irq, pin)						\
39 static const unsigned int intc_irq##irq##_pins[] = {			\
40 	pin,								\
41 };									\
42 static const unsigned int intc_irq##irq##_mux[] = {			\
43 	IRQ##irq##_MARK,						\
44 }
45 
46 #define IRQC_PINS_MUX(irq, idx, pin)					\
47 static const unsigned int intc_irq##irq##_##idx##_pins[] = {		\
48 	pin,								\
49 };									\
50 static const unsigned int intc_irq##irq##_##idx##_mux[] = {		\
51 	IRQ##irq##_PORT##pin##_MARK,					\
52 }
53 
54 enum {
55 	PINMUX_RESERVED = 0,
56 
57 	/* PORT0_DATA -> PORT211_DATA */
58 	PINMUX_DATA_BEGIN,
59 	PORT_ALL(DATA),
60 	PINMUX_DATA_END,
61 
62 	/* PORT0_IN -> PORT211_IN */
63 	PINMUX_INPUT_BEGIN,
64 	PORT_ALL(IN),
65 	PINMUX_INPUT_END,
66 
67 	/* PORT0_OUT -> PORT211_OUT */
68 	PINMUX_OUTPUT_BEGIN,
69 	PORT_ALL(OUT),
70 	PINMUX_OUTPUT_END,
71 
72 	PINMUX_FUNCTION_BEGIN,
73 	PORT_ALL(FN_IN),	/* PORT0_FN_IN -> PORT211_FN_IN */
74 	PORT_ALL(FN_OUT),	/* PORT0_FN_OUT -> PORT211_FN_OUT */
75 	PORT_ALL(FN0),		/* PORT0_FN0 -> PORT211_FN0 */
76 	PORT_ALL(FN1),		/* PORT0_FN1 -> PORT211_FN1 */
77 	PORT_ALL(FN2),		/* PORT0_FN2 -> PORT211_FN2 */
78 	PORT_ALL(FN3),		/* PORT0_FN3 -> PORT211_FN3 */
79 	PORT_ALL(FN4),		/* PORT0_FN4 -> PORT211_FN4 */
80 	PORT_ALL(FN5),		/* PORT0_FN5 -> PORT211_FN5 */
81 	PORT_ALL(FN6),		/* PORT0_FN6 -> PORT211_FN6 */
82 	PORT_ALL(FN7),		/* PORT0_FN7 -> PORT211_FN7 */
83 
84 	MSEL1CR_31_0,	MSEL1CR_31_1,
85 	MSEL1CR_30_0,	MSEL1CR_30_1,
86 	MSEL1CR_29_0,	MSEL1CR_29_1,
87 	MSEL1CR_28_0,	MSEL1CR_28_1,
88 	MSEL1CR_27_0,	MSEL1CR_27_1,
89 	MSEL1CR_26_0,	MSEL1CR_26_1,
90 	MSEL1CR_16_0,	MSEL1CR_16_1,
91 	MSEL1CR_15_0,	MSEL1CR_15_1,
92 	MSEL1CR_14_0,	MSEL1CR_14_1,
93 	MSEL1CR_13_0,	MSEL1CR_13_1,
94 	MSEL1CR_12_0,	MSEL1CR_12_1,
95 	MSEL1CR_9_0,	MSEL1CR_9_1,
96 	MSEL1CR_7_0,	MSEL1CR_7_1,
97 	MSEL1CR_6_0,	MSEL1CR_6_1,
98 	MSEL1CR_5_0,	MSEL1CR_5_1,
99 	MSEL1CR_4_0,	MSEL1CR_4_1,
100 	MSEL1CR_3_0,	MSEL1CR_3_1,
101 	MSEL1CR_2_0,	MSEL1CR_2_1,
102 	MSEL1CR_0_0,	MSEL1CR_0_1,
103 
104 	MSEL3CR_15_0,	MSEL3CR_15_1, /* Trace / Debug ? */
105 	MSEL3CR_6_0,	MSEL3CR_6_1,
106 
107 	MSEL4CR_19_0,	MSEL4CR_19_1,
108 	MSEL4CR_18_0,	MSEL4CR_18_1,
109 	MSEL4CR_15_0,	MSEL4CR_15_1,
110 	MSEL4CR_10_0,	MSEL4CR_10_1,
111 	MSEL4CR_6_0,	MSEL4CR_6_1,
112 	MSEL4CR_4_0,	MSEL4CR_4_1,
113 	MSEL4CR_1_0,	MSEL4CR_1_1,
114 
115 	MSEL5CR_31_0,	MSEL5CR_31_1, /* irq/fiq output */
116 	MSEL5CR_30_0,	MSEL5CR_30_1,
117 	MSEL5CR_29_0,	MSEL5CR_29_1,
118 	MSEL5CR_27_0,	MSEL5CR_27_1,
119 	MSEL5CR_25_0,	MSEL5CR_25_1,
120 	MSEL5CR_23_0,	MSEL5CR_23_1,
121 	MSEL5CR_21_0,	MSEL5CR_21_1,
122 	MSEL5CR_19_0,	MSEL5CR_19_1,
123 	MSEL5CR_17_0,	MSEL5CR_17_1,
124 	MSEL5CR_15_0,	MSEL5CR_15_1,
125 	MSEL5CR_14_0,	MSEL5CR_14_1,
126 	MSEL5CR_13_0,	MSEL5CR_13_1,
127 	MSEL5CR_12_0,	MSEL5CR_12_1,
128 	MSEL5CR_11_0,	MSEL5CR_11_1,
129 	MSEL5CR_10_0,	MSEL5CR_10_1,
130 	MSEL5CR_8_0,	MSEL5CR_8_1,
131 	MSEL5CR_7_0,	MSEL5CR_7_1,
132 	MSEL5CR_6_0,	MSEL5CR_6_1,
133 	MSEL5CR_5_0,	MSEL5CR_5_1,
134 	MSEL5CR_4_0,	MSEL5CR_4_1,
135 	MSEL5CR_3_0,	MSEL5CR_3_1,
136 	MSEL5CR_2_0,	MSEL5CR_2_1,
137 	MSEL5CR_0_0,	MSEL5CR_0_1,
138 	PINMUX_FUNCTION_END,
139 
140 	PINMUX_MARK_BEGIN,
141 
142 	/* IRQ */
143 	IRQ0_PORT2_MARK,	IRQ0_PORT13_MARK,
144 	IRQ1_MARK,
145 	IRQ2_PORT11_MARK,	IRQ2_PORT12_MARK,
146 	IRQ3_PORT10_MARK,	IRQ3_PORT14_MARK,
147 	IRQ4_PORT15_MARK,	IRQ4_PORT172_MARK,
148 	IRQ5_PORT0_MARK,	IRQ5_PORT1_MARK,
149 	IRQ6_PORT121_MARK,	IRQ6_PORT173_MARK,
150 	IRQ7_PORT120_MARK,	IRQ7_PORT209_MARK,
151 	IRQ8_MARK,
152 	IRQ9_PORT118_MARK,	IRQ9_PORT210_MARK,
153 	IRQ10_MARK,
154 	IRQ11_MARK,
155 	IRQ12_PORT42_MARK,	IRQ12_PORT97_MARK,
156 	IRQ13_PORT64_MARK,	IRQ13_PORT98_MARK,
157 	IRQ14_PORT63_MARK,	IRQ14_PORT99_MARK,
158 	IRQ15_PORT62_MARK,	IRQ15_PORT100_MARK,
159 	IRQ16_PORT68_MARK,	IRQ16_PORT211_MARK,
160 	IRQ17_MARK,
161 	IRQ18_MARK,
162 	IRQ19_MARK,
163 	IRQ20_MARK,
164 	IRQ21_MARK,
165 	IRQ22_MARK,
166 	IRQ23_MARK,
167 	IRQ24_MARK,
168 	IRQ25_MARK,
169 	IRQ26_PORT58_MARK,	IRQ26_PORT81_MARK,
170 	IRQ27_PORT57_MARK,	IRQ27_PORT168_MARK,
171 	IRQ28_PORT56_MARK,	IRQ28_PORT169_MARK,
172 	IRQ29_PORT50_MARK,	IRQ29_PORT170_MARK,
173 	IRQ30_PORT49_MARK,	IRQ30_PORT171_MARK,
174 	IRQ31_PORT41_MARK,	IRQ31_PORT167_MARK,
175 
176 	/* Function */
177 
178 	/* DBGT */
179 	DBGMDT2_MARK,	DBGMDT1_MARK,	DBGMDT0_MARK,
180 	DBGMD10_MARK,	DBGMD11_MARK,	DBGMD20_MARK,
181 	DBGMD21_MARK,
182 
183 	/* FSI-A */
184 	FSIAISLD_PORT0_MARK,	/* FSIAISLD Port 0/5 */
185 	FSIAISLD_PORT5_MARK,
186 	FSIASPDIF_PORT9_MARK,	/* FSIASPDIF Port 9/18 */
187 	FSIASPDIF_PORT18_MARK,
188 	FSIAOSLD1_MARK,	FSIAOSLD2_MARK,	FSIAOLR_MARK,
189 	FSIAOBT_MARK,	FSIAOSLD_MARK,	FSIAOMC_MARK,
190 	FSIACK_MARK,	FSIAILR_MARK,	FSIAIBT_MARK,
191 
192 	/* FSI-B */
193 	FSIBCK_MARK,
194 
195 	/* FMSI */
196 	FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
197 	FMSISLD_PORT6_MARK,
198 	FMSIILR_MARK,	FMSIIBT_MARK,	FMSIOLR_MARK,	FMSIOBT_MARK,
199 	FMSICK_MARK,	FMSOILR_MARK,	FMSOIBT_MARK,	FMSOOLR_MARK,
200 	FMSOOBT_MARK,	FMSOSLD_MARK,	FMSOCK_MARK,
201 
202 	/* SCIFA0 */
203 	SCIFA0_SCK_MARK,	SCIFA0_CTS_MARK,	SCIFA0_RTS_MARK,
204 	SCIFA0_RXD_MARK,	SCIFA0_TXD_MARK,
205 
206 	/* SCIFA1 */
207 	SCIFA1_CTS_MARK,	SCIFA1_SCK_MARK,	SCIFA1_RXD_MARK,
208 	SCIFA1_TXD_MARK,	SCIFA1_RTS_MARK,
209 
210 	/* SCIFA2 */
211 	SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
212 	SCIFA2_SCK_PORT199_MARK,
213 	SCIFA2_RXD_MARK,	SCIFA2_TXD_MARK,
214 	SCIFA2_CTS_MARK,	SCIFA2_RTS_MARK,
215 
216 	/* SCIFA3 */
217 	SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
218 	SCIFA3_SCK_PORT116_MARK,
219 	SCIFA3_CTS_PORT117_MARK,
220 	SCIFA3_RXD_PORT174_MARK,
221 	SCIFA3_TXD_PORT175_MARK,
222 
223 	SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
224 	SCIFA3_SCK_PORT158_MARK,
225 	SCIFA3_CTS_PORT162_MARK,
226 	SCIFA3_RXD_PORT159_MARK,
227 	SCIFA3_TXD_PORT160_MARK,
228 
229 	/* SCIFA4 */
230 	SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
231 	SCIFA4_TXD_PORT13_MARK,
232 
233 	SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
234 	SCIFA4_TXD_PORT203_MARK,
235 
236 	SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
237 	SCIFA4_TXD_PORT93_MARK,
238 
239 	SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
240 	SCIFA4_SCK_PORT205_MARK,
241 
242 	/* SCIFA5 */
243 	SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
244 	SCIFA5_RXD_PORT10_MARK,
245 
246 	SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
247 	SCIFA5_TXD_PORT208_MARK,
248 
249 	SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
250 	SCIFA5_RXD_PORT92_MARK,
251 
252 	SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
253 	SCIFA5_SCK_PORT206_MARK,
254 
255 	/* SCIFA6 */
256 	SCIFA6_SCK_MARK,	SCIFA6_RXD_MARK,	SCIFA6_TXD_MARK,
257 
258 	/* SCIFA7 */
259 	SCIFA7_TXD_MARK,	SCIFA7_RXD_MARK,
260 
261 	/* SCIFAB */
262 	SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
263 	SCIFB_RXD_PORT191_MARK,
264 	SCIFB_TXD_PORT192_MARK,
265 	SCIFB_RTS_PORT186_MARK,
266 	SCIFB_CTS_PORT187_MARK,
267 
268 	SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
269 	SCIFB_RXD_PORT3_MARK,
270 	SCIFB_TXD_PORT4_MARK,
271 	SCIFB_RTS_PORT172_MARK,
272 	SCIFB_CTS_PORT173_MARK,
273 
274 	/* LCD0 */
275 	LCD0_D0_MARK,	LCD0_D1_MARK,	LCD0_D2_MARK,	LCD0_D3_MARK,
276 	LCD0_D4_MARK,	LCD0_D5_MARK,	LCD0_D6_MARK,	LCD0_D7_MARK,
277 	LCD0_D8_MARK,	LCD0_D9_MARK,	LCD0_D10_MARK,	LCD0_D11_MARK,
278 	LCD0_D12_MARK,	LCD0_D13_MARK,	LCD0_D14_MARK,	LCD0_D15_MARK,
279 	LCD0_D16_MARK,	LCD0_D17_MARK,
280 	LCD0_DON_MARK,	LCD0_VCPWC_MARK,	LCD0_VEPWC_MARK,
281 	LCD0_DCK_MARK,	LCD0_VSYN_MARK,	/* for RGB */
282 	LCD0_HSYN_MARK,	LCD0_DISP_MARK,	/* for RGB */
283 	LCD0_WR_MARK,	LCD0_RD_MARK,	/* for SYS */
284 	LCD0_CS_MARK,	LCD0_RS_MARK,	/* for SYS */
285 
286 	LCD0_D21_PORT158_MARK,	LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
287 	LCD0_D22_PORT160_MARK,	LCD0_D20_PORT161_MARK,
288 	LCD0_D19_PORT162_MARK,	LCD0_D18_PORT163_MARK,
289 	LCD0_LCLK_PORT165_MARK,
290 
291 	LCD0_D18_PORT40_MARK,	LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
292 	LCD0_D23_PORT1_MARK,	LCD0_D21_PORT2_MARK,
293 	LCD0_D20_PORT3_MARK,	LCD0_D19_PORT4_MARK,
294 	LCD0_LCLK_PORT102_MARK,
295 
296 	/* LCD1 */
297 	LCD1_D0_MARK,	LCD1_D1_MARK,	LCD1_D2_MARK,	LCD1_D3_MARK,
298 	LCD1_D4_MARK,	LCD1_D5_MARK,	LCD1_D6_MARK,	LCD1_D7_MARK,
299 	LCD1_D8_MARK,	LCD1_D9_MARK,	LCD1_D10_MARK,	LCD1_D11_MARK,
300 	LCD1_D12_MARK,	LCD1_D13_MARK,	LCD1_D14_MARK,	LCD1_D15_MARK,
301 	LCD1_D16_MARK,	LCD1_D17_MARK,	LCD1_D18_MARK,	LCD1_D19_MARK,
302 	LCD1_D20_MARK,	LCD1_D21_MARK,	LCD1_D22_MARK,	LCD1_D23_MARK,
303 	LCD1_DON_MARK,	LCD1_VCPWC_MARK,
304 	LCD1_LCLK_MARK,	LCD1_VEPWC_MARK,
305 
306 	LCD1_DCK_MARK,	LCD1_VSYN_MARK,	/* for RGB */
307 	LCD1_HSYN_MARK,	LCD1_DISP_MARK,	/* for RGB */
308 	LCD1_RS_MARK,	LCD1_CS_MARK,	/* for SYS */
309 	LCD1_RD_MARK,	LCD1_WR_MARK,	/* for SYS */
310 
311 	/* RSPI */
312 	RSPI_SSL0_A_MARK,	RSPI_SSL1_A_MARK,	RSPI_SSL2_A_MARK,
313 	RSPI_SSL3_A_MARK,	RSPI_CK_A_MARK,		RSPI_MOSI_A_MARK,
314 	RSPI_MISO_A_MARK,
315 
316 	/* VIO CKO */
317 	VIO_CKO1_MARK, /* needs fixup */
318 	VIO_CKO2_MARK,
319 	VIO_CKO_1_MARK,
320 	VIO_CKO_MARK,
321 
322 	/* VIO0 */
323 	VIO0_D0_MARK,	VIO0_D1_MARK,	VIO0_D2_MARK,	VIO0_D3_MARK,
324 	VIO0_D4_MARK,	VIO0_D5_MARK,	VIO0_D6_MARK,	VIO0_D7_MARK,
325 	VIO0_D8_MARK,	VIO0_D9_MARK,	VIO0_D10_MARK,	VIO0_D11_MARK,
326 	VIO0_D12_MARK,	VIO0_VD_MARK,	VIO0_HD_MARK,	VIO0_CLK_MARK,
327 	VIO0_FIELD_MARK,
328 
329 	VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
330 	VIO0_D14_PORT25_MARK,
331 	VIO0_D15_PORT24_MARK,
332 
333 	VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
334 	VIO0_D14_PORT95_MARK,
335 	VIO0_D15_PORT96_MARK,
336 
337 	/* VIO1 */
338 	VIO1_D0_MARK,	VIO1_D1_MARK,	VIO1_D2_MARK,	VIO1_D3_MARK,
339 	VIO1_D4_MARK,	VIO1_D5_MARK,	VIO1_D6_MARK,	VIO1_D7_MARK,
340 	VIO1_VD_MARK,	VIO1_HD_MARK,	VIO1_CLK_MARK,	VIO1_FIELD_MARK,
341 
342 	/* TPU0 */
343 	TPU0TO0_MARK,	TPU0TO1_MARK,	TPU0TO3_MARK,
344 	TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
345 	TPU0TO2_PORT202_MARK,
346 
347 	/* SSP1 0 */
348 	STP0_IPD0_MARK,	STP0_IPD1_MARK,	STP0_IPD2_MARK,	STP0_IPD3_MARK,
349 	STP0_IPD4_MARK,	STP0_IPD5_MARK,	STP0_IPD6_MARK,	STP0_IPD7_MARK,
350 	STP0_IPEN_MARK,	STP0_IPCLK_MARK,	STP0_IPSYNC_MARK,
351 
352 	/* SSP1 1 */
353 	STP1_IPD1_MARK,	STP1_IPD2_MARK,	STP1_IPD3_MARK,	STP1_IPD4_MARK,
354 	STP1_IPD5_MARK,	STP1_IPD6_MARK,	STP1_IPD7_MARK,	STP1_IPCLK_MARK,
355 	STP1_IPSYNC_MARK,
356 
357 	STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
358 	STP1_IPEN_PORT187_MARK,
359 
360 	STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
361 	STP1_IPEN_PORT193_MARK,
362 
363 	/* SIM */
364 	SIM_RST_MARK,	SIM_CLK_MARK,
365 	SIM_D_PORT22_MARK, /* SIM_D  Port 22/199 */
366 	SIM_D_PORT199_MARK,
367 
368 	/* SDHI0 */
369 	SDHI0_D0_MARK,	SDHI0_D1_MARK,	SDHI0_D2_MARK,	SDHI0_D3_MARK,
370 	SDHI0_CD_MARK,	SDHI0_WP_MARK,	SDHI0_CMD_MARK,	SDHI0_CLK_MARK,
371 
372 	/* SDHI1 */
373 	SDHI1_D0_MARK,	SDHI1_D1_MARK,	SDHI1_D2_MARK,	SDHI1_D3_MARK,
374 	SDHI1_CD_MARK,	SDHI1_WP_MARK,	SDHI1_CMD_MARK,	SDHI1_CLK_MARK,
375 
376 	/* SDHI2 */
377 	SDHI2_D0_MARK,	SDHI2_D1_MARK,	SDHI2_D2_MARK,	SDHI2_D3_MARK,
378 	SDHI2_CLK_MARK,	SDHI2_CMD_MARK,
379 
380 	SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
381 	SDHI2_WP_PORT25_MARK,
382 
383 	SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
384 	SDHI2_CD_PORT202_MARK,
385 
386 	/* MSIOF2 */
387 	MSIOF2_TXD_MARK,	MSIOF2_RXD_MARK,	MSIOF2_TSCK_MARK,
388 	MSIOF2_SS2_MARK,	MSIOF2_TSYNC_MARK,	MSIOF2_SS1_MARK,
389 	MSIOF2_MCK1_MARK,	MSIOF2_MCK0_MARK,	MSIOF2_RSYNC_MARK,
390 	MSIOF2_RSCK_MARK,
391 
392 	/* KEYSC */
393 	KEYIN4_MARK,	KEYIN5_MARK,	KEYIN6_MARK,	KEYIN7_MARK,
394 	KEYOUT0_MARK,	KEYOUT1_MARK,	KEYOUT2_MARK,	KEYOUT3_MARK,
395 	KEYOUT4_MARK,	KEYOUT5_MARK,	KEYOUT6_MARK,	KEYOUT7_MARK,
396 
397 	KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
398 	KEYIN1_PORT44_MARK,
399 	KEYIN2_PORT45_MARK,
400 	KEYIN3_PORT46_MARK,
401 
402 	KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
403 	KEYIN1_PORT57_MARK,
404 	KEYIN2_PORT56_MARK,
405 	KEYIN3_PORT55_MARK,
406 
407 	/* VOU */
408 	DV_D0_MARK,	DV_D1_MARK,	DV_D2_MARK,	DV_D3_MARK,
409 	DV_D4_MARK,	DV_D5_MARK,	DV_D6_MARK,	DV_D7_MARK,
410 	DV_D8_MARK,	DV_D9_MARK,	DV_D10_MARK,	DV_D11_MARK,
411 	DV_D12_MARK,	DV_D13_MARK,	DV_D14_MARK,	DV_D15_MARK,
412 	DV_CLK_MARK,	DV_VSYNC_MARK,	DV_HSYNC_MARK,
413 
414 	/* MEMC */
415 	MEMC_AD0_MARK,	MEMC_AD1_MARK,	MEMC_AD2_MARK,	MEMC_AD3_MARK,
416 	MEMC_AD4_MARK,	MEMC_AD5_MARK,	MEMC_AD6_MARK,	MEMC_AD7_MARK,
417 	MEMC_AD8_MARK,	MEMC_AD9_MARK,	MEMC_AD10_MARK,	MEMC_AD11_MARK,
418 	MEMC_AD12_MARK,	MEMC_AD13_MARK,	MEMC_AD14_MARK,	MEMC_AD15_MARK,
419 	MEMC_CS0_MARK,	MEMC_INT_MARK,	MEMC_NWE_MARK,	MEMC_NOE_MARK,
420 
421 	MEMC_CS1_MARK, /* MSEL4CR_6_0 */
422 	MEMC_ADV_MARK,
423 	MEMC_WAIT_MARK,
424 	MEMC_BUSCLK_MARK,
425 
426 	MEMC_A1_MARK, /* MSEL4CR_6_1 */
427 	MEMC_DREQ0_MARK,
428 	MEMC_DREQ1_MARK,
429 	MEMC_A0_MARK,
430 
431 	/* MMC */
432 	MMC0_D0_PORT68_MARK,	MMC0_D1_PORT69_MARK,	MMC0_D2_PORT70_MARK,
433 	MMC0_D3_PORT71_MARK,	MMC0_D4_PORT72_MARK,	MMC0_D5_PORT73_MARK,
434 	MMC0_D6_PORT74_MARK,	MMC0_D7_PORT75_MARK,	MMC0_CLK_PORT66_MARK,
435 	MMC0_CMD_PORT67_MARK,	/* MSEL4CR_15_0 */
436 
437 	MMC1_D0_PORT149_MARK,	MMC1_D1_PORT148_MARK,	MMC1_D2_PORT147_MARK,
438 	MMC1_D3_PORT146_MARK,	MMC1_D4_PORT145_MARK,	MMC1_D5_PORT144_MARK,
439 	MMC1_D6_PORT143_MARK,	MMC1_D7_PORT142_MARK,	MMC1_CLK_PORT103_MARK,
440 	MMC1_CMD_PORT104_MARK,	/* MSEL4CR_15_1 */
441 
442 	/* MSIOF0 */
443 	MSIOF0_SS1_MARK,	MSIOF0_SS2_MARK,	MSIOF0_RXD_MARK,
444 	MSIOF0_TXD_MARK,	MSIOF0_MCK0_MARK,	MSIOF0_MCK1_MARK,
445 	MSIOF0_RSYNC_MARK,	MSIOF0_RSCK_MARK,	MSIOF0_TSCK_MARK,
446 	MSIOF0_TSYNC_MARK,
447 
448 	/* MSIOF1 */
449 	MSIOF1_RSCK_MARK,	MSIOF1_RSYNC_MARK,
450 	MSIOF1_MCK0_MARK,	MSIOF1_MCK1_MARK,
451 
452 	MSIOF1_SS2_PORT116_MARK,	MSIOF1_SS1_PORT117_MARK,
453 	MSIOF1_RXD_PORT118_MARK,	MSIOF1_TXD_PORT119_MARK,
454 	MSIOF1_TSYNC_PORT120_MARK,
455 	MSIOF1_TSCK_PORT121_MARK,	/* MSEL4CR_10_0 */
456 
457 	MSIOF1_SS1_PORT67_MARK,		MSIOF1_TSCK_PORT72_MARK,
458 	MSIOF1_TSYNC_PORT73_MARK,	MSIOF1_TXD_PORT74_MARK,
459 	MSIOF1_RXD_PORT75_MARK,
460 	MSIOF1_SS2_PORT202_MARK,	/* MSEL4CR_10_1 */
461 
462 	/* GPIO */
463 	GPO0_MARK,	GPI0_MARK,	GPO1_MARK,	GPI1_MARK,
464 
465 	/* USB0 */
466 	USB0_OCI_MARK,	USB0_PPON_MARK,	VBUS_MARK,
467 
468 	/* USB1 */
469 	USB1_OCI_MARK,	USB1_PPON_MARK,
470 
471 	/* BBIF1 */
472 	BBIF1_RXD_MARK,		BBIF1_TXD_MARK,		BBIF1_TSYNC_MARK,
473 	BBIF1_TSCK_MARK,	BBIF1_RSCK_MARK,	BBIF1_RSYNC_MARK,
474 	BBIF1_FLOW_MARK,	BBIF1_RX_FLOW_N_MARK,
475 
476 	/* BBIF2 */
477 	BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
478 	BBIF2_RXD2_PORT60_MARK,
479 	BBIF2_TSYNC2_PORT6_MARK,
480 	BBIF2_TSCK2_PORT59_MARK,
481 
482 	BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
483 	BBIF2_TXD2_PORT183_MARK,
484 	BBIF2_TSCK2_PORT89_MARK,
485 	BBIF2_TSYNC2_PORT184_MARK,
486 
487 	/* BSC / FLCTL / PCMCIA */
488 	CS0_MARK,	CS2_MARK,	CS4_MARK,
489 	CS5B_MARK,	CS6A_MARK,
490 	CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
491 	CS5A_PORT19_MARK,
492 	IOIS16_MARK, /* ? */
493 
494 	A0_MARK,	A1_MARK,	A2_MARK,	A3_MARK,
495 	A4_FOE_MARK,	/* share with FLCTL */
496 	A5_FCDE_MARK,	/* share with FLCTL */
497 	A6_MARK,	A7_MARK,	A8_MARK,	A9_MARK,
498 	A10_MARK,	A11_MARK,	A12_MARK,	A13_MARK,
499 	A14_MARK,	A15_MARK,	A16_MARK,	A17_MARK,
500 	A18_MARK,	A19_MARK,	A20_MARK,	A21_MARK,
501 	A22_MARK,	A23_MARK,	A24_MARK,	A25_MARK,
502 	A26_MARK,
503 
504 	D0_NAF0_MARK,	D1_NAF1_MARK,	D2_NAF2_MARK,	/* share with FLCTL */
505 	D3_NAF3_MARK,	D4_NAF4_MARK,	D5_NAF5_MARK,	/* share with FLCTL */
506 	D6_NAF6_MARK,	D7_NAF7_MARK,	D8_NAF8_MARK,	/* share with FLCTL */
507 	D9_NAF9_MARK,	D10_NAF10_MARK,	D11_NAF11_MARK,	/* share with FLCTL */
508 	D12_NAF12_MARK,	D13_NAF13_MARK,	D14_NAF14_MARK,	/* share with FLCTL */
509 	D15_NAF15_MARK,					/* share with FLCTL */
510 	D16_MARK,	D17_MARK,	D18_MARK,	D19_MARK,
511 	D20_MARK,	D21_MARK,	D22_MARK,	D23_MARK,
512 	D24_MARK,	D25_MARK,	D26_MARK,	D27_MARK,
513 	D28_MARK,	D29_MARK,	D30_MARK,	D31_MARK,
514 
515 	WE0_FWE_MARK,	/* share with FLCTL */
516 	WE1_MARK,
517 	WE2_ICIORD_MARK,	/* share with PCMCIA */
518 	WE3_ICIOWR_MARK,	/* share with PCMCIA */
519 	CKO_MARK,	BS_MARK,	RDWR_MARK,
520 	RD_FSC_MARK,	/* share with FLCTL */
521 	WAIT_PORT177_MARK, /* WAIT Port 90/177 */
522 	WAIT_PORT90_MARK,
523 
524 	FCE0_MARK,	FCE1_MARK,	FRB_MARK, /* FLCTL */
525 
526 	/* IRDA */
527 	IRDA_FIRSEL_MARK,	IRDA_IN_MARK,	IRDA_OUT_MARK,
528 
529 	/* ATAPI */
530 	IDE_D0_MARK,	IDE_D1_MARK,	IDE_D2_MARK,	IDE_D3_MARK,
531 	IDE_D4_MARK,	IDE_D5_MARK,	IDE_D6_MARK,	IDE_D7_MARK,
532 	IDE_D8_MARK,	IDE_D9_MARK,	IDE_D10_MARK,	IDE_D11_MARK,
533 	IDE_D12_MARK,	IDE_D13_MARK,	IDE_D14_MARK,	IDE_D15_MARK,
534 	IDE_A0_MARK,	IDE_A1_MARK,	IDE_A2_MARK,	IDE_CS0_MARK,
535 	IDE_CS1_MARK,	IDE_IOWR_MARK,	IDE_IORD_MARK,	IDE_IORDY_MARK,
536 	IDE_INT_MARK,		IDE_RST_MARK,		IDE_DIRECTION_MARK,
537 	IDE_EXBUF_ENB_MARK,	IDE_IODACK_MARK,	IDE_IODREQ_MARK,
538 
539 	/* RMII */
540 	RMII_CRS_DV_MARK,	RMII_RX_ER_MARK,	RMII_RXD0_MARK,
541 	RMII_RXD1_MARK,		RMII_TX_EN_MARK,	RMII_TXD0_MARK,
542 	RMII_MDC_MARK,		RMII_TXD1_MARK,		RMII_MDIO_MARK,
543 	RMII_REF50CK_MARK,	/* for RMII */
544 	RMII_REF125CK_MARK,	/* for GMII */
545 
546 	/* GEther */
547 	ET_TX_CLK_MARK,	ET_TX_EN_MARK,	ET_ETXD0_MARK,	ET_ETXD1_MARK,
548 	ET_ETXD2_MARK,	ET_ETXD3_MARK,
549 	ET_ETXD4_MARK,	ET_ETXD5_MARK, /* for GEther */
550 	ET_ETXD6_MARK,	ET_ETXD7_MARK, /* for GEther */
551 	ET_COL_MARK,	ET_TX_ER_MARK,	ET_RX_CLK_MARK,	ET_RX_DV_MARK,
552 	ET_ERXD0_MARK,	ET_ERXD1_MARK,	ET_ERXD2_MARK,	ET_ERXD3_MARK,
553 	ET_ERXD4_MARK,	ET_ERXD5_MARK, /* for GEther */
554 	ET_ERXD6_MARK,	ET_ERXD7_MARK, /* for GEther */
555 	ET_RX_ER_MARK,	ET_CRS_MARK,		ET_MDC_MARK,	ET_MDIO_MARK,
556 	ET_LINK_MARK,	ET_PHY_INT_MARK,	ET_WOL_MARK,	ET_GTX_CLK_MARK,
557 
558 	/* DMA0 */
559 	DREQ0_MARK,	DACK0_MARK,
560 
561 	/* DMA1 */
562 	DREQ1_MARK,	DACK1_MARK,
563 
564 	/* SYSC */
565 	RESETOUTS_MARK,		RESETP_PULLUP_MARK,	RESETP_PLAIN_MARK,
566 
567 	/* IRREM */
568 	IROUT_MARK,
569 
570 	/* SDENC */
571 	SDENC_CPG_MARK,		SDENC_DV_CLKI_MARK,
572 
573 	/* HDMI */
574 	HDMI_HPD_MARK, HDMI_CEC_MARK,
575 
576 	/* DEBUG */
577 	EDEBGREQ_PULLUP_MARK,	/* for JTAG */
578 	EDEBGREQ_PULLDOWN_MARK,
579 
580 	TRACEAUD_FROM_VIO_MARK,	/* for TRACE/AUD */
581 	TRACEAUD_FROM_LCDC0_MARK,
582 	TRACEAUD_FROM_MEMC_MARK,
583 
584 	PINMUX_MARK_END,
585 };
586 
587 static const u16 pinmux_data[] = {
588 	PINMUX_DATA_ALL(),
589 
590 	/* Port0 */
591 	PINMUX_DATA(DBGMDT2_MARK,		PORT0_FN1),
592 	PINMUX_DATA(FSIAISLD_PORT0_MARK,	PORT0_FN2,	MSEL5CR_3_0),
593 	PINMUX_DATA(FSIAOSLD1_MARK,		PORT0_FN3),
594 	PINMUX_DATA(LCD0_D22_PORT0_MARK,	PORT0_FN4,	MSEL5CR_6_0),
595 	PINMUX_DATA(SCIFA7_RXD_MARK,		PORT0_FN6),
596 	PINMUX_DATA(LCD1_D4_MARK,		PORT0_FN7),
597 	PINMUX_DATA(IRQ5_PORT0_MARK,		PORT0_FN0,	MSEL1CR_5_0),
598 
599 	/* Port1 */
600 	PINMUX_DATA(DBGMDT1_MARK,		PORT1_FN1),
601 	PINMUX_DATA(FMSISLD_PORT1_MARK,		PORT1_FN2,	MSEL5CR_5_0),
602 	PINMUX_DATA(FSIAOSLD2_MARK,		PORT1_FN3),
603 	PINMUX_DATA(LCD0_D23_PORT1_MARK,	PORT1_FN4,	MSEL5CR_6_0),
604 	PINMUX_DATA(SCIFA7_TXD_MARK,		PORT1_FN6),
605 	PINMUX_DATA(LCD1_D3_MARK,		PORT1_FN7),
606 	PINMUX_DATA(IRQ5_PORT1_MARK,		PORT1_FN0,	MSEL1CR_5_1),
607 
608 	/* Port2 */
609 	PINMUX_DATA(DBGMDT0_MARK,		PORT2_FN1),
610 	PINMUX_DATA(SCIFB_SCK_PORT2_MARK,	PORT2_FN2,	MSEL5CR_17_1),
611 	PINMUX_DATA(LCD0_D21_PORT2_MARK,	PORT2_FN4,	MSEL5CR_6_0),
612 	PINMUX_DATA(LCD1_D2_MARK,		PORT2_FN7),
613 	PINMUX_DATA(IRQ0_PORT2_MARK,		PORT2_FN0,	MSEL1CR_0_1),
614 
615 	/* Port3 */
616 	PINMUX_DATA(DBGMD21_MARK,		PORT3_FN1),
617 	PINMUX_DATA(SCIFB_RXD_PORT3_MARK,	PORT3_FN2,	MSEL5CR_17_1),
618 	PINMUX_DATA(LCD0_D20_PORT3_MARK,	PORT3_FN4,	MSEL5CR_6_0),
619 	PINMUX_DATA(LCD1_D1_MARK,		PORT3_FN7),
620 
621 	/* Port4 */
622 	PINMUX_DATA(DBGMD20_MARK,		PORT4_FN1),
623 	PINMUX_DATA(SCIFB_TXD_PORT4_MARK,	PORT4_FN2,	MSEL5CR_17_1),
624 	PINMUX_DATA(LCD0_D19_PORT4_MARK,	PORT4_FN4,	MSEL5CR_6_0),
625 	PINMUX_DATA(LCD1_D0_MARK,		PORT4_FN7),
626 
627 	/* Port5 */
628 	PINMUX_DATA(DBGMD11_MARK,		PORT5_FN1),
629 	PINMUX_DATA(BBIF2_TXD2_PORT5_MARK,	PORT5_FN2,	MSEL5CR_0_0),
630 	PINMUX_DATA(FSIAISLD_PORT5_MARK,	PORT5_FN4,	MSEL5CR_3_1),
631 	PINMUX_DATA(RSPI_SSL0_A_MARK,		PORT5_FN6),
632 	PINMUX_DATA(LCD1_VCPWC_MARK,		PORT5_FN7),
633 
634 	/* Port6 */
635 	PINMUX_DATA(DBGMD10_MARK,		PORT6_FN1),
636 	PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK,	PORT6_FN2,	MSEL5CR_0_0),
637 	PINMUX_DATA(FMSISLD_PORT6_MARK,		PORT6_FN4,	MSEL5CR_5_1),
638 	PINMUX_DATA(RSPI_SSL1_A_MARK,		PORT6_FN6),
639 	PINMUX_DATA(LCD1_VEPWC_MARK,		PORT6_FN7),
640 
641 	/* Port7 */
642 	PINMUX_DATA(FSIAOLR_MARK,		PORT7_FN1),
643 
644 	/* Port8 */
645 	PINMUX_DATA(FSIAOBT_MARK,		PORT8_FN1),
646 
647 	/* Port9 */
648 	PINMUX_DATA(FSIAOSLD_MARK,		PORT9_FN1),
649 	PINMUX_DATA(FSIASPDIF_PORT9_MARK,	PORT9_FN2,	MSEL5CR_4_0),
650 
651 	/* Port10 */
652 	PINMUX_DATA(FSIAOMC_MARK,		PORT10_FN1),
653 	PINMUX_DATA(SCIFA5_RXD_PORT10_MARK,	PORT10_FN3,	MSEL5CR_14_0,	MSEL5CR_15_0),
654 	PINMUX_DATA(IRQ3_PORT10_MARK,		PORT10_FN0,	MSEL1CR_3_0),
655 
656 	/* Port11 */
657 	PINMUX_DATA(FSIACK_MARK,		PORT11_FN1),
658 	PINMUX_DATA(FSIBCK_MARK,		PORT11_FN2),
659 	PINMUX_DATA(IRQ2_PORT11_MARK,		PORT11_FN0,	MSEL1CR_2_0),
660 
661 	/* Port12 */
662 	PINMUX_DATA(FSIAILR_MARK,		PORT12_FN1),
663 	PINMUX_DATA(SCIFA4_RXD_PORT12_MARK,	PORT12_FN2,	MSEL5CR_12_0,	MSEL5CR_11_0),
664 	PINMUX_DATA(LCD1_RS_MARK,		PORT12_FN6),
665 	PINMUX_DATA(LCD1_DISP_MARK,		PORT12_FN7),
666 	PINMUX_DATA(IRQ2_PORT12_MARK,		PORT12_FN0,	MSEL1CR_2_1),
667 
668 	/* Port13 */
669 	PINMUX_DATA(FSIAIBT_MARK,		PORT13_FN1),
670 	PINMUX_DATA(SCIFA4_TXD_PORT13_MARK,	PORT13_FN2,	MSEL5CR_12_0,	MSEL5CR_11_0),
671 	PINMUX_DATA(LCD1_RD_MARK,		PORT13_FN7),
672 	PINMUX_DATA(IRQ0_PORT13_MARK,		PORT13_FN0,	MSEL1CR_0_0),
673 
674 	/* Port14 */
675 	PINMUX_DATA(FMSOILR_MARK,		PORT14_FN1),
676 	PINMUX_DATA(FMSIILR_MARK,		PORT14_FN2),
677 	PINMUX_DATA(VIO_CKO1_MARK,		PORT14_FN3),
678 	PINMUX_DATA(LCD1_D23_MARK,		PORT14_FN7),
679 	PINMUX_DATA(IRQ3_PORT14_MARK,		PORT14_FN0,	MSEL1CR_3_1),
680 
681 	/* Port15 */
682 	PINMUX_DATA(FMSOIBT_MARK,		PORT15_FN1),
683 	PINMUX_DATA(FMSIIBT_MARK,		PORT15_FN2),
684 	PINMUX_DATA(VIO_CKO2_MARK,		PORT15_FN3),
685 	PINMUX_DATA(LCD1_D22_MARK,		PORT15_FN7),
686 	PINMUX_DATA(IRQ4_PORT15_MARK,		PORT15_FN0,	MSEL1CR_4_0),
687 
688 	/* Port16 */
689 	PINMUX_DATA(FMSOOLR_MARK,		PORT16_FN1),
690 	PINMUX_DATA(FMSIOLR_MARK,		PORT16_FN2),
691 
692 	/* Port17 */
693 	PINMUX_DATA(FMSOOBT_MARK,		PORT17_FN1),
694 	PINMUX_DATA(FMSIOBT_MARK,		PORT17_FN2),
695 
696 	/* Port18 */
697 	PINMUX_DATA(FMSOSLD_MARK,		PORT18_FN1),
698 	PINMUX_DATA(FSIASPDIF_PORT18_MARK,	PORT18_FN2,	MSEL5CR_4_1),
699 
700 	/* Port19 */
701 	PINMUX_DATA(FMSICK_MARK,		PORT19_FN1),
702 	PINMUX_DATA(CS5A_PORT19_MARK,		PORT19_FN7,	MSEL5CR_2_1),
703 	PINMUX_DATA(IRQ10_MARK,			PORT19_FN0),
704 
705 	/* Port20 */
706 	PINMUX_DATA(FMSOCK_MARK,		PORT20_FN1),
707 	PINMUX_DATA(SCIFA5_TXD_PORT20_MARK,	PORT20_FN3,	MSEL5CR_15_0,	MSEL5CR_14_0),
708 	PINMUX_DATA(IRQ1_MARK,			PORT20_FN0),
709 
710 	/* Port21 */
711 	PINMUX_DATA(SCIFA1_CTS_MARK,		PORT21_FN1),
712 	PINMUX_DATA(SCIFA4_SCK_PORT21_MARK,	PORT21_FN2,	MSEL5CR_10_0),
713 	PINMUX_DATA(TPU0TO1_MARK,		PORT21_FN4),
714 	PINMUX_DATA(VIO1_FIELD_MARK,		PORT21_FN5),
715 	PINMUX_DATA(STP0_IPD5_MARK,		PORT21_FN6),
716 	PINMUX_DATA(LCD1_D10_MARK,		PORT21_FN7),
717 
718 	/* Port22 */
719 	PINMUX_DATA(SCIFA2_SCK_PORT22_MARK,	PORT22_FN1,	MSEL5CR_7_0),
720 	PINMUX_DATA(SIM_D_PORT22_MARK,		PORT22_FN4,	MSEL5CR_21_0),
721 	PINMUX_DATA(VIO0_D13_PORT22_MARK,	PORT22_FN7,	MSEL5CR_27_1),
722 
723 	/* Port23 */
724 	PINMUX_DATA(SCIFA1_RTS_MARK,		PORT23_FN1),
725 	PINMUX_DATA(SCIFA5_SCK_PORT23_MARK,	PORT23_FN3,	MSEL5CR_13_0),
726 	PINMUX_DATA(TPU0TO0_MARK,		PORT23_FN4),
727 	PINMUX_DATA(VIO_CKO_1_MARK,		PORT23_FN5),
728 	PINMUX_DATA(STP0_IPD2_MARK,		PORT23_FN6),
729 	PINMUX_DATA(LCD1_D7_MARK,		PORT23_FN7),
730 
731 	/* Port24 */
732 	PINMUX_DATA(VIO0_D15_PORT24_MARK,	PORT24_FN1,	MSEL5CR_27_0),
733 	PINMUX_DATA(VIO1_D7_MARK,		PORT24_FN5),
734 	PINMUX_DATA(SCIFA6_SCK_MARK,		PORT24_FN6),
735 	PINMUX_DATA(SDHI2_CD_PORT24_MARK,	PORT24_FN7,	MSEL5CR_19_0),
736 
737 	/* Port25 */
738 	PINMUX_DATA(VIO0_D14_PORT25_MARK,	PORT25_FN1,	MSEL5CR_27_0),
739 	PINMUX_DATA(VIO1_D6_MARK,		PORT25_FN5),
740 	PINMUX_DATA(SCIFA6_RXD_MARK,		PORT25_FN6),
741 	PINMUX_DATA(SDHI2_WP_PORT25_MARK,	PORT25_FN7,	MSEL5CR_19_0),
742 
743 	/* Port26 */
744 	PINMUX_DATA(VIO0_D13_PORT26_MARK,	PORT26_FN1,	MSEL5CR_27_0),
745 	PINMUX_DATA(VIO1_D5_MARK,		PORT26_FN5),
746 	PINMUX_DATA(SCIFA6_TXD_MARK,		PORT26_FN6),
747 
748 	/* Port27 - Port39 Function */
749 	PINMUX_DATA(VIO0_D7_MARK,		PORT27_FN1),
750 	PINMUX_DATA(VIO0_D6_MARK,		PORT28_FN1),
751 	PINMUX_DATA(VIO0_D5_MARK,		PORT29_FN1),
752 	PINMUX_DATA(VIO0_D4_MARK,		PORT30_FN1),
753 	PINMUX_DATA(VIO0_D3_MARK,		PORT31_FN1),
754 	PINMUX_DATA(VIO0_D2_MARK,		PORT32_FN1),
755 	PINMUX_DATA(VIO0_D1_MARK,		PORT33_FN1),
756 	PINMUX_DATA(VIO0_D0_MARK,		PORT34_FN1),
757 	PINMUX_DATA(VIO0_CLK_MARK,		PORT35_FN1),
758 	PINMUX_DATA(VIO_CKO_MARK,		PORT36_FN1),
759 	PINMUX_DATA(VIO0_HD_MARK,		PORT37_FN1),
760 	PINMUX_DATA(VIO0_FIELD_MARK,		PORT38_FN1),
761 	PINMUX_DATA(VIO0_VD_MARK,		PORT39_FN1),
762 
763 	/* Port38 IRQ */
764 	PINMUX_DATA(IRQ25_MARK,			PORT38_FN0),
765 
766 	/* Port40 */
767 	PINMUX_DATA(LCD0_D18_PORT40_MARK,	PORT40_FN4,	MSEL5CR_6_0),
768 	PINMUX_DATA(RSPI_CK_A_MARK,		PORT40_FN6),
769 	PINMUX_DATA(LCD1_LCLK_MARK,		PORT40_FN7),
770 
771 	/* Port41 */
772 	PINMUX_DATA(LCD0_D17_MARK,		PORT41_FN1),
773 	PINMUX_DATA(MSIOF2_SS1_MARK,		PORT41_FN2),
774 	PINMUX_DATA(IRQ31_PORT41_MARK,		PORT41_FN0,	MSEL1CR_31_1),
775 
776 	/* Port42 */
777 	PINMUX_DATA(LCD0_D16_MARK,		PORT42_FN1),
778 	PINMUX_DATA(MSIOF2_MCK1_MARK,		PORT42_FN2),
779 	PINMUX_DATA(IRQ12_PORT42_MARK,		PORT42_FN0,	MSEL1CR_12_1),
780 
781 	/* Port43 */
782 	PINMUX_DATA(LCD0_D15_MARK,		PORT43_FN1),
783 	PINMUX_DATA(MSIOF2_MCK0_MARK,		PORT43_FN2),
784 	PINMUX_DATA(KEYIN0_PORT43_MARK,		PORT43_FN3,	MSEL4CR_18_0),
785 	PINMUX_DATA(DV_D15_MARK,		PORT43_FN6),
786 
787 	/* Port44 */
788 	PINMUX_DATA(LCD0_D14_MARK,		PORT44_FN1),
789 	PINMUX_DATA(MSIOF2_RSYNC_MARK,		PORT44_FN2),
790 	PINMUX_DATA(KEYIN1_PORT44_MARK,		PORT44_FN3,	MSEL4CR_18_0),
791 	PINMUX_DATA(DV_D14_MARK,		PORT44_FN6),
792 
793 	/* Port45 */
794 	PINMUX_DATA(LCD0_D13_MARK,		PORT45_FN1),
795 	PINMUX_DATA(MSIOF2_RSCK_MARK,		PORT45_FN2),
796 	PINMUX_DATA(KEYIN2_PORT45_MARK,		PORT45_FN3,	MSEL4CR_18_0),
797 	PINMUX_DATA(DV_D13_MARK,		PORT45_FN6),
798 
799 	/* Port46 */
800 	PINMUX_DATA(LCD0_D12_MARK,		PORT46_FN1),
801 	PINMUX_DATA(KEYIN3_PORT46_MARK,		PORT46_FN3,	MSEL4CR_18_0),
802 	PINMUX_DATA(DV_D12_MARK,		PORT46_FN6),
803 
804 	/* Port47 */
805 	PINMUX_DATA(LCD0_D11_MARK,		PORT47_FN1),
806 	PINMUX_DATA(KEYIN4_MARK,		PORT47_FN3),
807 	PINMUX_DATA(DV_D11_MARK,		PORT47_FN6),
808 
809 	/* Port48 */
810 	PINMUX_DATA(LCD0_D10_MARK,		PORT48_FN1),
811 	PINMUX_DATA(KEYIN5_MARK,		PORT48_FN3),
812 	PINMUX_DATA(DV_D10_MARK,		PORT48_FN6),
813 
814 	/* Port49 */
815 	PINMUX_DATA(LCD0_D9_MARK,		PORT49_FN1),
816 	PINMUX_DATA(KEYIN6_MARK,		PORT49_FN3),
817 	PINMUX_DATA(DV_D9_MARK,			PORT49_FN6),
818 	PINMUX_DATA(IRQ30_PORT49_MARK,		PORT49_FN0,	MSEL1CR_30_1),
819 
820 	/* Port50 */
821 	PINMUX_DATA(LCD0_D8_MARK,		PORT50_FN1),
822 	PINMUX_DATA(KEYIN7_MARK,		PORT50_FN3),
823 	PINMUX_DATA(DV_D8_MARK,			PORT50_FN6),
824 	PINMUX_DATA(IRQ29_PORT50_MARK,		PORT50_FN0,	MSEL1CR_29_1),
825 
826 	/* Port51 */
827 	PINMUX_DATA(LCD0_D7_MARK,		PORT51_FN1),
828 	PINMUX_DATA(KEYOUT0_MARK,		PORT51_FN3),
829 	PINMUX_DATA(DV_D7_MARK,			PORT51_FN6),
830 
831 	/* Port52 */
832 	PINMUX_DATA(LCD0_D6_MARK,		PORT52_FN1),
833 	PINMUX_DATA(KEYOUT1_MARK,		PORT52_FN3),
834 	PINMUX_DATA(DV_D6_MARK,			PORT52_FN6),
835 
836 	/* Port53 */
837 	PINMUX_DATA(LCD0_D5_MARK,		PORT53_FN1),
838 	PINMUX_DATA(KEYOUT2_MARK,		PORT53_FN3),
839 	PINMUX_DATA(DV_D5_MARK,			PORT53_FN6),
840 
841 	/* Port54 */
842 	PINMUX_DATA(LCD0_D4_MARK,		PORT54_FN1),
843 	PINMUX_DATA(KEYOUT3_MARK,		PORT54_FN3),
844 	PINMUX_DATA(DV_D4_MARK,			PORT54_FN6),
845 
846 	/* Port55 */
847 	PINMUX_DATA(LCD0_D3_MARK,		PORT55_FN1),
848 	PINMUX_DATA(KEYOUT4_MARK,		PORT55_FN3),
849 	PINMUX_DATA(KEYIN3_PORT55_MARK,		PORT55_FN4,	MSEL4CR_18_1),
850 	PINMUX_DATA(DV_D3_MARK,			PORT55_FN6),
851 
852 	/* Port56 */
853 	PINMUX_DATA(LCD0_D2_MARK,		PORT56_FN1),
854 	PINMUX_DATA(KEYOUT5_MARK,		PORT56_FN3),
855 	PINMUX_DATA(KEYIN2_PORT56_MARK,		PORT56_FN4,	MSEL4CR_18_1),
856 	PINMUX_DATA(DV_D2_MARK,			PORT56_FN6),
857 	PINMUX_DATA(IRQ28_PORT56_MARK,		PORT56_FN0,	MSEL1CR_28_1),
858 
859 	/* Port57 */
860 	PINMUX_DATA(LCD0_D1_MARK,		PORT57_FN1),
861 	PINMUX_DATA(KEYOUT6_MARK,		PORT57_FN3),
862 	PINMUX_DATA(KEYIN1_PORT57_MARK,		PORT57_FN4,	MSEL4CR_18_1),
863 	PINMUX_DATA(DV_D1_MARK,			PORT57_FN6),
864 	PINMUX_DATA(IRQ27_PORT57_MARK,		PORT57_FN0,	MSEL1CR_27_1),
865 
866 	/* Port58 */
867 	PINMUX_DATA(LCD0_D0_MARK,		PORT58_FN1,	MSEL3CR_6_0),
868 	PINMUX_DATA(KEYOUT7_MARK,		PORT58_FN3),
869 	PINMUX_DATA(KEYIN0_PORT58_MARK,		PORT58_FN4,	MSEL4CR_18_1),
870 	PINMUX_DATA(DV_D0_MARK,			PORT58_FN6),
871 	PINMUX_DATA(IRQ26_PORT58_MARK,		PORT58_FN0,	MSEL1CR_26_1),
872 
873 	/* Port59 */
874 	PINMUX_DATA(LCD0_VCPWC_MARK,		PORT59_FN1),
875 	PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK,	PORT59_FN2,	MSEL5CR_0_0),
876 	PINMUX_DATA(RSPI_MOSI_A_MARK,		PORT59_FN6),
877 
878 	/* Port60 */
879 	PINMUX_DATA(LCD0_VEPWC_MARK,		PORT60_FN1),
880 	PINMUX_DATA(BBIF2_RXD2_PORT60_MARK,	PORT60_FN2,	MSEL5CR_0_0),
881 	PINMUX_DATA(RSPI_MISO_A_MARK,		PORT60_FN6),
882 
883 	/* Port61 */
884 	PINMUX_DATA(LCD0_DON_MARK,		PORT61_FN1),
885 	PINMUX_DATA(MSIOF2_TXD_MARK,		PORT61_FN2),
886 
887 	/* Port62 */
888 	PINMUX_DATA(LCD0_DCK_MARK,		PORT62_FN1),
889 	PINMUX_DATA(LCD0_WR_MARK,		PORT62_FN4),
890 	PINMUX_DATA(DV_CLK_MARK,		PORT62_FN6),
891 	PINMUX_DATA(IRQ15_PORT62_MARK,		PORT62_FN0,	MSEL1CR_15_1),
892 
893 	/* Port63 */
894 	PINMUX_DATA(LCD0_VSYN_MARK,		PORT63_FN1),
895 	PINMUX_DATA(DV_VSYNC_MARK,		PORT63_FN6),
896 	PINMUX_DATA(IRQ14_PORT63_MARK,		PORT63_FN0,	MSEL1CR_14_1),
897 
898 	/* Port64 */
899 	PINMUX_DATA(LCD0_HSYN_MARK,		PORT64_FN1),
900 	PINMUX_DATA(LCD0_CS_MARK,		PORT64_FN4),
901 	PINMUX_DATA(DV_HSYNC_MARK,		PORT64_FN6),
902 	PINMUX_DATA(IRQ13_PORT64_MARK,		PORT64_FN0,	MSEL1CR_13_1),
903 
904 	/* Port65 */
905 	PINMUX_DATA(LCD0_DISP_MARK,		PORT65_FN1),
906 	PINMUX_DATA(MSIOF2_TSCK_MARK,		PORT65_FN2),
907 	PINMUX_DATA(LCD0_RS_MARK,		PORT65_FN4),
908 
909 	/* Port66 */
910 	PINMUX_DATA(MEMC_INT_MARK,		PORT66_FN1),
911 	PINMUX_DATA(TPU0TO2_PORT66_MARK,	PORT66_FN3,	MSEL5CR_25_0),
912 	PINMUX_DATA(MMC0_CLK_PORT66_MARK,	PORT66_FN4,	MSEL4CR_15_0),
913 	PINMUX_DATA(SDHI1_CLK_MARK,		PORT66_FN6),
914 
915 	/* Port67 - Port73 Function1 */
916 	PINMUX_DATA(MEMC_CS0_MARK,		PORT67_FN1),
917 	PINMUX_DATA(MEMC_AD8_MARK,		PORT68_FN1),
918 	PINMUX_DATA(MEMC_AD9_MARK,		PORT69_FN1),
919 	PINMUX_DATA(MEMC_AD10_MARK,		PORT70_FN1),
920 	PINMUX_DATA(MEMC_AD11_MARK,		PORT71_FN1),
921 	PINMUX_DATA(MEMC_AD12_MARK,		PORT72_FN1),
922 	PINMUX_DATA(MEMC_AD13_MARK,		PORT73_FN1),
923 
924 	/* Port67 - Port73 Function2 */
925 	PINMUX_DATA(MSIOF1_SS1_PORT67_MARK,	PORT67_FN2,	MSEL4CR_10_1),
926 	PINMUX_DATA(MSIOF1_RSCK_MARK,		PORT68_FN2),
927 	PINMUX_DATA(MSIOF1_RSYNC_MARK,		PORT69_FN2),
928 	PINMUX_DATA(MSIOF1_MCK0_MARK,		PORT70_FN2),
929 	PINMUX_DATA(MSIOF1_MCK1_MARK,		PORT71_FN2),
930 	PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK,	PORT72_FN2,	MSEL4CR_10_1),
931 	PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK,	PORT73_FN2,	MSEL4CR_10_1),
932 
933 	/* Port67 - Port73 Function4 */
934 	PINMUX_DATA(MMC0_CMD_PORT67_MARK,	PORT67_FN4,	MSEL4CR_15_0),
935 	PINMUX_DATA(MMC0_D0_PORT68_MARK,	PORT68_FN4,	MSEL4CR_15_0),
936 	PINMUX_DATA(MMC0_D1_PORT69_MARK,	PORT69_FN4,	MSEL4CR_15_0),
937 	PINMUX_DATA(MMC0_D2_PORT70_MARK,	PORT70_FN4,	MSEL4CR_15_0),
938 	PINMUX_DATA(MMC0_D3_PORT71_MARK,	PORT71_FN4,	MSEL4CR_15_0),
939 	PINMUX_DATA(MMC0_D4_PORT72_MARK,	PORT72_FN4,	MSEL4CR_15_0),
940 	PINMUX_DATA(MMC0_D5_PORT73_MARK,	PORT73_FN4,	MSEL4CR_15_0),
941 
942 	/* Port67 - Port73 Function6 */
943 	PINMUX_DATA(SDHI1_CMD_MARK,		PORT67_FN6),
944 	PINMUX_DATA(SDHI1_D0_MARK,		PORT68_FN6),
945 	PINMUX_DATA(SDHI1_D1_MARK,		PORT69_FN6),
946 	PINMUX_DATA(SDHI1_D2_MARK,		PORT70_FN6),
947 	PINMUX_DATA(SDHI1_D3_MARK,		PORT71_FN6),
948 	PINMUX_DATA(SDHI1_CD_MARK,		PORT72_FN6),
949 	PINMUX_DATA(SDHI1_WP_MARK,		PORT73_FN6),
950 
951 	/* Port67 - Port71 IRQ */
952 	PINMUX_DATA(IRQ20_MARK,			PORT67_FN0),
953 	PINMUX_DATA(IRQ16_PORT68_MARK,		PORT68_FN0,	MSEL1CR_16_0),
954 	PINMUX_DATA(IRQ17_MARK,			PORT69_FN0),
955 	PINMUX_DATA(IRQ18_MARK,			PORT70_FN0),
956 	PINMUX_DATA(IRQ19_MARK,			PORT71_FN0),
957 
958 	/* Port74 */
959 	PINMUX_DATA(MEMC_AD14_MARK,		PORT74_FN1),
960 	PINMUX_DATA(MSIOF1_TXD_PORT74_MARK,	PORT74_FN2,	MSEL4CR_10_1),
961 	PINMUX_DATA(MMC0_D6_PORT74_MARK,	PORT74_FN4,	MSEL4CR_15_0),
962 	PINMUX_DATA(STP1_IPD7_MARK,		PORT74_FN6),
963 	PINMUX_DATA(LCD1_D21_MARK,		PORT74_FN7),
964 
965 	/* Port75 */
966 	PINMUX_DATA(MEMC_AD15_MARK,		PORT75_FN1),
967 	PINMUX_DATA(MSIOF1_RXD_PORT75_MARK,	PORT75_FN2,	MSEL4CR_10_1),
968 	PINMUX_DATA(MMC0_D7_PORT75_MARK,	PORT75_FN4,	MSEL4CR_15_0),
969 	PINMUX_DATA(STP1_IPD6_MARK,		PORT75_FN6),
970 	PINMUX_DATA(LCD1_D20_MARK,		PORT75_FN7),
971 
972 	/* Port76 - Port80 Function */
973 	PINMUX_DATA(SDHI0_CMD_MARK,		PORT76_FN1),
974 	PINMUX_DATA(SDHI0_D0_MARK,		PORT77_FN1),
975 	PINMUX_DATA(SDHI0_D1_MARK,		PORT78_FN1),
976 	PINMUX_DATA(SDHI0_D2_MARK,		PORT79_FN1),
977 	PINMUX_DATA(SDHI0_D3_MARK,		PORT80_FN1),
978 
979 	/* Port81 */
980 	PINMUX_DATA(SDHI0_CD_MARK,		PORT81_FN1),
981 	PINMUX_DATA(IRQ26_PORT81_MARK,		PORT81_FN0,	MSEL1CR_26_0),
982 
983 	/* Port82 - Port88 Function */
984 	PINMUX_DATA(SDHI0_CLK_MARK,		PORT82_FN1),
985 	PINMUX_DATA(SDHI0_WP_MARK,		PORT83_FN1),
986 	PINMUX_DATA(RESETOUTS_MARK,		PORT84_FN1),
987 	PINMUX_DATA(USB0_PPON_MARK,		PORT85_FN1),
988 	PINMUX_DATA(USB0_OCI_MARK,		PORT86_FN1),
989 	PINMUX_DATA(USB1_PPON_MARK,		PORT87_FN1),
990 	PINMUX_DATA(USB1_OCI_MARK,		PORT88_FN1),
991 
992 	/* Port89 */
993 	PINMUX_DATA(DREQ0_MARK,			PORT89_FN1),
994 	PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK,	PORT89_FN2,	MSEL5CR_0_1),
995 	PINMUX_DATA(RSPI_SSL3_A_MARK,		PORT89_FN6),
996 
997 	/* Port90 */
998 	PINMUX_DATA(DACK0_MARK,			PORT90_FN1),
999 	PINMUX_DATA(BBIF2_RXD2_PORT90_MARK,	PORT90_FN2,	MSEL5CR_0_1),
1000 	PINMUX_DATA(RSPI_SSL2_A_MARK,		PORT90_FN6),
1001 	PINMUX_DATA(WAIT_PORT90_MARK,		PORT90_FN7,	MSEL5CR_2_1),
1002 
1003 	/* Port91 */
1004 	PINMUX_DATA(MEMC_AD0_MARK,		PORT91_FN1),
1005 	PINMUX_DATA(BBIF1_RXD_MARK,		PORT91_FN2),
1006 	PINMUX_DATA(SCIFA5_TXD_PORT91_MARK,	PORT91_FN3,	MSEL5CR_15_1,	MSEL5CR_14_0),
1007 	PINMUX_DATA(LCD1_D5_MARK,		PORT91_FN7),
1008 
1009 	/* Port92 */
1010 	PINMUX_DATA(MEMC_AD1_MARK,		PORT92_FN1),
1011 	PINMUX_DATA(BBIF1_TSYNC_MARK,		PORT92_FN2),
1012 	PINMUX_DATA(SCIFA5_RXD_PORT92_MARK,	PORT92_FN3,	MSEL5CR_15_1,	MSEL5CR_14_0),
1013 	PINMUX_DATA(STP0_IPD1_MARK,		PORT92_FN6),
1014 	PINMUX_DATA(LCD1_D6_MARK,		PORT92_FN7),
1015 
1016 	/* Port93 */
1017 	PINMUX_DATA(MEMC_AD2_MARK,		PORT93_FN1),
1018 	PINMUX_DATA(BBIF1_TSCK_MARK,		PORT93_FN2),
1019 	PINMUX_DATA(SCIFA4_TXD_PORT93_MARK,	PORT93_FN3,	MSEL5CR_12_1,	MSEL5CR_11_0),
1020 	PINMUX_DATA(STP0_IPD3_MARK,		PORT93_FN6),
1021 	PINMUX_DATA(LCD1_D8_MARK,		PORT93_FN7),
1022 
1023 	/* Port94 */
1024 	PINMUX_DATA(MEMC_AD3_MARK,		PORT94_FN1),
1025 	PINMUX_DATA(BBIF1_TXD_MARK,		PORT94_FN2),
1026 	PINMUX_DATA(SCIFA4_RXD_PORT94_MARK,	PORT94_FN3,	MSEL5CR_12_1,	MSEL5CR_11_0),
1027 	PINMUX_DATA(STP0_IPD4_MARK,		PORT94_FN6),
1028 	PINMUX_DATA(LCD1_D9_MARK,		PORT94_FN7),
1029 
1030 	/* Port95 */
1031 	PINMUX_DATA(MEMC_CS1_MARK,		PORT95_FN1,	MSEL4CR_6_0),
1032 	PINMUX_DATA(MEMC_A1_MARK,		PORT95_FN1,	MSEL4CR_6_1),
1033 
1034 	PINMUX_DATA(SCIFA2_CTS_MARK,		PORT95_FN2),
1035 	PINMUX_DATA(SIM_RST_MARK,		PORT95_FN4),
1036 	PINMUX_DATA(VIO0_D14_PORT95_MARK,	PORT95_FN7,	MSEL5CR_27_1),
1037 	PINMUX_DATA(IRQ22_MARK,			PORT95_FN0),
1038 
1039 	/* Port96 */
1040 	PINMUX_DATA(MEMC_ADV_MARK,		PORT96_FN1,	MSEL4CR_6_0),
1041 	PINMUX_DATA(MEMC_DREQ0_MARK,		PORT96_FN1,	MSEL4CR_6_1),
1042 
1043 	PINMUX_DATA(SCIFA2_RTS_MARK,		PORT96_FN2),
1044 	PINMUX_DATA(SIM_CLK_MARK,		PORT96_FN4),
1045 	PINMUX_DATA(VIO0_D15_PORT96_MARK,	PORT96_FN7,	MSEL5CR_27_1),
1046 	PINMUX_DATA(IRQ23_MARK,			PORT96_FN0),
1047 
1048 	/* Port97 */
1049 	PINMUX_DATA(MEMC_AD4_MARK,		PORT97_FN1),
1050 	PINMUX_DATA(BBIF1_RSCK_MARK,		PORT97_FN2),
1051 	PINMUX_DATA(LCD1_CS_MARK,		PORT97_FN6),
1052 	PINMUX_DATA(LCD1_HSYN_MARK,		PORT97_FN7),
1053 	PINMUX_DATA(IRQ12_PORT97_MARK,		PORT97_FN0,	MSEL1CR_12_0),
1054 
1055 	/* Port98 */
1056 	PINMUX_DATA(MEMC_AD5_MARK,		PORT98_FN1),
1057 	PINMUX_DATA(BBIF1_RSYNC_MARK,		PORT98_FN2),
1058 	PINMUX_DATA(LCD1_VSYN_MARK,		PORT98_FN7),
1059 	PINMUX_DATA(IRQ13_PORT98_MARK,		PORT98_FN0,	MSEL1CR_13_0),
1060 
1061 	/* Port99 */
1062 	PINMUX_DATA(MEMC_AD6_MARK,		PORT99_FN1),
1063 	PINMUX_DATA(BBIF1_FLOW_MARK,		PORT99_FN2),
1064 	PINMUX_DATA(LCD1_WR_MARK,		PORT99_FN6),
1065 	PINMUX_DATA(LCD1_DCK_MARK,		PORT99_FN7),
1066 	PINMUX_DATA(IRQ14_PORT99_MARK,		PORT99_FN0,	MSEL1CR_14_0),
1067 
1068 	/* Port100 */
1069 	PINMUX_DATA(MEMC_AD7_MARK,		PORT100_FN1),
1070 	PINMUX_DATA(BBIF1_RX_FLOW_N_MARK,	PORT100_FN2),
1071 	PINMUX_DATA(LCD1_DON_MARK,		PORT100_FN7),
1072 	PINMUX_DATA(IRQ15_PORT100_MARK,		PORT100_FN0,	MSEL1CR_15_0),
1073 
1074 	/* Port101 */
1075 	PINMUX_DATA(FCE0_MARK,			PORT101_FN1),
1076 
1077 	/* Port102 */
1078 	PINMUX_DATA(FRB_MARK,			PORT102_FN1),
1079 	PINMUX_DATA(LCD0_LCLK_PORT102_MARK,	PORT102_FN4,	MSEL5CR_6_0),
1080 
1081 	/* Port103 */
1082 	PINMUX_DATA(CS5B_MARK,			PORT103_FN1),
1083 	PINMUX_DATA(FCE1_MARK,			PORT103_FN2),
1084 	PINMUX_DATA(MMC1_CLK_PORT103_MARK,	PORT103_FN3,	MSEL4CR_15_1),
1085 
1086 	/* Port104 */
1087 	PINMUX_DATA(CS6A_MARK,			PORT104_FN1),
1088 	PINMUX_DATA(MMC1_CMD_PORT104_MARK,	PORT104_FN3,	MSEL4CR_15_1),
1089 	PINMUX_DATA(IRQ11_MARK,			PORT104_FN0),
1090 
1091 	/* Port105 */
1092 	PINMUX_DATA(CS5A_PORT105_MARK,		PORT105_FN1,	MSEL5CR_2_0),
1093 	PINMUX_DATA(SCIFA3_RTS_PORT105_MARK,	PORT105_FN4,	MSEL5CR_8_0),
1094 
1095 	/* Port106 */
1096 	PINMUX_DATA(IOIS16_MARK,		PORT106_FN1),
1097 	PINMUX_DATA(IDE_EXBUF_ENB_MARK,		PORT106_FN6),
1098 
1099 	/* Port107 - Port115 Function */
1100 	PINMUX_DATA(WE3_ICIOWR_MARK,		PORT107_FN1),
1101 	PINMUX_DATA(WE2_ICIORD_MARK,		PORT108_FN1),
1102 	PINMUX_DATA(CS0_MARK,			PORT109_FN1),
1103 	PINMUX_DATA(CS2_MARK,			PORT110_FN1),
1104 	PINMUX_DATA(CS4_MARK,			PORT111_FN1),
1105 	PINMUX_DATA(WE1_MARK,			PORT112_FN1),
1106 	PINMUX_DATA(WE0_FWE_MARK,		PORT113_FN1),
1107 	PINMUX_DATA(RDWR_MARK,			PORT114_FN1),
1108 	PINMUX_DATA(RD_FSC_MARK,		PORT115_FN1),
1109 
1110 	/* Port116 */
1111 	PINMUX_DATA(A25_MARK,			PORT116_FN1),
1112 	PINMUX_DATA(MSIOF0_SS2_MARK,		PORT116_FN2),
1113 	PINMUX_DATA(MSIOF1_SS2_PORT116_MARK,	PORT116_FN3,	MSEL4CR_10_0),
1114 	PINMUX_DATA(SCIFA3_SCK_PORT116_MARK,	PORT116_FN4,	MSEL5CR_8_0),
1115 	PINMUX_DATA(GPO1_MARK,			PORT116_FN5),
1116 
1117 	/* Port117 */
1118 	PINMUX_DATA(A24_MARK,			PORT117_FN1),
1119 	PINMUX_DATA(MSIOF0_SS1_MARK,		PORT117_FN2),
1120 	PINMUX_DATA(MSIOF1_SS1_PORT117_MARK,	PORT117_FN3,	MSEL4CR_10_0),
1121 	PINMUX_DATA(SCIFA3_CTS_PORT117_MARK,	PORT117_FN4,	MSEL5CR_8_0),
1122 	PINMUX_DATA(GPO0_MARK,			PORT117_FN5),
1123 
1124 	/* Port118 */
1125 	PINMUX_DATA(A23_MARK,			PORT118_FN1),
1126 	PINMUX_DATA(MSIOF0_MCK1_MARK,		PORT118_FN2),
1127 	PINMUX_DATA(MSIOF1_RXD_PORT118_MARK,	PORT118_FN3,	MSEL4CR_10_0),
1128 	PINMUX_DATA(GPI1_MARK,			PORT118_FN5),
1129 	PINMUX_DATA(IRQ9_PORT118_MARK,		PORT118_FN0,	MSEL1CR_9_0),
1130 
1131 	/* Port119 */
1132 	PINMUX_DATA(A22_MARK,			PORT119_FN1),
1133 	PINMUX_DATA(MSIOF0_MCK0_MARK,		PORT119_FN2),
1134 	PINMUX_DATA(MSIOF1_TXD_PORT119_MARK,	PORT119_FN3,	MSEL4CR_10_0),
1135 	PINMUX_DATA(GPI0_MARK,			PORT119_FN5),
1136 	PINMUX_DATA(IRQ8_MARK,			PORT119_FN0),
1137 
1138 	/* Port120 */
1139 	PINMUX_DATA(A21_MARK,			PORT120_FN1),
1140 	PINMUX_DATA(MSIOF0_RSYNC_MARK,		PORT120_FN2),
1141 	PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK,	PORT120_FN3,	MSEL4CR_10_0),
1142 	PINMUX_DATA(IRQ7_PORT120_MARK,		PORT120_FN0,	MSEL1CR_7_1),
1143 
1144 	/* Port121 */
1145 	PINMUX_DATA(A20_MARK,			PORT121_FN1),
1146 	PINMUX_DATA(MSIOF0_RSCK_MARK,		PORT121_FN2),
1147 	PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK,	PORT121_FN3,	MSEL4CR_10_0),
1148 	PINMUX_DATA(IRQ6_PORT121_MARK,		PORT121_FN0,	MSEL1CR_6_0),
1149 
1150 	/* Port122 */
1151 	PINMUX_DATA(A19_MARK,			PORT122_FN1),
1152 	PINMUX_DATA(MSIOF0_RXD_MARK,		PORT122_FN2),
1153 
1154 	/* Port123 */
1155 	PINMUX_DATA(A18_MARK,			PORT123_FN1),
1156 	PINMUX_DATA(MSIOF0_TSCK_MARK,		PORT123_FN2),
1157 
1158 	/* Port124 */
1159 	PINMUX_DATA(A17_MARK,			PORT124_FN1),
1160 	PINMUX_DATA(MSIOF0_TSYNC_MARK,		PORT124_FN2),
1161 
1162 	/* Port125 - Port141 Function */
1163 	PINMUX_DATA(A16_MARK,			PORT125_FN1),
1164 	PINMUX_DATA(A15_MARK,			PORT126_FN1),
1165 	PINMUX_DATA(A14_MARK,			PORT127_FN1),
1166 	PINMUX_DATA(A13_MARK,			PORT128_FN1),
1167 	PINMUX_DATA(A12_MARK,			PORT129_FN1),
1168 	PINMUX_DATA(A11_MARK,			PORT130_FN1),
1169 	PINMUX_DATA(A10_MARK,			PORT131_FN1),
1170 	PINMUX_DATA(A9_MARK,			PORT132_FN1),
1171 	PINMUX_DATA(A8_MARK,			PORT133_FN1),
1172 	PINMUX_DATA(A7_MARK,			PORT134_FN1),
1173 	PINMUX_DATA(A6_MARK,			PORT135_FN1),
1174 	PINMUX_DATA(A5_FCDE_MARK,		PORT136_FN1),
1175 	PINMUX_DATA(A4_FOE_MARK,		PORT137_FN1),
1176 	PINMUX_DATA(A3_MARK,			PORT138_FN1),
1177 	PINMUX_DATA(A2_MARK,			PORT139_FN1),
1178 	PINMUX_DATA(A1_MARK,			PORT140_FN1),
1179 	PINMUX_DATA(CKO_MARK,			PORT141_FN1),
1180 
1181 	/* Port142 - Port157 Function1 */
1182 	PINMUX_DATA(D15_NAF15_MARK,		PORT142_FN1),
1183 	PINMUX_DATA(D14_NAF14_MARK,		PORT143_FN1),
1184 	PINMUX_DATA(D13_NAF13_MARK,		PORT144_FN1),
1185 	PINMUX_DATA(D12_NAF12_MARK,		PORT145_FN1),
1186 	PINMUX_DATA(D11_NAF11_MARK,		PORT146_FN1),
1187 	PINMUX_DATA(D10_NAF10_MARK,		PORT147_FN1),
1188 	PINMUX_DATA(D9_NAF9_MARK,		PORT148_FN1),
1189 	PINMUX_DATA(D8_NAF8_MARK,		PORT149_FN1),
1190 	PINMUX_DATA(D7_NAF7_MARK,		PORT150_FN1),
1191 	PINMUX_DATA(D6_NAF6_MARK,		PORT151_FN1),
1192 	PINMUX_DATA(D5_NAF5_MARK,		PORT152_FN1),
1193 	PINMUX_DATA(D4_NAF4_MARK,		PORT153_FN1),
1194 	PINMUX_DATA(D3_NAF3_MARK,		PORT154_FN1),
1195 	PINMUX_DATA(D2_NAF2_MARK,		PORT155_FN1),
1196 	PINMUX_DATA(D1_NAF1_MARK,		PORT156_FN1),
1197 	PINMUX_DATA(D0_NAF0_MARK,		PORT157_FN1),
1198 
1199 	/* Port142 - Port149 Function3 */
1200 	PINMUX_DATA(MMC1_D7_PORT142_MARK,	PORT142_FN3,	MSEL4CR_15_1),
1201 	PINMUX_DATA(MMC1_D6_PORT143_MARK,	PORT143_FN3,	MSEL4CR_15_1),
1202 	PINMUX_DATA(MMC1_D5_PORT144_MARK,	PORT144_FN3,	MSEL4CR_15_1),
1203 	PINMUX_DATA(MMC1_D4_PORT145_MARK,	PORT145_FN3,	MSEL4CR_15_1),
1204 	PINMUX_DATA(MMC1_D3_PORT146_MARK,	PORT146_FN3,	MSEL4CR_15_1),
1205 	PINMUX_DATA(MMC1_D2_PORT147_MARK,	PORT147_FN3,	MSEL4CR_15_1),
1206 	PINMUX_DATA(MMC1_D1_PORT148_MARK,	PORT148_FN3,	MSEL4CR_15_1),
1207 	PINMUX_DATA(MMC1_D0_PORT149_MARK,	PORT149_FN3,	MSEL4CR_15_1),
1208 
1209 	/* Port158 */
1210 	PINMUX_DATA(D31_MARK,			PORT158_FN1),
1211 	PINMUX_DATA(SCIFA3_SCK_PORT158_MARK,	PORT158_FN2,	MSEL5CR_8_1),
1212 	PINMUX_DATA(RMII_REF125CK_MARK,		PORT158_FN3),
1213 	PINMUX_DATA(LCD0_D21_PORT158_MARK,	PORT158_FN4,	MSEL5CR_6_1),
1214 	PINMUX_DATA(IRDA_FIRSEL_MARK,		PORT158_FN5),
1215 	PINMUX_DATA(IDE_D15_MARK,		PORT158_FN6),
1216 
1217 	/* Port159 */
1218 	PINMUX_DATA(D30_MARK,			PORT159_FN1),
1219 	PINMUX_DATA(SCIFA3_RXD_PORT159_MARK,	PORT159_FN2,	MSEL5CR_8_1),
1220 	PINMUX_DATA(RMII_REF50CK_MARK,		PORT159_FN3),
1221 	PINMUX_DATA(LCD0_D23_PORT159_MARK,	PORT159_FN4,	MSEL5CR_6_1),
1222 	PINMUX_DATA(IDE_D14_MARK,		PORT159_FN6),
1223 
1224 	/* Port160 */
1225 	PINMUX_DATA(D29_MARK,			PORT160_FN1),
1226 	PINMUX_DATA(SCIFA3_TXD_PORT160_MARK,	PORT160_FN2,	MSEL5CR_8_1),
1227 	PINMUX_DATA(LCD0_D22_PORT160_MARK,	PORT160_FN4,	MSEL5CR_6_1),
1228 	PINMUX_DATA(VIO1_HD_MARK,		PORT160_FN5),
1229 	PINMUX_DATA(IDE_D13_MARK,		PORT160_FN6),
1230 
1231 	/* Port161 */
1232 	PINMUX_DATA(D28_MARK,			PORT161_FN1),
1233 	PINMUX_DATA(SCIFA3_RTS_PORT161_MARK,	PORT161_FN2,	MSEL5CR_8_1),
1234 	PINMUX_DATA(ET_RX_DV_MARK,		PORT161_FN3),
1235 	PINMUX_DATA(LCD0_D20_PORT161_MARK,	PORT161_FN4,	MSEL5CR_6_1),
1236 	PINMUX_DATA(IRDA_IN_MARK,		PORT161_FN5),
1237 	PINMUX_DATA(IDE_D12_MARK,		PORT161_FN6),
1238 
1239 	/* Port162 */
1240 	PINMUX_DATA(D27_MARK,			PORT162_FN1),
1241 	PINMUX_DATA(SCIFA3_CTS_PORT162_MARK,	PORT162_FN2,	MSEL5CR_8_1),
1242 	PINMUX_DATA(LCD0_D19_PORT162_MARK,	PORT162_FN4,	MSEL5CR_6_1),
1243 	PINMUX_DATA(IRDA_OUT_MARK,		PORT162_FN5),
1244 	PINMUX_DATA(IDE_D11_MARK,		PORT162_FN6),
1245 
1246 	/* Port163 */
1247 	PINMUX_DATA(D26_MARK,			PORT163_FN1),
1248 	PINMUX_DATA(MSIOF2_SS2_MARK,		PORT163_FN2),
1249 	PINMUX_DATA(ET_COL_MARK,		PORT163_FN3),
1250 	PINMUX_DATA(LCD0_D18_PORT163_MARK,	PORT163_FN4,	MSEL5CR_6_1),
1251 	PINMUX_DATA(IROUT_MARK,			PORT163_FN5),
1252 	PINMUX_DATA(IDE_D10_MARK,		PORT163_FN6),
1253 
1254 	/* Port164 */
1255 	PINMUX_DATA(D25_MARK,			PORT164_FN1),
1256 	PINMUX_DATA(MSIOF2_TSYNC_MARK,		PORT164_FN2),
1257 	PINMUX_DATA(ET_PHY_INT_MARK,		PORT164_FN3),
1258 	PINMUX_DATA(LCD0_RD_MARK,		PORT164_FN4),
1259 	PINMUX_DATA(IDE_D9_MARK,		PORT164_FN6),
1260 
1261 	/* Port165 */
1262 	PINMUX_DATA(D24_MARK,			PORT165_FN1),
1263 	PINMUX_DATA(MSIOF2_RXD_MARK,		PORT165_FN2),
1264 	PINMUX_DATA(LCD0_LCLK_PORT165_MARK,	PORT165_FN4,	MSEL5CR_6_1),
1265 	PINMUX_DATA(IDE_D8_MARK,		PORT165_FN6),
1266 
1267 	/* Port166 - Port171 Function1 */
1268 	PINMUX_DATA(D21_MARK,			PORT166_FN1),
1269 	PINMUX_DATA(D20_MARK,			PORT167_FN1),
1270 	PINMUX_DATA(D19_MARK,			PORT168_FN1),
1271 	PINMUX_DATA(D18_MARK,			PORT169_FN1),
1272 	PINMUX_DATA(D17_MARK,			PORT170_FN1),
1273 	PINMUX_DATA(D16_MARK,			PORT171_FN1),
1274 
1275 	/* Port166 - Port171 Function3 */
1276 	PINMUX_DATA(ET_ETXD5_MARK,		PORT166_FN3),
1277 	PINMUX_DATA(ET_ETXD4_MARK,		PORT167_FN3),
1278 	PINMUX_DATA(ET_ETXD3_MARK,		PORT168_FN3),
1279 	PINMUX_DATA(ET_ETXD2_MARK,		PORT169_FN3),
1280 	PINMUX_DATA(ET_ETXD1_MARK,		PORT170_FN3),
1281 	PINMUX_DATA(ET_ETXD0_MARK,		PORT171_FN3),
1282 
1283 	/* Port166 - Port171 Function6 */
1284 	PINMUX_DATA(IDE_D5_MARK,		PORT166_FN6),
1285 	PINMUX_DATA(IDE_D4_MARK,		PORT167_FN6),
1286 	PINMUX_DATA(IDE_D3_MARK,		PORT168_FN6),
1287 	PINMUX_DATA(IDE_D2_MARK,		PORT169_FN6),
1288 	PINMUX_DATA(IDE_D1_MARK,		PORT170_FN6),
1289 	PINMUX_DATA(IDE_D0_MARK,		PORT171_FN6),
1290 
1291 	/* Port167 - Port171 IRQ */
1292 	PINMUX_DATA(IRQ31_PORT167_MARK,		PORT167_FN0,	MSEL1CR_31_0),
1293 	PINMUX_DATA(IRQ27_PORT168_MARK,		PORT168_FN0,	MSEL1CR_27_0),
1294 	PINMUX_DATA(IRQ28_PORT169_MARK,		PORT169_FN0,	MSEL1CR_28_0),
1295 	PINMUX_DATA(IRQ29_PORT170_MARK,		PORT170_FN0,	MSEL1CR_29_0),
1296 	PINMUX_DATA(IRQ30_PORT171_MARK,		PORT171_FN0,	MSEL1CR_30_0),
1297 
1298 	/* Port172 */
1299 	PINMUX_DATA(D23_MARK,			PORT172_FN1),
1300 	PINMUX_DATA(SCIFB_RTS_PORT172_MARK,	PORT172_FN2,	MSEL5CR_17_1),
1301 	PINMUX_DATA(ET_ETXD7_MARK,		PORT172_FN3),
1302 	PINMUX_DATA(IDE_D7_MARK,		PORT172_FN6),
1303 	PINMUX_DATA(IRQ4_PORT172_MARK,		PORT172_FN0,	MSEL1CR_4_1),
1304 
1305 	/* Port173 */
1306 	PINMUX_DATA(D22_MARK,			PORT173_FN1),
1307 	PINMUX_DATA(SCIFB_CTS_PORT173_MARK,	PORT173_FN2,	MSEL5CR_17_1),
1308 	PINMUX_DATA(ET_ETXD6_MARK,		PORT173_FN3),
1309 	PINMUX_DATA(IDE_D6_MARK,		PORT173_FN6),
1310 	PINMUX_DATA(IRQ6_PORT173_MARK,		PORT173_FN0,	MSEL1CR_6_1),
1311 
1312 	/* Port174 */
1313 	PINMUX_DATA(A26_MARK,			PORT174_FN1),
1314 	PINMUX_DATA(MSIOF0_TXD_MARK,		PORT174_FN2),
1315 	PINMUX_DATA(ET_RX_CLK_MARK,		PORT174_FN3),
1316 	PINMUX_DATA(SCIFA3_RXD_PORT174_MARK,	PORT174_FN4,	MSEL5CR_8_0),
1317 
1318 	/* Port175 */
1319 	PINMUX_DATA(A0_MARK,			PORT175_FN1),
1320 	PINMUX_DATA(BS_MARK,			PORT175_FN2),
1321 	PINMUX_DATA(ET_WOL_MARK,		PORT175_FN3),
1322 	PINMUX_DATA(SCIFA3_TXD_PORT175_MARK,	PORT175_FN4,	MSEL5CR_8_0),
1323 
1324 	/* Port176 */
1325 	PINMUX_DATA(ET_GTX_CLK_MARK,		PORT176_FN3),
1326 
1327 	/* Port177 */
1328 	PINMUX_DATA(WAIT_PORT177_MARK,		PORT177_FN1,	MSEL5CR_2_0),
1329 	PINMUX_DATA(ET_LINK_MARK,		PORT177_FN3),
1330 	PINMUX_DATA(IDE_IOWR_MARK,		PORT177_FN6),
1331 	PINMUX_DATA(SDHI2_WP_PORT177_MARK,	PORT177_FN7,	MSEL5CR_19_1),
1332 
1333 	/* Port178 */
1334 	PINMUX_DATA(VIO0_D12_MARK,		PORT178_FN1),
1335 	PINMUX_DATA(VIO1_D4_MARK,		PORT178_FN5),
1336 	PINMUX_DATA(IDE_IORD_MARK,		PORT178_FN6),
1337 
1338 	/* Port179 */
1339 	PINMUX_DATA(VIO0_D11_MARK,		PORT179_FN1),
1340 	PINMUX_DATA(VIO1_D3_MARK,		PORT179_FN5),
1341 	PINMUX_DATA(IDE_IORDY_MARK,		PORT179_FN6),
1342 
1343 	/* Port180 */
1344 	PINMUX_DATA(VIO0_D10_MARK,		PORT180_FN1),
1345 	PINMUX_DATA(TPU0TO3_MARK,		PORT180_FN4),
1346 	PINMUX_DATA(VIO1_D2_MARK,		PORT180_FN5),
1347 	PINMUX_DATA(IDE_INT_MARK,		PORT180_FN6),
1348 	PINMUX_DATA(IRQ24_MARK,			PORT180_FN0),
1349 
1350 	/* Port181 */
1351 	PINMUX_DATA(VIO0_D9_MARK,		PORT181_FN1),
1352 	PINMUX_DATA(VIO1_D1_MARK,		PORT181_FN5),
1353 	PINMUX_DATA(IDE_RST_MARK,		PORT181_FN6),
1354 
1355 	/* Port182 */
1356 	PINMUX_DATA(VIO0_D8_MARK,		PORT182_FN1),
1357 	PINMUX_DATA(VIO1_D0_MARK,		PORT182_FN5),
1358 	PINMUX_DATA(IDE_DIRECTION_MARK,		PORT182_FN6),
1359 
1360 	/* Port183 */
1361 	PINMUX_DATA(DREQ1_MARK,			PORT183_FN1),
1362 	PINMUX_DATA(BBIF2_TXD2_PORT183_MARK,	PORT183_FN2,	MSEL5CR_0_1),
1363 	PINMUX_DATA(ET_TX_EN_MARK,		PORT183_FN3),
1364 
1365 	/* Port184 */
1366 	PINMUX_DATA(DACK1_MARK,			PORT184_FN1),
1367 	PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK,	PORT184_FN2,	MSEL5CR_0_1),
1368 	PINMUX_DATA(ET_TX_CLK_MARK,		PORT184_FN3),
1369 
1370 	/* Port185 - Port192 Function1 */
1371 	PINMUX_DATA(SCIFA1_SCK_MARK,		PORT185_FN1),
1372 	PINMUX_DATA(SCIFB_RTS_PORT186_MARK,	PORT186_FN1,	MSEL5CR_17_0),
1373 	PINMUX_DATA(SCIFB_CTS_PORT187_MARK,	PORT187_FN1,	MSEL5CR_17_0),
1374 	PINMUX_DATA(SCIFA0_SCK_MARK,		PORT188_FN1),
1375 	PINMUX_DATA(SCIFB_SCK_PORT190_MARK,	PORT190_FN1,	MSEL5CR_17_0),
1376 	PINMUX_DATA(SCIFB_RXD_PORT191_MARK,	PORT191_FN1,	MSEL5CR_17_0),
1377 	PINMUX_DATA(SCIFB_TXD_PORT192_MARK,	PORT192_FN1,	MSEL5CR_17_0),
1378 
1379 	/* Port185 - Port192 Function3 */
1380 	PINMUX_DATA(ET_ERXD0_MARK,		PORT185_FN3),
1381 	PINMUX_DATA(ET_ERXD1_MARK,		PORT186_FN3),
1382 	PINMUX_DATA(ET_ERXD2_MARK,		PORT187_FN3),
1383 	PINMUX_DATA(ET_ERXD3_MARK,		PORT188_FN3),
1384 	PINMUX_DATA(ET_ERXD4_MARK,		PORT189_FN3),
1385 	PINMUX_DATA(ET_ERXD5_MARK,		PORT190_FN3),
1386 	PINMUX_DATA(ET_ERXD6_MARK,		PORT191_FN3),
1387 	PINMUX_DATA(ET_ERXD7_MARK,		PORT192_FN3),
1388 
1389 	/* Port185 - Port192 Function6 */
1390 	PINMUX_DATA(STP1_IPCLK_MARK,		PORT185_FN6),
1391 	PINMUX_DATA(STP1_IPD0_PORT186_MARK,	PORT186_FN6,	MSEL5CR_23_0),
1392 	PINMUX_DATA(STP1_IPEN_PORT187_MARK,	PORT187_FN6,	MSEL5CR_23_0),
1393 	PINMUX_DATA(STP1_IPSYNC_MARK,		PORT188_FN6),
1394 	PINMUX_DATA(STP0_IPCLK_MARK,		PORT189_FN6),
1395 	PINMUX_DATA(STP0_IPD0_MARK,		PORT190_FN6),
1396 	PINMUX_DATA(STP0_IPEN_MARK,		PORT191_FN6),
1397 	PINMUX_DATA(STP0_IPSYNC_MARK,		PORT192_FN6),
1398 
1399 	/* Port193 */
1400 	PINMUX_DATA(SCIFA0_CTS_MARK,		PORT193_FN1),
1401 	PINMUX_DATA(RMII_CRS_DV_MARK,		PORT193_FN3),
1402 	PINMUX_DATA(STP1_IPEN_PORT193_MARK,	PORT193_FN6,	MSEL5CR_23_1), /* ? */
1403 	PINMUX_DATA(LCD1_D17_MARK,		PORT193_FN7),
1404 
1405 	/* Port194 */
1406 	PINMUX_DATA(SCIFA0_RTS_MARK,		PORT194_FN1),
1407 	PINMUX_DATA(RMII_RX_ER_MARK,		PORT194_FN3),
1408 	PINMUX_DATA(STP1_IPD0_PORT194_MARK,	PORT194_FN6,	MSEL5CR_23_1), /* ? */
1409 	PINMUX_DATA(LCD1_D16_MARK,		PORT194_FN7),
1410 
1411 	/* Port195 */
1412 	PINMUX_DATA(SCIFA1_RXD_MARK,		PORT195_FN1),
1413 	PINMUX_DATA(RMII_RXD0_MARK,		PORT195_FN3),
1414 	PINMUX_DATA(STP1_IPD3_MARK,		PORT195_FN6),
1415 	PINMUX_DATA(LCD1_D15_MARK,		PORT195_FN7),
1416 
1417 	/* Port196 */
1418 	PINMUX_DATA(SCIFA1_TXD_MARK,		PORT196_FN1),
1419 	PINMUX_DATA(RMII_RXD1_MARK,		PORT196_FN3),
1420 	PINMUX_DATA(STP1_IPD2_MARK,		PORT196_FN6),
1421 	PINMUX_DATA(LCD1_D14_MARK,		PORT196_FN7),
1422 
1423 	/* Port197 */
1424 	PINMUX_DATA(SCIFA0_RXD_MARK,		PORT197_FN1),
1425 	PINMUX_DATA(VIO1_CLK_MARK,		PORT197_FN5),
1426 	PINMUX_DATA(STP1_IPD5_MARK,		PORT197_FN6),
1427 	PINMUX_DATA(LCD1_D19_MARK,		PORT197_FN7),
1428 
1429 	/* Port198 */
1430 	PINMUX_DATA(SCIFA0_TXD_MARK,		PORT198_FN1),
1431 	PINMUX_DATA(VIO1_VD_MARK,		PORT198_FN5),
1432 	PINMUX_DATA(STP1_IPD4_MARK,		PORT198_FN6),
1433 	PINMUX_DATA(LCD1_D18_MARK,		PORT198_FN7),
1434 
1435 	/* Port199 */
1436 	PINMUX_DATA(MEMC_NWE_MARK,		PORT199_FN1),
1437 	PINMUX_DATA(SCIFA2_SCK_PORT199_MARK,	PORT199_FN2,	MSEL5CR_7_1),
1438 	PINMUX_DATA(RMII_TX_EN_MARK,		PORT199_FN3),
1439 	PINMUX_DATA(SIM_D_PORT199_MARK,		PORT199_FN4,	MSEL5CR_21_1),
1440 	PINMUX_DATA(STP1_IPD1_MARK,		PORT199_FN6),
1441 	PINMUX_DATA(LCD1_D13_MARK,		PORT199_FN7),
1442 
1443 	/* Port200 */
1444 	PINMUX_DATA(MEMC_NOE_MARK,		PORT200_FN1),
1445 	PINMUX_DATA(SCIFA2_RXD_MARK,		PORT200_FN2),
1446 	PINMUX_DATA(RMII_TXD0_MARK,		PORT200_FN3),
1447 	PINMUX_DATA(STP0_IPD7_MARK,		PORT200_FN6),
1448 	PINMUX_DATA(LCD1_D12_MARK,		PORT200_FN7),
1449 
1450 	/* Port201 */
1451 	PINMUX_DATA(MEMC_WAIT_MARK,		PORT201_FN1,	MSEL4CR_6_0),
1452 	PINMUX_DATA(MEMC_DREQ1_MARK,		PORT201_FN1,	MSEL4CR_6_1),
1453 
1454 	PINMUX_DATA(SCIFA2_TXD_MARK,		PORT201_FN2),
1455 	PINMUX_DATA(RMII_TXD1_MARK,		PORT201_FN3),
1456 	PINMUX_DATA(STP0_IPD6_MARK,		PORT201_FN6),
1457 	PINMUX_DATA(LCD1_D11_MARK,		PORT201_FN7),
1458 
1459 	/* Port202 */
1460 	PINMUX_DATA(MEMC_BUSCLK_MARK,		PORT202_FN1,	MSEL4CR_6_0),
1461 	PINMUX_DATA(MEMC_A0_MARK,		PORT202_FN1,	MSEL4CR_6_1),
1462 
1463 	PINMUX_DATA(MSIOF1_SS2_PORT202_MARK,	PORT202_FN2,	MSEL4CR_10_1),
1464 	PINMUX_DATA(RMII_MDC_MARK,		PORT202_FN3),
1465 	PINMUX_DATA(TPU0TO2_PORT202_MARK,	PORT202_FN4,	MSEL5CR_25_1),
1466 	PINMUX_DATA(IDE_CS0_MARK,		PORT202_FN6),
1467 	PINMUX_DATA(SDHI2_CD_PORT202_MARK,	PORT202_FN7,	MSEL5CR_19_1),
1468 	PINMUX_DATA(IRQ21_MARK,			PORT202_FN0),
1469 
1470 	/* Port203 - Port208 Function1 */
1471 	PINMUX_DATA(SDHI2_CLK_MARK,		PORT203_FN1),
1472 	PINMUX_DATA(SDHI2_CMD_MARK,		PORT204_FN1),
1473 	PINMUX_DATA(SDHI2_D0_MARK,		PORT205_FN1),
1474 	PINMUX_DATA(SDHI2_D1_MARK,		PORT206_FN1),
1475 	PINMUX_DATA(SDHI2_D2_MARK,		PORT207_FN1),
1476 	PINMUX_DATA(SDHI2_D3_MARK,		PORT208_FN1),
1477 
1478 	/* Port203 - Port208 Function3 */
1479 	PINMUX_DATA(ET_TX_ER_MARK,		PORT203_FN3),
1480 	PINMUX_DATA(ET_RX_ER_MARK,		PORT204_FN3),
1481 	PINMUX_DATA(ET_CRS_MARK,		PORT205_FN3),
1482 	PINMUX_DATA(ET_MDC_MARK,		PORT206_FN3),
1483 	PINMUX_DATA(ET_MDIO_MARK,		PORT207_FN3),
1484 	PINMUX_DATA(RMII_MDIO_MARK,		PORT208_FN3),
1485 
1486 	/* Port203 - Port208 Function6 */
1487 	PINMUX_DATA(IDE_A2_MARK,		PORT203_FN6),
1488 	PINMUX_DATA(IDE_A1_MARK,		PORT204_FN6),
1489 	PINMUX_DATA(IDE_A0_MARK,		PORT205_FN6),
1490 	PINMUX_DATA(IDE_IODACK_MARK,		PORT206_FN6),
1491 	PINMUX_DATA(IDE_IODREQ_MARK,		PORT207_FN6),
1492 	PINMUX_DATA(IDE_CS1_MARK,		PORT208_FN6),
1493 
1494 	/* Port203 - Port208 Function7 */
1495 	PINMUX_DATA(SCIFA4_TXD_PORT203_MARK,	PORT203_FN7,	MSEL5CR_12_0,	MSEL5CR_11_1),
1496 	PINMUX_DATA(SCIFA4_RXD_PORT204_MARK,	PORT204_FN7,	MSEL5CR_12_0,	MSEL5CR_11_1),
1497 	PINMUX_DATA(SCIFA4_SCK_PORT205_MARK,	PORT205_FN7,	MSEL5CR_10_1),
1498 	PINMUX_DATA(SCIFA5_SCK_PORT206_MARK,	PORT206_FN7,	MSEL5CR_13_1),
1499 	PINMUX_DATA(SCIFA5_RXD_PORT207_MARK,	PORT207_FN7,	MSEL5CR_15_0,	MSEL5CR_14_1),
1500 	PINMUX_DATA(SCIFA5_TXD_PORT208_MARK,	PORT208_FN7,	MSEL5CR_15_0,	MSEL5CR_14_1),
1501 
1502 	/* Port209 */
1503 	PINMUX_DATA(VBUS_MARK,			PORT209_FN1),
1504 	PINMUX_DATA(IRQ7_PORT209_MARK,		PORT209_FN0,	MSEL1CR_7_0),
1505 
1506 	/* Port210 */
1507 	PINMUX_DATA(IRQ9_PORT210_MARK,		PORT210_FN0,	MSEL1CR_9_1),
1508 	PINMUX_DATA(HDMI_HPD_MARK,		PORT210_FN1),
1509 
1510 	/* Port211 */
1511 	PINMUX_DATA(IRQ16_PORT211_MARK,		PORT211_FN0,	MSEL1CR_16_1),
1512 	PINMUX_DATA(HDMI_CEC_MARK,		PORT211_FN1),
1513 
1514 	/* SDENC */
1515 	PINMUX_DATA(SDENC_CPG_MARK,				MSEL4CR_19_0),
1516 	PINMUX_DATA(SDENC_DV_CLKI_MARK,				MSEL4CR_19_1),
1517 
1518 	/* SYSC */
1519 	PINMUX_DATA(RESETP_PULLUP_MARK,				MSEL4CR_4_0),
1520 	PINMUX_DATA(RESETP_PLAIN_MARK,				MSEL4CR_4_1),
1521 
1522 	/* DEBUG */
1523 	PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK,			MSEL4CR_1_0),
1524 	PINMUX_DATA(EDEBGREQ_PULLUP_MARK,			MSEL4CR_1_1),
1525 
1526 	PINMUX_DATA(TRACEAUD_FROM_VIO_MARK,			MSEL5CR_30_0,	MSEL5CR_29_0),
1527 	PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK,			MSEL5CR_30_0,	MSEL5CR_29_1),
1528 	PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK,			MSEL5CR_30_1,	MSEL5CR_29_0),
1529 };
1530 
1531 #define __I		(SH_PFC_PIN_CFG_INPUT)
1532 #define __O		(SH_PFC_PIN_CFG_OUTPUT)
1533 #define __IO		(SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1534 #define __PD		(SH_PFC_PIN_CFG_PULL_DOWN)
1535 #define __PU		(SH_PFC_PIN_CFG_PULL_UP)
1536 #define __PUD		(SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1537 
1538 #define R8A7740_PIN_I_PD(pin)		SH_PFC_PIN_CFG(pin, __I | __PD)
1539 #define R8A7740_PIN_I_PU(pin)		SH_PFC_PIN_CFG(pin, __I | __PU)
1540 #define R8A7740_PIN_I_PU_PD(pin)	SH_PFC_PIN_CFG(pin, __I | __PUD)
1541 #define R8A7740_PIN_IO(pin)		SH_PFC_PIN_CFG(pin, __IO)
1542 #define R8A7740_PIN_IO_PD(pin)		SH_PFC_PIN_CFG(pin, __IO | __PD)
1543 #define R8A7740_PIN_IO_PU(pin)		SH_PFC_PIN_CFG(pin, __IO | __PU)
1544 #define R8A7740_PIN_IO_PU_PD(pin)	SH_PFC_PIN_CFG(pin, __IO | __PUD)
1545 #define R8A7740_PIN_O(pin)		SH_PFC_PIN_CFG(pin, __O)
1546 #define R8A7740_PIN_O_PU_PD(pin)	SH_PFC_PIN_CFG(pin, __O | __PUD)
1547 
1548 static const struct sh_pfc_pin pinmux_pins[] = {
1549 	/* Table 56-1 (I/O and Pull U/D) */
1550 	R8A7740_PIN_IO_PD(0),		R8A7740_PIN_IO_PD(1),
1551 	R8A7740_PIN_IO_PD(2),		R8A7740_PIN_IO_PD(3),
1552 	R8A7740_PIN_IO_PD(4),		R8A7740_PIN_IO_PD(5),
1553 	R8A7740_PIN_IO_PD(6),		R8A7740_PIN_IO(7),
1554 	R8A7740_PIN_IO(8),		R8A7740_PIN_IO(9),
1555 	R8A7740_PIN_IO_PD(10),		R8A7740_PIN_IO_PD(11),
1556 	R8A7740_PIN_IO_PD(12),		R8A7740_PIN_IO_PU_PD(13),
1557 	R8A7740_PIN_IO_PD(14),		R8A7740_PIN_IO_PD(15),
1558 	R8A7740_PIN_IO_PD(16),		R8A7740_PIN_IO_PD(17),
1559 	R8A7740_PIN_IO(18),		R8A7740_PIN_IO_PU(19),
1560 	R8A7740_PIN_IO_PU_PD(20),	R8A7740_PIN_IO_PD(21),
1561 	R8A7740_PIN_IO_PU_PD(22),	R8A7740_PIN_IO(23),
1562 	R8A7740_PIN_IO_PU(24),		R8A7740_PIN_IO_PU(25),
1563 	R8A7740_PIN_IO_PU(26),		R8A7740_PIN_IO_PU(27),
1564 	R8A7740_PIN_IO_PU(28),		R8A7740_PIN_IO_PU(29),
1565 	R8A7740_PIN_IO_PU(30),		R8A7740_PIN_IO_PD(31),
1566 	R8A7740_PIN_IO_PD(32),		R8A7740_PIN_IO_PD(33),
1567 	R8A7740_PIN_IO_PD(34),		R8A7740_PIN_IO_PU(35),
1568 	R8A7740_PIN_IO_PU(36),		R8A7740_PIN_IO_PD(37),
1569 	R8A7740_PIN_IO_PU(38),		R8A7740_PIN_IO_PD(39),
1570 	R8A7740_PIN_IO_PU_PD(40),	R8A7740_PIN_IO_PD(41),
1571 	R8A7740_PIN_IO_PD(42),		R8A7740_PIN_IO_PU_PD(43),
1572 	R8A7740_PIN_IO_PU_PD(44),	R8A7740_PIN_IO_PU_PD(45),
1573 	R8A7740_PIN_IO_PU_PD(46),	R8A7740_PIN_IO_PU_PD(47),
1574 	R8A7740_PIN_IO_PU_PD(48),	R8A7740_PIN_IO_PU_PD(49),
1575 	R8A7740_PIN_IO_PU_PD(50),	R8A7740_PIN_IO_PD(51),
1576 	R8A7740_PIN_IO_PD(52),		R8A7740_PIN_IO_PD(53),
1577 	R8A7740_PIN_IO_PD(54),		R8A7740_PIN_IO_PU_PD(55),
1578 	R8A7740_PIN_IO_PU_PD(56),	R8A7740_PIN_IO_PU_PD(57),
1579 	R8A7740_PIN_IO_PU_PD(58),	R8A7740_PIN_IO_PU_PD(59),
1580 	R8A7740_PIN_IO_PU_PD(60),	R8A7740_PIN_IO_PD(61),
1581 	R8A7740_PIN_IO_PD(62),		R8A7740_PIN_IO_PD(63),
1582 	R8A7740_PIN_IO_PD(64),		R8A7740_PIN_IO_PD(65),
1583 	R8A7740_PIN_IO_PU_PD(66),	R8A7740_PIN_IO_PU_PD(67),
1584 	R8A7740_PIN_IO_PU_PD(68),	R8A7740_PIN_IO_PU_PD(69),
1585 	R8A7740_PIN_IO_PU_PD(70),	R8A7740_PIN_IO_PU_PD(71),
1586 	R8A7740_PIN_IO_PU_PD(72),	R8A7740_PIN_IO_PU_PD(73),
1587 	R8A7740_PIN_IO_PU_PD(74),	R8A7740_PIN_IO_PU_PD(75),
1588 	R8A7740_PIN_IO_PU_PD(76),	R8A7740_PIN_IO_PU_PD(77),
1589 	R8A7740_PIN_IO_PU_PD(78),	R8A7740_PIN_IO_PU_PD(79),
1590 	R8A7740_PIN_IO_PU_PD(80),	R8A7740_PIN_IO_PU_PD(81),
1591 	R8A7740_PIN_IO(82),		R8A7740_PIN_IO_PU_PD(83),
1592 	R8A7740_PIN_IO(84),		R8A7740_PIN_IO_PD(85),
1593 	R8A7740_PIN_IO_PD(86),		R8A7740_PIN_IO_PD(87),
1594 	R8A7740_PIN_IO_PD(88),		R8A7740_PIN_IO_PD(89),
1595 	R8A7740_PIN_IO_PD(90),		R8A7740_PIN_IO_PU_PD(91),
1596 	R8A7740_PIN_IO_PU_PD(92),	R8A7740_PIN_IO_PU_PD(93),
1597 	R8A7740_PIN_IO_PU_PD(94),	R8A7740_PIN_IO_PU_PD(95),
1598 	R8A7740_PIN_IO_PU_PD(96),	R8A7740_PIN_IO_PU_PD(97),
1599 	R8A7740_PIN_IO_PU_PD(98),	R8A7740_PIN_IO_PU_PD(99),
1600 	R8A7740_PIN_IO_PU_PD(100),	R8A7740_PIN_IO(101),
1601 	R8A7740_PIN_IO_PU(102),		R8A7740_PIN_IO_PU_PD(103),
1602 	R8A7740_PIN_IO_PU(104),		R8A7740_PIN_IO_PU(105),
1603 	R8A7740_PIN_IO_PU_PD(106),	R8A7740_PIN_IO(107),
1604 	R8A7740_PIN_IO(108),		R8A7740_PIN_IO(109),
1605 	R8A7740_PIN_IO(110),		R8A7740_PIN_IO(111),
1606 	R8A7740_PIN_IO(112),		R8A7740_PIN_IO(113),
1607 	R8A7740_PIN_IO_PU_PD(114),	R8A7740_PIN_IO(115),
1608 	R8A7740_PIN_IO_PD(116),		R8A7740_PIN_IO_PD(117),
1609 	R8A7740_PIN_IO_PD(118),		R8A7740_PIN_IO_PD(119),
1610 	R8A7740_PIN_IO_PD(120),		R8A7740_PIN_IO_PD(121),
1611 	R8A7740_PIN_IO_PD(122),		R8A7740_PIN_IO_PD(123),
1612 	R8A7740_PIN_IO_PD(124),		R8A7740_PIN_IO(125),
1613 	R8A7740_PIN_IO(126),		R8A7740_PIN_IO(127),
1614 	R8A7740_PIN_IO(128),		R8A7740_PIN_IO(129),
1615 	R8A7740_PIN_IO(130),		R8A7740_PIN_IO(131),
1616 	R8A7740_PIN_IO(132),		R8A7740_PIN_IO(133),
1617 	R8A7740_PIN_IO(134),		R8A7740_PIN_IO(135),
1618 	R8A7740_PIN_IO(136),		R8A7740_PIN_IO(137),
1619 	R8A7740_PIN_IO(138),		R8A7740_PIN_IO(139),
1620 	R8A7740_PIN_IO(140),		R8A7740_PIN_IO(141),
1621 	R8A7740_PIN_IO_PU(142),		R8A7740_PIN_IO_PU(143),
1622 	R8A7740_PIN_IO_PU(144),		R8A7740_PIN_IO_PU(145),
1623 	R8A7740_PIN_IO_PU(146),		R8A7740_PIN_IO_PU(147),
1624 	R8A7740_PIN_IO_PU(148),		R8A7740_PIN_IO_PU(149),
1625 	R8A7740_PIN_IO_PU(150),		R8A7740_PIN_IO_PU(151),
1626 	R8A7740_PIN_IO_PU(152),		R8A7740_PIN_IO_PU(153),
1627 	R8A7740_PIN_IO_PU(154),		R8A7740_PIN_IO_PU(155),
1628 	R8A7740_PIN_IO_PU(156),		R8A7740_PIN_IO_PU(157),
1629 	R8A7740_PIN_IO_PD(158),		R8A7740_PIN_IO_PD(159),
1630 	R8A7740_PIN_IO_PU_PD(160),	R8A7740_PIN_IO_PD(161),
1631 	R8A7740_PIN_IO_PD(162),		R8A7740_PIN_IO_PD(163),
1632 	R8A7740_PIN_IO_PD(164),		R8A7740_PIN_IO_PD(165),
1633 	R8A7740_PIN_IO_PU(166),		R8A7740_PIN_IO_PU(167),
1634 	R8A7740_PIN_IO_PU(168),		R8A7740_PIN_IO_PU(169),
1635 	R8A7740_PIN_IO_PU(170),		R8A7740_PIN_IO_PU(171),
1636 	R8A7740_PIN_IO_PD(172),		R8A7740_PIN_IO_PD(173),
1637 	R8A7740_PIN_IO_PD(174),		R8A7740_PIN_IO_PD(175),
1638 	R8A7740_PIN_IO_PU(176),		R8A7740_PIN_IO_PU_PD(177),
1639 	R8A7740_PIN_IO_PU(178),		R8A7740_PIN_IO_PD(179),
1640 	R8A7740_PIN_IO_PD(180),		R8A7740_PIN_IO_PU(181),
1641 	R8A7740_PIN_IO_PU(182),		R8A7740_PIN_IO(183),
1642 	R8A7740_PIN_IO_PD(184),		R8A7740_PIN_IO_PD(185),
1643 	R8A7740_PIN_IO_PD(186),		R8A7740_PIN_IO_PD(187),
1644 	R8A7740_PIN_IO_PD(188),		R8A7740_PIN_IO_PD(189),
1645 	R8A7740_PIN_IO_PD(190),		R8A7740_PIN_IO_PD(191),
1646 	R8A7740_PIN_IO_PD(192),		R8A7740_PIN_IO_PU_PD(193),
1647 	R8A7740_PIN_IO_PU_PD(194),	R8A7740_PIN_IO_PD(195),
1648 	R8A7740_PIN_IO_PU_PD(196),	R8A7740_PIN_IO_PD(197),
1649 	R8A7740_PIN_IO_PU_PD(198),	R8A7740_PIN_IO_PU_PD(199),
1650 	R8A7740_PIN_IO_PU_PD(200),	R8A7740_PIN_IO_PU(201),
1651 	R8A7740_PIN_IO_PU_PD(202),	R8A7740_PIN_IO(203),
1652 	R8A7740_PIN_IO_PU_PD(204),	R8A7740_PIN_IO_PU_PD(205),
1653 	R8A7740_PIN_IO_PU_PD(206),	R8A7740_PIN_IO_PU_PD(207),
1654 	R8A7740_PIN_IO_PU_PD(208),	R8A7740_PIN_IO_PD(209),
1655 	R8A7740_PIN_IO_PD(210),		R8A7740_PIN_IO_PD(211),
1656 };
1657 
1658 /* - BSC -------------------------------------------------------------------- */
1659 static const unsigned int bsc_data8_pins[] = {
1660 	/* D[0:7] */
1661 	157, 156, 155, 154, 153, 152, 151, 150,
1662 };
1663 static const unsigned int bsc_data8_mux[] = {
1664 	D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1665 	D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1666 };
1667 static const unsigned int bsc_data16_pins[] = {
1668 	/* D[0:15] */
1669 	157, 156, 155, 154, 153, 152, 151, 150,
1670 	149, 148, 147, 146, 145, 144, 143, 142,
1671 };
1672 static const unsigned int bsc_data16_mux[] = {
1673 	D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1674 	D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1675 	D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1676 	D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1677 };
1678 static const unsigned int bsc_data32_pins[] = {
1679 	/* D[0:31] */
1680 	157, 156, 155, 154, 153, 152, 151, 150,
1681 	149, 148, 147, 146, 145, 144, 143, 142,
1682 	171, 170, 169, 168, 167, 166, 173, 172,
1683 	165, 164, 163, 162, 161, 160, 159, 158,
1684 };
1685 static const unsigned int bsc_data32_mux[] = {
1686 	D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1687 	D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1688 	D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1689 	D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1690 	D16_MARK, D17_MARK, D18_MARK, D19_MARK,
1691 	D20_MARK, D21_MARK, D22_MARK, D23_MARK,
1692 	D24_MARK, D25_MARK, D26_MARK, D27_MARK,
1693 	D28_MARK, D29_MARK, D30_MARK, D31_MARK,
1694 };
1695 static const unsigned int bsc_cs0_pins[] = {
1696 	/* CS */
1697 	109,
1698 };
1699 static const unsigned int bsc_cs0_mux[] = {
1700 	CS0_MARK,
1701 };
1702 static const unsigned int bsc_cs2_pins[] = {
1703 	/* CS */
1704 	110,
1705 };
1706 static const unsigned int bsc_cs2_mux[] = {
1707 	CS2_MARK,
1708 };
1709 static const unsigned int bsc_cs4_pins[] = {
1710 	/* CS */
1711 	111,
1712 };
1713 static const unsigned int bsc_cs4_mux[] = {
1714 	CS4_MARK,
1715 };
1716 static const unsigned int bsc_cs5a_0_pins[] = {
1717 	/* CS */
1718 	105,
1719 };
1720 static const unsigned int bsc_cs5a_0_mux[] = {
1721 	CS5A_PORT105_MARK,
1722 };
1723 static const unsigned int bsc_cs5a_1_pins[] = {
1724 	/* CS */
1725 	19,
1726 };
1727 static const unsigned int bsc_cs5a_1_mux[] = {
1728 	CS5A_PORT19_MARK,
1729 };
1730 static const unsigned int bsc_cs5b_pins[] = {
1731 	/* CS */
1732 	103,
1733 };
1734 static const unsigned int bsc_cs5b_mux[] = {
1735 	CS5B_MARK,
1736 };
1737 static const unsigned int bsc_cs6a_pins[] = {
1738 	/* CS */
1739 	104,
1740 };
1741 static const unsigned int bsc_cs6a_mux[] = {
1742 	CS6A_MARK,
1743 };
1744 static const unsigned int bsc_rd_we8_pins[] = {
1745 	/* RD, WE[0] */
1746 	115, 113,
1747 };
1748 static const unsigned int bsc_rd_we8_mux[] = {
1749 	RD_FSC_MARK, WE0_FWE_MARK,
1750 };
1751 static const unsigned int bsc_rd_we16_pins[] = {
1752 	/* RD, WE[0:1] */
1753 	115, 113, 112,
1754 };
1755 static const unsigned int bsc_rd_we16_mux[] = {
1756 	RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
1757 };
1758 static const unsigned int bsc_rd_we32_pins[] = {
1759 	/* RD, WE[0:3] */
1760 	115, 113, 112, 108, 107,
1761 };
1762 static const unsigned int bsc_rd_we32_mux[] = {
1763 	RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
1764 };
1765 static const unsigned int bsc_bs_pins[] = {
1766 	/* BS */
1767 	175,
1768 };
1769 static const unsigned int bsc_bs_mux[] = {
1770 	BS_MARK,
1771 };
1772 static const unsigned int bsc_rdwr_pins[] = {
1773 	/* RDWR */
1774 	114,
1775 };
1776 static const unsigned int bsc_rdwr_mux[] = {
1777 	RDWR_MARK,
1778 };
1779 /* - CEU0 ------------------------------------------------------------------- */
1780 static const unsigned int ceu0_data_0_7_pins[] = {
1781 	/* D[0:7] */
1782 	34, 33, 32, 31, 30, 29, 28, 27,
1783 };
1784 static const unsigned int ceu0_data_0_7_mux[] = {
1785 	VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
1786 	VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
1787 };
1788 static const unsigned int ceu0_data_8_15_0_pins[] = {
1789 	/* D[8:15] */
1790 	182, 181, 180, 179, 178, 26, 25, 24,
1791 };
1792 static const unsigned int ceu0_data_8_15_0_mux[] = {
1793 	VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1794 	VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK,
1795 	VIO0_D15_PORT24_MARK,
1796 };
1797 static const unsigned int ceu0_data_8_15_1_pins[] = {
1798 	/* D[8:15] */
1799 	182, 181, 180, 179, 178, 22, 95, 96,
1800 };
1801 static const unsigned int ceu0_data_8_15_1_mux[] = {
1802 	VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1803 	VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK,
1804 	VIO0_D15_PORT96_MARK,
1805 };
1806 static const unsigned int ceu0_clk_0_pins[] = {
1807 	/* CKO */
1808 	36,
1809 };
1810 static const unsigned int ceu0_clk_0_mux[] = {
1811 	VIO_CKO_MARK,
1812 };
1813 static const unsigned int ceu0_clk_1_pins[] = {
1814 	/* CKO */
1815 	14,
1816 };
1817 static const unsigned int ceu0_clk_1_mux[] = {
1818 	VIO_CKO1_MARK,
1819 };
1820 static const unsigned int ceu0_clk_2_pins[] = {
1821 	/* CKO */
1822 	15,
1823 };
1824 static const unsigned int ceu0_clk_2_mux[] = {
1825 	VIO_CKO2_MARK,
1826 };
1827 static const unsigned int ceu0_sync_pins[] = {
1828 	/* CLK, VD, HD */
1829 	35, 39, 37,
1830 };
1831 static const unsigned int ceu0_sync_mux[] = {
1832 	VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK,
1833 };
1834 static const unsigned int ceu0_field_pins[] = {
1835 	/* FIELD */
1836 	38,
1837 };
1838 static const unsigned int ceu0_field_mux[] = {
1839 	VIO0_FIELD_MARK,
1840 };
1841 /* - CEU1 ------------------------------------------------------------------- */
1842 static const unsigned int ceu1_data_pins[] = {
1843 	/* D[0:7] */
1844 	182, 181, 180, 179, 178, 26, 25, 24,
1845 };
1846 static const unsigned int ceu1_data_mux[] = {
1847 	VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
1848 	VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
1849 };
1850 static const unsigned int ceu1_clk_pins[] = {
1851 	/* CKO */
1852 	23,
1853 };
1854 static const unsigned int ceu1_clk_mux[] = {
1855 	VIO_CKO_1_MARK,
1856 };
1857 static const unsigned int ceu1_sync_pins[] = {
1858 	/* CLK, VD, HD */
1859 	197, 198, 160,
1860 };
1861 static const unsigned int ceu1_sync_mux[] = {
1862 	VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK,
1863 };
1864 static const unsigned int ceu1_field_pins[] = {
1865 	/* FIELD */
1866 	21,
1867 };
1868 static const unsigned int ceu1_field_mux[] = {
1869 	VIO1_FIELD_MARK,
1870 };
1871 /* - FSIA ------------------------------------------------------------------- */
1872 static const unsigned int fsia_mclk_in_pins[] = {
1873 	/* CK */
1874 	11,
1875 };
1876 static const unsigned int fsia_mclk_in_mux[] = {
1877 	FSIACK_MARK,
1878 };
1879 static const unsigned int fsia_mclk_out_pins[] = {
1880 	/* OMC */
1881 	10,
1882 };
1883 static const unsigned int fsia_mclk_out_mux[] = {
1884 	FSIAOMC_MARK,
1885 };
1886 static const unsigned int fsia_sclk_in_pins[] = {
1887 	/* ILR, IBT */
1888 	12, 13,
1889 };
1890 static const unsigned int fsia_sclk_in_mux[] = {
1891 	FSIAILR_MARK, FSIAIBT_MARK,
1892 };
1893 static const unsigned int fsia_sclk_out_pins[] = {
1894 	/* OLR, OBT */
1895 	7, 8,
1896 };
1897 static const unsigned int fsia_sclk_out_mux[] = {
1898 	FSIAOLR_MARK, FSIAOBT_MARK,
1899 };
1900 static const unsigned int fsia_data_in_0_pins[] = {
1901 	/* ISLD */
1902 	0,
1903 };
1904 static const unsigned int fsia_data_in_0_mux[] = {
1905 	FSIAISLD_PORT0_MARK,
1906 };
1907 static const unsigned int fsia_data_in_1_pins[] = {
1908 	/* ISLD */
1909 	5,
1910 };
1911 static const unsigned int fsia_data_in_1_mux[] = {
1912 	FSIAISLD_PORT5_MARK,
1913 };
1914 static const unsigned int fsia_data_out_0_pins[] = {
1915 	/* OSLD */
1916 	9,
1917 };
1918 static const unsigned int fsia_data_out_0_mux[] = {
1919 	FSIAOSLD_MARK,
1920 };
1921 static const unsigned int fsia_data_out_1_pins[] = {
1922 	/* OSLD */
1923 	0,
1924 };
1925 static const unsigned int fsia_data_out_1_mux[] = {
1926 	FSIAOSLD1_MARK,
1927 };
1928 static const unsigned int fsia_data_out_2_pins[] = {
1929 	/* OSLD */
1930 	1,
1931 };
1932 static const unsigned int fsia_data_out_2_mux[] = {
1933 	FSIAOSLD2_MARK,
1934 };
1935 static const unsigned int fsia_spdif_0_pins[] = {
1936 	/* SPDIF */
1937 	9,
1938 };
1939 static const unsigned int fsia_spdif_0_mux[] = {
1940 	FSIASPDIF_PORT9_MARK,
1941 };
1942 static const unsigned int fsia_spdif_1_pins[] = {
1943 	/* SPDIF */
1944 	18,
1945 };
1946 static const unsigned int fsia_spdif_1_mux[] = {
1947 	FSIASPDIF_PORT18_MARK,
1948 };
1949 /* - FSIB ------------------------------------------------------------------- */
1950 static const unsigned int fsib_mclk_in_pins[] = {
1951 	/* CK */
1952 	11,
1953 };
1954 static const unsigned int fsib_mclk_in_mux[] = {
1955 	FSIBCK_MARK,
1956 };
1957 /* - GETHER ----------------------------------------------------------------- */
1958 static const unsigned int gether_rmii_pins[] = {
1959 	/* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
1960 	195, 196, 194, 193, 200, 201, 199, 159, 202, 208,
1961 };
1962 static const unsigned int gether_rmii_mux[] = {
1963 	RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK,
1964 	RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK,
1965 	RMII_MDC_MARK, RMII_MDIO_MARK,
1966 };
1967 static const unsigned int gether_mii_pins[] = {
1968 	/* RXD[0:3], RX_CLK, RX_DV, RX_ER
1969 	 * TXD[0:3], TX_CLK, TX_EN, TX_ER
1970 	 * CRS, COL, MDC, MDIO,
1971 	 */
1972 	185, 186, 187, 188, 174, 161, 204,
1973 	171, 170, 169, 168, 184, 183, 203,
1974 	205, 163, 206, 207,
1975 };
1976 static const unsigned int gether_mii_mux[] = {
1977 	ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
1978 	ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
1979 	ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
1980 	ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
1981 	ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
1982 };
1983 static const unsigned int gether_gmii_pins[] = {
1984 	/* RXD[0:7], RX_CLK, RX_DV, RX_ER
1985 	 * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
1986 	 * CRS, COL, MDC, MDIO, REF125CK_MARK,
1987 	 */
1988 	185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
1989 	171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
1990 	205, 163, 206, 207,
1991 };
1992 static const unsigned int gether_gmii_mux[] = {
1993 	ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
1994 	ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK,
1995 	ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
1996 	ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
1997 	ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK,
1998 	ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
1999 	ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
2000 	RMII_REF125CK_MARK,
2001 };
2002 static const unsigned int gether_int_pins[] = {
2003 	/* PHY_INT */
2004 	164,
2005 };
2006 static const unsigned int gether_int_mux[] = {
2007 	ET_PHY_INT_MARK,
2008 };
2009 static const unsigned int gether_link_pins[] = {
2010 	/* LINK */
2011 	177,
2012 };
2013 static const unsigned int gether_link_mux[] = {
2014 	ET_LINK_MARK,
2015 };
2016 static const unsigned int gether_wol_pins[] = {
2017 	/* WOL */
2018 	175,
2019 };
2020 static const unsigned int gether_wol_mux[] = {
2021 	ET_WOL_MARK,
2022 };
2023 /* - HDMI ------------------------------------------------------------------- */
2024 static const unsigned int hdmi_pins[] = {
2025 	/* HPD, CEC */
2026 	210, 211,
2027 };
2028 static const unsigned int hdmi_mux[] = {
2029 	HDMI_HPD_MARK, HDMI_CEC_MARK,
2030 };
2031 /* - INTC ------------------------------------------------------------------- */
2032 IRQC_PINS_MUX(0, 0, 2);
2033 IRQC_PINS_MUX(0, 1, 13);
2034 IRQC_PIN_MUX(1, 20);
2035 IRQC_PINS_MUX(2, 0, 11);
2036 IRQC_PINS_MUX(2, 1, 12);
2037 IRQC_PINS_MUX(3, 0, 10);
2038 IRQC_PINS_MUX(3, 1, 14);
2039 IRQC_PINS_MUX(4, 0, 15);
2040 IRQC_PINS_MUX(4, 1, 172);
2041 IRQC_PINS_MUX(5, 0, 0);
2042 IRQC_PINS_MUX(5, 1, 1);
2043 IRQC_PINS_MUX(6, 0, 121);
2044 IRQC_PINS_MUX(6, 1, 173);
2045 IRQC_PINS_MUX(7, 0, 120);
2046 IRQC_PINS_MUX(7, 1, 209);
2047 IRQC_PIN_MUX(8, 119);
2048 IRQC_PINS_MUX(9, 0, 118);
2049 IRQC_PINS_MUX(9, 1, 210);
2050 IRQC_PIN_MUX(10, 19);
2051 IRQC_PIN_MUX(11, 104);
2052 IRQC_PINS_MUX(12, 0, 42);
2053 IRQC_PINS_MUX(12, 1, 97);
2054 IRQC_PINS_MUX(13, 0, 64);
2055 IRQC_PINS_MUX(13, 1, 98);
2056 IRQC_PINS_MUX(14, 0, 63);
2057 IRQC_PINS_MUX(14, 1, 99);
2058 IRQC_PINS_MUX(15, 0, 62);
2059 IRQC_PINS_MUX(15, 1, 100);
2060 IRQC_PINS_MUX(16, 0, 68);
2061 IRQC_PINS_MUX(16, 1, 211);
2062 IRQC_PIN_MUX(17, 69);
2063 IRQC_PIN_MUX(18, 70);
2064 IRQC_PIN_MUX(19, 71);
2065 IRQC_PIN_MUX(20, 67);
2066 IRQC_PIN_MUX(21, 202);
2067 IRQC_PIN_MUX(22, 95);
2068 IRQC_PIN_MUX(23, 96);
2069 IRQC_PIN_MUX(24, 180);
2070 IRQC_PIN_MUX(25, 38);
2071 IRQC_PINS_MUX(26, 0, 58);
2072 IRQC_PINS_MUX(26, 1, 81);
2073 IRQC_PINS_MUX(27, 0, 57);
2074 IRQC_PINS_MUX(27, 1, 168);
2075 IRQC_PINS_MUX(28, 0, 56);
2076 IRQC_PINS_MUX(28, 1, 169);
2077 IRQC_PINS_MUX(29, 0, 50);
2078 IRQC_PINS_MUX(29, 1, 170);
2079 IRQC_PINS_MUX(30, 0, 49);
2080 IRQC_PINS_MUX(30, 1, 171);
2081 IRQC_PINS_MUX(31, 0, 41);
2082 IRQC_PINS_MUX(31, 1, 167);
2083 
2084 /* - LCD0 ------------------------------------------------------------------- */
2085 static const unsigned int lcd0_data8_pins[] = {
2086 	/* D[0:7] */
2087 	58, 57, 56, 55, 54, 53, 52, 51,
2088 };
2089 static const unsigned int lcd0_data8_mux[] = {
2090 	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2091 	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2092 };
2093 static const unsigned int lcd0_data9_pins[] = {
2094 	/* D[0:8] */
2095 	58, 57, 56, 55, 54, 53, 52, 51,
2096 	50,
2097 };
2098 static const unsigned int lcd0_data9_mux[] = {
2099 	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2100 	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2101 	LCD0_D8_MARK,
2102 };
2103 static const unsigned int lcd0_data12_pins[] = {
2104 	/* D[0:11] */
2105 	58, 57, 56, 55, 54, 53, 52, 51,
2106 	50, 49, 48, 47,
2107 };
2108 static const unsigned int lcd0_data12_mux[] = {
2109 	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2110 	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2111 	LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2112 };
2113 static const unsigned int lcd0_data16_pins[] = {
2114 	/* D[0:15] */
2115 	58, 57, 56, 55, 54, 53, 52, 51,
2116 	50, 49, 48, 47, 46, 45, 44, 43,
2117 };
2118 static const unsigned int lcd0_data16_mux[] = {
2119 	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2120 	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2121 	LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2122 	LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2123 };
2124 static const unsigned int lcd0_data18_pins[] = {
2125 	/* D[0:17] */
2126 	58, 57, 56, 55, 54, 53, 52, 51,
2127 	50, 49, 48, 47, 46, 45, 44, 43,
2128 	42, 41,
2129 };
2130 static const unsigned int lcd0_data18_mux[] = {
2131 	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2132 	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2133 	LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2134 	LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2135 	LCD0_D16_MARK, LCD0_D17_MARK,
2136 };
2137 static const unsigned int lcd0_data24_0_pins[] = {
2138 	/* D[0:23] */
2139 	58, 57, 56, 55, 54, 53, 52, 51,
2140 	50, 49, 48, 47, 46, 45, 44, 43,
2141 	42, 41, 40, 4, 3, 2, 0, 1,
2142 };
2143 static const unsigned int lcd0_data24_0_mux[] = {
2144 	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2145 	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2146 	LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2147 	LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2148 	LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
2149 	LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
2150 	LCD0_D23_PORT1_MARK,
2151 };
2152 static const unsigned int lcd0_data24_1_pins[] = {
2153 	/* D[0:23] */
2154 	58, 57, 56, 55, 54, 53, 52, 51,
2155 	50, 49, 48, 47, 46, 45, 44, 43,
2156 	42, 41, 163, 162, 161, 158, 160, 159,
2157 };
2158 static const unsigned int lcd0_data24_1_mux[] = {
2159 	LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2160 	LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2161 	LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2162 	LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
2163 	LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
2164 	LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
2165 };
2166 static const unsigned int lcd0_display_pins[] = {
2167 	/* DON, VCPWC, VEPWC */
2168 	61, 59, 60,
2169 };
2170 static const unsigned int lcd0_display_mux[] = {
2171 	LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
2172 };
2173 static const unsigned int lcd0_lclk_0_pins[] = {
2174 	/* LCLK */
2175 	102,
2176 };
2177 static const unsigned int lcd0_lclk_0_mux[] = {
2178 	LCD0_LCLK_PORT102_MARK,
2179 };
2180 static const unsigned int lcd0_lclk_1_pins[] = {
2181 	/* LCLK */
2182 	165,
2183 };
2184 static const unsigned int lcd0_lclk_1_mux[] = {
2185 	LCD0_LCLK_PORT165_MARK,
2186 };
2187 static const unsigned int lcd0_sync_pins[] = {
2188 	/* VSYN, HSYN, DCK, DISP */
2189 	63, 64, 62, 65,
2190 };
2191 static const unsigned int lcd0_sync_mux[] = {
2192 	LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
2193 };
2194 static const unsigned int lcd0_sys_pins[] = {
2195 	/* CS, WR, RD, RS */
2196 	64, 62, 164, 65,
2197 };
2198 static const unsigned int lcd0_sys_mux[] = {
2199 	LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
2200 };
2201 /* - LCD1 ------------------------------------------------------------------- */
2202 static const unsigned int lcd1_data8_pins[] = {
2203 	/* D[0:7] */
2204 	4, 3, 2, 1, 0, 91, 92, 23,
2205 };
2206 static const unsigned int lcd1_data8_mux[] = {
2207 	LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2208 	LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2209 };
2210 static const unsigned int lcd1_data9_pins[] = {
2211 	/* D[0:8] */
2212 	4, 3, 2, 1, 0, 91, 92, 23,
2213 	93,
2214 };
2215 static const unsigned int lcd1_data9_mux[] = {
2216 	LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2217 	LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2218 	LCD1_D8_MARK,
2219 };
2220 static const unsigned int lcd1_data12_pins[] = {
2221 	/* D[0:12] */
2222 	4, 3, 2, 1, 0, 91, 92, 23,
2223 	93, 94, 21, 201,
2224 };
2225 static const unsigned int lcd1_data12_mux[] = {
2226 	LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2227 	LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2228 	LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2229 };
2230 static const unsigned int lcd1_data16_pins[] = {
2231 	/* D[0:15] */
2232 	4, 3, 2, 1, 0, 91, 92, 23,
2233 	93, 94, 21, 201, 200, 199, 196, 195,
2234 };
2235 static const unsigned int lcd1_data16_mux[] = {
2236 	LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2237 	LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2238 	LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2239 	LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2240 };
2241 static const unsigned int lcd1_data18_pins[] = {
2242 	/* D[0:17] */
2243 	4, 3, 2, 1, 0, 91, 92, 23,
2244 	93, 94, 21, 201, 200, 199, 196, 195,
2245 	194, 193,
2246 };
2247 static const unsigned int lcd1_data18_mux[] = {
2248 	LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2249 	LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2250 	LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2251 	LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2252 	LCD1_D16_MARK, LCD1_D17_MARK,
2253 };
2254 static const unsigned int lcd1_data24_pins[] = {
2255 	/* D[0:23] */
2256 	4, 3, 2, 1, 0, 91, 92, 23,
2257 	93, 94, 21, 201, 200, 199, 196, 195,
2258 	194, 193, 198, 197, 75, 74, 15, 14,
2259 };
2260 static const unsigned int lcd1_data24_mux[] = {
2261 	LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2262 	LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2263 	LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2264 	LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2265 	LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
2266 	LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
2267 };
2268 static const unsigned int lcd1_display_pins[] = {
2269 	/* DON, VCPWC, VEPWC */
2270 	100, 5, 6,
2271 };
2272 static const unsigned int lcd1_display_mux[] = {
2273 	LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
2274 };
2275 static const unsigned int lcd1_lclk_pins[] = {
2276 	/* LCLK */
2277 	40,
2278 };
2279 static const unsigned int lcd1_lclk_mux[] = {
2280 	LCD1_LCLK_MARK,
2281 };
2282 static const unsigned int lcd1_sync_pins[] = {
2283 	/* VSYN, HSYN, DCK, DISP */
2284 	98, 97, 99, 12,
2285 };
2286 static const unsigned int lcd1_sync_mux[] = {
2287 	LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
2288 };
2289 static const unsigned int lcd1_sys_pins[] = {
2290 	/* CS, WR, RD, RS */
2291 	97, 99, 13, 12,
2292 };
2293 static const unsigned int lcd1_sys_mux[] = {
2294 	LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
2295 };
2296 /* - MMCIF ------------------------------------------------------------------ */
2297 static const unsigned int mmc0_data1_0_pins[] = {
2298 	/* D[0] */
2299 	68,
2300 };
2301 static const unsigned int mmc0_data1_0_mux[] = {
2302 	MMC0_D0_PORT68_MARK,
2303 };
2304 static const unsigned int mmc0_data4_0_pins[] = {
2305 	/* D[0:3] */
2306 	68, 69, 70, 71,
2307 };
2308 static const unsigned int mmc0_data4_0_mux[] = {
2309 	MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2310 };
2311 static const unsigned int mmc0_data8_0_pins[] = {
2312 	/* D[0:7] */
2313 	68, 69, 70, 71, 72, 73, 74, 75,
2314 };
2315 static const unsigned int mmc0_data8_0_mux[] = {
2316 	MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2317 	MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
2318 };
2319 static const unsigned int mmc0_ctrl_0_pins[] = {
2320 	/* CMD, CLK */
2321 	67, 66,
2322 };
2323 static const unsigned int mmc0_ctrl_0_mux[] = {
2324 	MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
2325 };
2326 
2327 static const unsigned int mmc0_data1_1_pins[] = {
2328 	/* D[0] */
2329 	149,
2330 };
2331 static const unsigned int mmc0_data1_1_mux[] = {
2332 	MMC1_D0_PORT149_MARK,
2333 };
2334 static const unsigned int mmc0_data4_1_pins[] = {
2335 	/* D[0:3] */
2336 	149, 148, 147, 146,
2337 };
2338 static const unsigned int mmc0_data4_1_mux[] = {
2339 	MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2340 };
2341 static const unsigned int mmc0_data8_1_pins[] = {
2342 	/* D[0:7] */
2343 	149, 148, 147, 146, 145, 144, 143, 142,
2344 };
2345 static const unsigned int mmc0_data8_1_mux[] = {
2346 	MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2347 	MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
2348 };
2349 static const unsigned int mmc0_ctrl_1_pins[] = {
2350 	/* CMD, CLK */
2351 	104, 103,
2352 };
2353 static const unsigned int mmc0_ctrl_1_mux[] = {
2354 	MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
2355 };
2356 /* - SCIFA0 ----------------------------------------------------------------- */
2357 static const unsigned int scifa0_data_pins[] = {
2358 	/* RXD, TXD */
2359 	197, 198,
2360 };
2361 static const unsigned int scifa0_data_mux[] = {
2362 	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2363 };
2364 static const unsigned int scifa0_clk_pins[] = {
2365 	/* SCK */
2366 	188,
2367 };
2368 static const unsigned int scifa0_clk_mux[] = {
2369 	SCIFA0_SCK_MARK,
2370 };
2371 static const unsigned int scifa0_ctrl_pins[] = {
2372 	/* RTS, CTS */
2373 	194, 193,
2374 };
2375 static const unsigned int scifa0_ctrl_mux[] = {
2376 	SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
2377 };
2378 /* - SCIFA1 ----------------------------------------------------------------- */
2379 static const unsigned int scifa1_data_pins[] = {
2380 	/* RXD, TXD */
2381 	195, 196,
2382 };
2383 static const unsigned int scifa1_data_mux[] = {
2384 	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2385 };
2386 static const unsigned int scifa1_clk_pins[] = {
2387 	/* SCK */
2388 	185,
2389 };
2390 static const unsigned int scifa1_clk_mux[] = {
2391 	SCIFA1_SCK_MARK,
2392 };
2393 static const unsigned int scifa1_ctrl_pins[] = {
2394 	/* RTS, CTS */
2395 	23, 21,
2396 };
2397 static const unsigned int scifa1_ctrl_mux[] = {
2398 	SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
2399 };
2400 /* - SCIFA2 ----------------------------------------------------------------- */
2401 static const unsigned int scifa2_data_pins[] = {
2402 	/* RXD, TXD */
2403 	200, 201,
2404 };
2405 static const unsigned int scifa2_data_mux[] = {
2406 	SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2407 };
2408 static const unsigned int scifa2_clk_0_pins[] = {
2409 	/* SCK */
2410 	22,
2411 };
2412 static const unsigned int scifa2_clk_0_mux[] = {
2413 	SCIFA2_SCK_PORT22_MARK,
2414 };
2415 static const unsigned int scifa2_clk_1_pins[] = {
2416 	/* SCK */
2417 	199,
2418 };
2419 static const unsigned int scifa2_clk_1_mux[] = {
2420 	SCIFA2_SCK_PORT199_MARK,
2421 };
2422 static const unsigned int scifa2_ctrl_pins[] = {
2423 	/* RTS, CTS */
2424 	96, 95,
2425 };
2426 static const unsigned int scifa2_ctrl_mux[] = {
2427 	SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
2428 };
2429 /* - SCIFA3 ----------------------------------------------------------------- */
2430 static const unsigned int scifa3_data_0_pins[] = {
2431 	/* RXD, TXD */
2432 	174, 175,
2433 };
2434 static const unsigned int scifa3_data_0_mux[] = {
2435 	SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
2436 };
2437 static const unsigned int scifa3_clk_0_pins[] = {
2438 	/* SCK */
2439 	116,
2440 };
2441 static const unsigned int scifa3_clk_0_mux[] = {
2442 	SCIFA3_SCK_PORT116_MARK,
2443 };
2444 static const unsigned int scifa3_ctrl_0_pins[] = {
2445 	/* RTS, CTS */
2446 	105, 117,
2447 };
2448 static const unsigned int scifa3_ctrl_0_mux[] = {
2449 	SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
2450 };
2451 static const unsigned int scifa3_data_1_pins[] = {
2452 	/* RXD, TXD */
2453 	159, 160,
2454 };
2455 static const unsigned int scifa3_data_1_mux[] = {
2456 	SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
2457 };
2458 static const unsigned int scifa3_clk_1_pins[] = {
2459 	/* SCK */
2460 	158,
2461 };
2462 static const unsigned int scifa3_clk_1_mux[] = {
2463 	SCIFA3_SCK_PORT158_MARK,
2464 };
2465 static const unsigned int scifa3_ctrl_1_pins[] = {
2466 	/* RTS, CTS */
2467 	161, 162,
2468 };
2469 static const unsigned int scifa3_ctrl_1_mux[] = {
2470 	SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
2471 };
2472 /* - SCIFA4 ----------------------------------------------------------------- */
2473 static const unsigned int scifa4_data_0_pins[] = {
2474 	/* RXD, TXD */
2475 	12, 13,
2476 };
2477 static const unsigned int scifa4_data_0_mux[] = {
2478 	SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
2479 };
2480 static const unsigned int scifa4_data_1_pins[] = {
2481 	/* RXD, TXD */
2482 	204, 203,
2483 };
2484 static const unsigned int scifa4_data_1_mux[] = {
2485 	SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
2486 };
2487 static const unsigned int scifa4_data_2_pins[] = {
2488 	/* RXD, TXD */
2489 	94, 93,
2490 };
2491 static const unsigned int scifa4_data_2_mux[] = {
2492 	SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
2493 };
2494 static const unsigned int scifa4_clk_0_pins[] = {
2495 	/* SCK */
2496 	21,
2497 };
2498 static const unsigned int scifa4_clk_0_mux[] = {
2499 	SCIFA4_SCK_PORT21_MARK,
2500 };
2501 static const unsigned int scifa4_clk_1_pins[] = {
2502 	/* SCK */
2503 	205,
2504 };
2505 static const unsigned int scifa4_clk_1_mux[] = {
2506 	SCIFA4_SCK_PORT205_MARK,
2507 };
2508 /* - SCIFA5 ----------------------------------------------------------------- */
2509 static const unsigned int scifa5_data_0_pins[] = {
2510 	/* RXD, TXD */
2511 	10, 20,
2512 };
2513 static const unsigned int scifa5_data_0_mux[] = {
2514 	SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
2515 };
2516 static const unsigned int scifa5_data_1_pins[] = {
2517 	/* RXD, TXD */
2518 	207, 208,
2519 };
2520 static const unsigned int scifa5_data_1_mux[] = {
2521 	SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
2522 };
2523 static const unsigned int scifa5_data_2_pins[] = {
2524 	/* RXD, TXD */
2525 	92, 91,
2526 };
2527 static const unsigned int scifa5_data_2_mux[] = {
2528 	SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
2529 };
2530 static const unsigned int scifa5_clk_0_pins[] = {
2531 	/* SCK */
2532 	23,
2533 };
2534 static const unsigned int scifa5_clk_0_mux[] = {
2535 	SCIFA5_SCK_PORT23_MARK,
2536 };
2537 static const unsigned int scifa5_clk_1_pins[] = {
2538 	/* SCK */
2539 	206,
2540 };
2541 static const unsigned int scifa5_clk_1_mux[] = {
2542 	SCIFA5_SCK_PORT206_MARK,
2543 };
2544 /* - SCIFA6 ----------------------------------------------------------------- */
2545 static const unsigned int scifa6_data_pins[] = {
2546 	/* RXD, TXD */
2547 	25, 26,
2548 };
2549 static const unsigned int scifa6_data_mux[] = {
2550 	SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
2551 };
2552 static const unsigned int scifa6_clk_pins[] = {
2553 	/* SCK */
2554 	24,
2555 };
2556 static const unsigned int scifa6_clk_mux[] = {
2557 	SCIFA6_SCK_MARK,
2558 };
2559 /* - SCIFA7 ----------------------------------------------------------------- */
2560 static const unsigned int scifa7_data_pins[] = {
2561 	/* RXD, TXD */
2562 	0, 1,
2563 };
2564 static const unsigned int scifa7_data_mux[] = {
2565 	SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2566 };
2567 /* - SCIFB ------------------------------------------------------------------ */
2568 static const unsigned int scifb_data_0_pins[] = {
2569 	/* RXD, TXD */
2570 	191, 192,
2571 };
2572 static const unsigned int scifb_data_0_mux[] = {
2573 	SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
2574 };
2575 static const unsigned int scifb_clk_0_pins[] = {
2576 	/* SCK */
2577 	190,
2578 };
2579 static const unsigned int scifb_clk_0_mux[] = {
2580 	SCIFB_SCK_PORT190_MARK,
2581 };
2582 static const unsigned int scifb_ctrl_0_pins[] = {
2583 	/* RTS, CTS */
2584 	186, 187,
2585 };
2586 static const unsigned int scifb_ctrl_0_mux[] = {
2587 	SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
2588 };
2589 static const unsigned int scifb_data_1_pins[] = {
2590 	/* RXD, TXD */
2591 	3, 4,
2592 };
2593 static const unsigned int scifb_data_1_mux[] = {
2594 	SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
2595 };
2596 static const unsigned int scifb_clk_1_pins[] = {
2597 	/* SCK */
2598 	2,
2599 };
2600 static const unsigned int scifb_clk_1_mux[] = {
2601 	SCIFB_SCK_PORT2_MARK,
2602 };
2603 static const unsigned int scifb_ctrl_1_pins[] = {
2604 	/* RTS, CTS */
2605 	172, 173,
2606 };
2607 static const unsigned int scifb_ctrl_1_mux[] = {
2608 	SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
2609 };
2610 /* - SDHI0 ------------------------------------------------------------------ */
2611 static const unsigned int sdhi0_data1_pins[] = {
2612 	/* D0 */
2613 	77,
2614 };
2615 static const unsigned int sdhi0_data1_mux[] = {
2616 	SDHI0_D0_MARK,
2617 };
2618 static const unsigned int sdhi0_data4_pins[] = {
2619 	/* D[0:3] */
2620 	77, 78, 79, 80,
2621 };
2622 static const unsigned int sdhi0_data4_mux[] = {
2623 	SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
2624 };
2625 static const unsigned int sdhi0_ctrl_pins[] = {
2626 	/* CMD, CLK */
2627 	76, 82,
2628 };
2629 static const unsigned int sdhi0_ctrl_mux[] = {
2630 	SDHI0_CMD_MARK, SDHI0_CLK_MARK,
2631 };
2632 static const unsigned int sdhi0_cd_pins[] = {
2633 	/* CD */
2634 	81,
2635 };
2636 static const unsigned int sdhi0_cd_mux[] = {
2637 	SDHI0_CD_MARK,
2638 };
2639 static const unsigned int sdhi0_wp_pins[] = {
2640 	/* WP */
2641 	83,
2642 };
2643 static const unsigned int sdhi0_wp_mux[] = {
2644 	SDHI0_WP_MARK,
2645 };
2646 /* - SDHI1 ------------------------------------------------------------------ */
2647 static const unsigned int sdhi1_data1_pins[] = {
2648 	/* D0 */
2649 	68,
2650 };
2651 static const unsigned int sdhi1_data1_mux[] = {
2652 	SDHI1_D0_MARK,
2653 };
2654 static const unsigned int sdhi1_data4_pins[] = {
2655 	/* D[0:3] */
2656 	68, 69, 70, 71,
2657 };
2658 static const unsigned int sdhi1_data4_mux[] = {
2659 	SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
2660 };
2661 static const unsigned int sdhi1_ctrl_pins[] = {
2662 	/* CMD, CLK */
2663 	67, 66,
2664 };
2665 static const unsigned int sdhi1_ctrl_mux[] = {
2666 	SDHI1_CMD_MARK, SDHI1_CLK_MARK,
2667 };
2668 static const unsigned int sdhi1_cd_pins[] = {
2669 	/* CD */
2670 	72,
2671 };
2672 static const unsigned int sdhi1_cd_mux[] = {
2673 	SDHI1_CD_MARK,
2674 };
2675 static const unsigned int sdhi1_wp_pins[] = {
2676 	/* WP */
2677 	73,
2678 };
2679 static const unsigned int sdhi1_wp_mux[] = {
2680 	SDHI1_WP_MARK,
2681 };
2682 /* - SDHI2 ------------------------------------------------------------------ */
2683 static const unsigned int sdhi2_data1_pins[] = {
2684 	/* D0 */
2685 	205,
2686 };
2687 static const unsigned int sdhi2_data1_mux[] = {
2688 	SDHI2_D0_MARK,
2689 };
2690 static const unsigned int sdhi2_data4_pins[] = {
2691 	/* D[0:3] */
2692 	205, 206, 207, 208,
2693 };
2694 static const unsigned int sdhi2_data4_mux[] = {
2695 	SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
2696 };
2697 static const unsigned int sdhi2_ctrl_pins[] = {
2698 	/* CMD, CLK */
2699 	204, 203,
2700 };
2701 static const unsigned int sdhi2_ctrl_mux[] = {
2702 	SDHI2_CMD_MARK, SDHI2_CLK_MARK,
2703 };
2704 static const unsigned int sdhi2_cd_0_pins[] = {
2705 	/* CD */
2706 	202,
2707 };
2708 static const unsigned int sdhi2_cd_0_mux[] = {
2709 	SDHI2_CD_PORT202_MARK,
2710 };
2711 static const unsigned int sdhi2_wp_0_pins[] = {
2712 	/* WP */
2713 	177,
2714 };
2715 static const unsigned int sdhi2_wp_0_mux[] = {
2716 	SDHI2_WP_PORT177_MARK,
2717 };
2718 static const unsigned int sdhi2_cd_1_pins[] = {
2719 	/* CD */
2720 	24,
2721 };
2722 static const unsigned int sdhi2_cd_1_mux[] = {
2723 	SDHI2_CD_PORT24_MARK,
2724 };
2725 static const unsigned int sdhi2_wp_1_pins[] = {
2726 	/* WP */
2727 	25,
2728 };
2729 static const unsigned int sdhi2_wp_1_mux[] = {
2730 	SDHI2_WP_PORT25_MARK,
2731 };
2732 /* - TPU0 ------------------------------------------------------------------- */
2733 static const unsigned int tpu0_to0_pins[] = {
2734 	/* TO */
2735 	23,
2736 };
2737 static const unsigned int tpu0_to0_mux[] = {
2738 	TPU0TO0_MARK,
2739 };
2740 static const unsigned int tpu0_to1_pins[] = {
2741 	/* TO */
2742 	21,
2743 };
2744 static const unsigned int tpu0_to1_mux[] = {
2745 	TPU0TO1_MARK,
2746 };
2747 static const unsigned int tpu0_to2_0_pins[] = {
2748 	/* TO */
2749 	66,
2750 };
2751 static const unsigned int tpu0_to2_0_mux[] = {
2752 	TPU0TO2_PORT66_MARK,
2753 };
2754 static const unsigned int tpu0_to2_1_pins[] = {
2755 	/* TO */
2756 	202,
2757 };
2758 static const unsigned int tpu0_to2_1_mux[] = {
2759 	TPU0TO2_PORT202_MARK,
2760 };
2761 static const unsigned int tpu0_to3_pins[] = {
2762 	/* TO */
2763 	180,
2764 };
2765 static const unsigned int tpu0_to3_mux[] = {
2766 	TPU0TO3_MARK,
2767 };
2768 
2769 static const struct sh_pfc_pin_group pinmux_groups[] = {
2770 	SH_PFC_PIN_GROUP(bsc_data8),
2771 	SH_PFC_PIN_GROUP(bsc_data16),
2772 	SH_PFC_PIN_GROUP(bsc_data32),
2773 	SH_PFC_PIN_GROUP(bsc_cs0),
2774 	SH_PFC_PIN_GROUP(bsc_cs2),
2775 	SH_PFC_PIN_GROUP(bsc_cs4),
2776 	SH_PFC_PIN_GROUP(bsc_cs5a_0),
2777 	SH_PFC_PIN_GROUP(bsc_cs5a_1),
2778 	SH_PFC_PIN_GROUP(bsc_cs5b),
2779 	SH_PFC_PIN_GROUP(bsc_cs6a),
2780 	SH_PFC_PIN_GROUP(bsc_rd_we8),
2781 	SH_PFC_PIN_GROUP(bsc_rd_we16),
2782 	SH_PFC_PIN_GROUP(bsc_rd_we32),
2783 	SH_PFC_PIN_GROUP(bsc_bs),
2784 	SH_PFC_PIN_GROUP(bsc_rdwr),
2785 	SH_PFC_PIN_GROUP(ceu0_data_0_7),
2786 	SH_PFC_PIN_GROUP(ceu0_data_8_15_0),
2787 	SH_PFC_PIN_GROUP(ceu0_data_8_15_1),
2788 	SH_PFC_PIN_GROUP(ceu0_clk_0),
2789 	SH_PFC_PIN_GROUP(ceu0_clk_1),
2790 	SH_PFC_PIN_GROUP(ceu0_clk_2),
2791 	SH_PFC_PIN_GROUP(ceu0_sync),
2792 	SH_PFC_PIN_GROUP(ceu0_field),
2793 	SH_PFC_PIN_GROUP(ceu1_data),
2794 	SH_PFC_PIN_GROUP(ceu1_clk),
2795 	SH_PFC_PIN_GROUP(ceu1_sync),
2796 	SH_PFC_PIN_GROUP(ceu1_field),
2797 	SH_PFC_PIN_GROUP(fsia_mclk_in),
2798 	SH_PFC_PIN_GROUP(fsia_mclk_out),
2799 	SH_PFC_PIN_GROUP(fsia_sclk_in),
2800 	SH_PFC_PIN_GROUP(fsia_sclk_out),
2801 	SH_PFC_PIN_GROUP(fsia_data_in_0),
2802 	SH_PFC_PIN_GROUP(fsia_data_in_1),
2803 	SH_PFC_PIN_GROUP(fsia_data_out_0),
2804 	SH_PFC_PIN_GROUP(fsia_data_out_1),
2805 	SH_PFC_PIN_GROUP(fsia_data_out_2),
2806 	SH_PFC_PIN_GROUP(fsia_spdif_0),
2807 	SH_PFC_PIN_GROUP(fsia_spdif_1),
2808 	SH_PFC_PIN_GROUP(fsib_mclk_in),
2809 	SH_PFC_PIN_GROUP(gether_rmii),
2810 	SH_PFC_PIN_GROUP(gether_mii),
2811 	SH_PFC_PIN_GROUP(gether_gmii),
2812 	SH_PFC_PIN_GROUP(gether_int),
2813 	SH_PFC_PIN_GROUP(gether_link),
2814 	SH_PFC_PIN_GROUP(gether_wol),
2815 	SH_PFC_PIN_GROUP(hdmi),
2816 	SH_PFC_PIN_GROUP(intc_irq0_0),
2817 	SH_PFC_PIN_GROUP(intc_irq0_1),
2818 	SH_PFC_PIN_GROUP(intc_irq1),
2819 	SH_PFC_PIN_GROUP(intc_irq2_0),
2820 	SH_PFC_PIN_GROUP(intc_irq2_1),
2821 	SH_PFC_PIN_GROUP(intc_irq3_0),
2822 	SH_PFC_PIN_GROUP(intc_irq3_1),
2823 	SH_PFC_PIN_GROUP(intc_irq4_0),
2824 	SH_PFC_PIN_GROUP(intc_irq4_1),
2825 	SH_PFC_PIN_GROUP(intc_irq5_0),
2826 	SH_PFC_PIN_GROUP(intc_irq5_1),
2827 	SH_PFC_PIN_GROUP(intc_irq6_0),
2828 	SH_PFC_PIN_GROUP(intc_irq6_1),
2829 	SH_PFC_PIN_GROUP(intc_irq7_0),
2830 	SH_PFC_PIN_GROUP(intc_irq7_1),
2831 	SH_PFC_PIN_GROUP(intc_irq8),
2832 	SH_PFC_PIN_GROUP(intc_irq9_0),
2833 	SH_PFC_PIN_GROUP(intc_irq9_1),
2834 	SH_PFC_PIN_GROUP(intc_irq10),
2835 	SH_PFC_PIN_GROUP(intc_irq11),
2836 	SH_PFC_PIN_GROUP(intc_irq12_0),
2837 	SH_PFC_PIN_GROUP(intc_irq12_1),
2838 	SH_PFC_PIN_GROUP(intc_irq13_0),
2839 	SH_PFC_PIN_GROUP(intc_irq13_1),
2840 	SH_PFC_PIN_GROUP(intc_irq14_0),
2841 	SH_PFC_PIN_GROUP(intc_irq14_1),
2842 	SH_PFC_PIN_GROUP(intc_irq15_0),
2843 	SH_PFC_PIN_GROUP(intc_irq15_1),
2844 	SH_PFC_PIN_GROUP(intc_irq16_0),
2845 	SH_PFC_PIN_GROUP(intc_irq16_1),
2846 	SH_PFC_PIN_GROUP(intc_irq17),
2847 	SH_PFC_PIN_GROUP(intc_irq18),
2848 	SH_PFC_PIN_GROUP(intc_irq19),
2849 	SH_PFC_PIN_GROUP(intc_irq20),
2850 	SH_PFC_PIN_GROUP(intc_irq21),
2851 	SH_PFC_PIN_GROUP(intc_irq22),
2852 	SH_PFC_PIN_GROUP(intc_irq23),
2853 	SH_PFC_PIN_GROUP(intc_irq24),
2854 	SH_PFC_PIN_GROUP(intc_irq25),
2855 	SH_PFC_PIN_GROUP(intc_irq26_0),
2856 	SH_PFC_PIN_GROUP(intc_irq26_1),
2857 	SH_PFC_PIN_GROUP(intc_irq27_0),
2858 	SH_PFC_PIN_GROUP(intc_irq27_1),
2859 	SH_PFC_PIN_GROUP(intc_irq28_0),
2860 	SH_PFC_PIN_GROUP(intc_irq28_1),
2861 	SH_PFC_PIN_GROUP(intc_irq29_0),
2862 	SH_PFC_PIN_GROUP(intc_irq29_1),
2863 	SH_PFC_PIN_GROUP(intc_irq30_0),
2864 	SH_PFC_PIN_GROUP(intc_irq30_1),
2865 	SH_PFC_PIN_GROUP(intc_irq31_0),
2866 	SH_PFC_PIN_GROUP(intc_irq31_1),
2867 	SH_PFC_PIN_GROUP(lcd0_data8),
2868 	SH_PFC_PIN_GROUP(lcd0_data9),
2869 	SH_PFC_PIN_GROUP(lcd0_data12),
2870 	SH_PFC_PIN_GROUP(lcd0_data16),
2871 	SH_PFC_PIN_GROUP(lcd0_data18),
2872 	SH_PFC_PIN_GROUP(lcd0_data24_0),
2873 	SH_PFC_PIN_GROUP(lcd0_data24_1),
2874 	SH_PFC_PIN_GROUP(lcd0_display),
2875 	SH_PFC_PIN_GROUP(lcd0_lclk_0),
2876 	SH_PFC_PIN_GROUP(lcd0_lclk_1),
2877 	SH_PFC_PIN_GROUP(lcd0_sync),
2878 	SH_PFC_PIN_GROUP(lcd0_sys),
2879 	SH_PFC_PIN_GROUP(lcd1_data8),
2880 	SH_PFC_PIN_GROUP(lcd1_data9),
2881 	SH_PFC_PIN_GROUP(lcd1_data12),
2882 	SH_PFC_PIN_GROUP(lcd1_data16),
2883 	SH_PFC_PIN_GROUP(lcd1_data18),
2884 	SH_PFC_PIN_GROUP(lcd1_data24),
2885 	SH_PFC_PIN_GROUP(lcd1_display),
2886 	SH_PFC_PIN_GROUP(lcd1_lclk),
2887 	SH_PFC_PIN_GROUP(lcd1_sync),
2888 	SH_PFC_PIN_GROUP(lcd1_sys),
2889 	SH_PFC_PIN_GROUP(mmc0_data1_0),
2890 	SH_PFC_PIN_GROUP(mmc0_data4_0),
2891 	SH_PFC_PIN_GROUP(mmc0_data8_0),
2892 	SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2893 	SH_PFC_PIN_GROUP(mmc0_data1_1),
2894 	SH_PFC_PIN_GROUP(mmc0_data4_1),
2895 	SH_PFC_PIN_GROUP(mmc0_data8_1),
2896 	SH_PFC_PIN_GROUP(mmc0_ctrl_1),
2897 	SH_PFC_PIN_GROUP(scifa0_data),
2898 	SH_PFC_PIN_GROUP(scifa0_clk),
2899 	SH_PFC_PIN_GROUP(scifa0_ctrl),
2900 	SH_PFC_PIN_GROUP(scifa1_data),
2901 	SH_PFC_PIN_GROUP(scifa1_clk),
2902 	SH_PFC_PIN_GROUP(scifa1_ctrl),
2903 	SH_PFC_PIN_GROUP(scifa2_data),
2904 	SH_PFC_PIN_GROUP(scifa2_clk_0),
2905 	SH_PFC_PIN_GROUP(scifa2_clk_1),
2906 	SH_PFC_PIN_GROUP(scifa2_ctrl),
2907 	SH_PFC_PIN_GROUP(scifa3_data_0),
2908 	SH_PFC_PIN_GROUP(scifa3_clk_0),
2909 	SH_PFC_PIN_GROUP(scifa3_ctrl_0),
2910 	SH_PFC_PIN_GROUP(scifa3_data_1),
2911 	SH_PFC_PIN_GROUP(scifa3_clk_1),
2912 	SH_PFC_PIN_GROUP(scifa3_ctrl_1),
2913 	SH_PFC_PIN_GROUP(scifa4_data_0),
2914 	SH_PFC_PIN_GROUP(scifa4_data_1),
2915 	SH_PFC_PIN_GROUP(scifa4_data_2),
2916 	SH_PFC_PIN_GROUP(scifa4_clk_0),
2917 	SH_PFC_PIN_GROUP(scifa4_clk_1),
2918 	SH_PFC_PIN_GROUP(scifa5_data_0),
2919 	SH_PFC_PIN_GROUP(scifa5_data_1),
2920 	SH_PFC_PIN_GROUP(scifa5_data_2),
2921 	SH_PFC_PIN_GROUP(scifa5_clk_0),
2922 	SH_PFC_PIN_GROUP(scifa5_clk_1),
2923 	SH_PFC_PIN_GROUP(scifa6_data),
2924 	SH_PFC_PIN_GROUP(scifa6_clk),
2925 	SH_PFC_PIN_GROUP(scifa7_data),
2926 	SH_PFC_PIN_GROUP(scifb_data_0),
2927 	SH_PFC_PIN_GROUP(scifb_clk_0),
2928 	SH_PFC_PIN_GROUP(scifb_ctrl_0),
2929 	SH_PFC_PIN_GROUP(scifb_data_1),
2930 	SH_PFC_PIN_GROUP(scifb_clk_1),
2931 	SH_PFC_PIN_GROUP(scifb_ctrl_1),
2932 	SH_PFC_PIN_GROUP(sdhi0_data1),
2933 	SH_PFC_PIN_GROUP(sdhi0_data4),
2934 	SH_PFC_PIN_GROUP(sdhi0_ctrl),
2935 	SH_PFC_PIN_GROUP(sdhi0_cd),
2936 	SH_PFC_PIN_GROUP(sdhi0_wp),
2937 	SH_PFC_PIN_GROUP(sdhi1_data1),
2938 	SH_PFC_PIN_GROUP(sdhi1_data4),
2939 	SH_PFC_PIN_GROUP(sdhi1_ctrl),
2940 	SH_PFC_PIN_GROUP(sdhi1_cd),
2941 	SH_PFC_PIN_GROUP(sdhi1_wp),
2942 	SH_PFC_PIN_GROUP(sdhi2_data1),
2943 	SH_PFC_PIN_GROUP(sdhi2_data4),
2944 	SH_PFC_PIN_GROUP(sdhi2_ctrl),
2945 	SH_PFC_PIN_GROUP(sdhi2_cd_0),
2946 	SH_PFC_PIN_GROUP(sdhi2_wp_0),
2947 	SH_PFC_PIN_GROUP(sdhi2_cd_1),
2948 	SH_PFC_PIN_GROUP(sdhi2_wp_1),
2949 	SH_PFC_PIN_GROUP(tpu0_to0),
2950 	SH_PFC_PIN_GROUP(tpu0_to1),
2951 	SH_PFC_PIN_GROUP(tpu0_to2_0),
2952 	SH_PFC_PIN_GROUP(tpu0_to2_1),
2953 	SH_PFC_PIN_GROUP(tpu0_to3),
2954 };
2955 
2956 static const char * const bsc_groups[] = {
2957 	"bsc_data8",
2958 	"bsc_data16",
2959 	"bsc_data32",
2960 	"bsc_cs0",
2961 	"bsc_cs2",
2962 	"bsc_cs4",
2963 	"bsc_cs5a_0",
2964 	"bsc_cs5a_1",
2965 	"bsc_cs5b",
2966 	"bsc_cs6a",
2967 	"bsc_rd_we8",
2968 	"bsc_rd_we16",
2969 	"bsc_rd_we32",
2970 	"bsc_bs",
2971 	"bsc_rdwr",
2972 };
2973 
2974 static const char * const ceu0_groups[] = {
2975 	"ceu0_data_0_7",
2976 	"ceu0_data_8_15_0",
2977 	"ceu0_data_8_15_1",
2978 	"ceu0_clk_0",
2979 	"ceu0_clk_1",
2980 	"ceu0_clk_2",
2981 	"ceu0_sync",
2982 	"ceu0_field",
2983 };
2984 
2985 static const char * const ceu1_groups[] = {
2986 	"ceu1_data",
2987 	"ceu1_clk",
2988 	"ceu1_sync",
2989 	"ceu1_field",
2990 };
2991 
2992 static const char * const fsia_groups[] = {
2993 	"fsia_mclk_in",
2994 	"fsia_mclk_out",
2995 	"fsia_sclk_in",
2996 	"fsia_sclk_out",
2997 	"fsia_data_in_0",
2998 	"fsia_data_in_1",
2999 	"fsia_data_out_0",
3000 	"fsia_data_out_1",
3001 	"fsia_data_out_2",
3002 	"fsia_spdif_0",
3003 	"fsia_spdif_1",
3004 };
3005 
3006 static const char * const fsib_groups[] = {
3007 	"fsib_mclk_in",
3008 };
3009 
3010 static const char * const gether_groups[] = {
3011 	"gether_rmii",
3012 	"gether_mii",
3013 	"gether_gmii",
3014 	"gether_int",
3015 	"gether_link",
3016 	"gether_wol",
3017 };
3018 
3019 static const char * const hdmi_groups[] = {
3020 	"hdmi",
3021 };
3022 
3023 static const char * const intc_groups[] = {
3024 	"intc_irq0_0",
3025 	"intc_irq0_1",
3026 	"intc_irq1",
3027 	"intc_irq2_0",
3028 	"intc_irq2_1",
3029 	"intc_irq3_0",
3030 	"intc_irq3_1",
3031 	"intc_irq4_0",
3032 	"intc_irq4_1",
3033 	"intc_irq5_0",
3034 	"intc_irq5_1",
3035 	"intc_irq6_0",
3036 	"intc_irq6_1",
3037 	"intc_irq7_0",
3038 	"intc_irq7_1",
3039 	"intc_irq8",
3040 	"intc_irq9_0",
3041 	"intc_irq9_1",
3042 	"intc_irq10",
3043 	"intc_irq11",
3044 	"intc_irq12_0",
3045 	"intc_irq12_1",
3046 	"intc_irq13_0",
3047 	"intc_irq13_1",
3048 	"intc_irq14_0",
3049 	"intc_irq14_1",
3050 	"intc_irq15_0",
3051 	"intc_irq15_1",
3052 	"intc_irq16_0",
3053 	"intc_irq16_1",
3054 	"intc_irq17",
3055 	"intc_irq18",
3056 	"intc_irq19",
3057 	"intc_irq20",
3058 	"intc_irq21",
3059 	"intc_irq22",
3060 	"intc_irq23",
3061 	"intc_irq24",
3062 	"intc_irq25",
3063 	"intc_irq26_0",
3064 	"intc_irq26_1",
3065 	"intc_irq27_0",
3066 	"intc_irq27_1",
3067 	"intc_irq28_0",
3068 	"intc_irq28_1",
3069 	"intc_irq29_0",
3070 	"intc_irq29_1",
3071 	"intc_irq30_0",
3072 	"intc_irq30_1",
3073 	"intc_irq31_0",
3074 	"intc_irq31_1",
3075 };
3076 
3077 static const char * const lcd0_groups[] = {
3078 	"lcd0_data8",
3079 	"lcd0_data9",
3080 	"lcd0_data12",
3081 	"lcd0_data16",
3082 	"lcd0_data18",
3083 	"lcd0_data24_0",
3084 	"lcd0_data24_1",
3085 	"lcd0_display",
3086 	"lcd0_lclk_0",
3087 	"lcd0_lclk_1",
3088 	"lcd0_sync",
3089 	"lcd0_sys",
3090 };
3091 
3092 static const char * const lcd1_groups[] = {
3093 	"lcd1_data8",
3094 	"lcd1_data9",
3095 	"lcd1_data12",
3096 	"lcd1_data16",
3097 	"lcd1_data18",
3098 	"lcd1_data24",
3099 	"lcd1_display",
3100 	"lcd1_lclk",
3101 	"lcd1_sync",
3102 	"lcd1_sys",
3103 };
3104 
3105 static const char * const mmc0_groups[] = {
3106 	"mmc0_data1_0",
3107 	"mmc0_data4_0",
3108 	"mmc0_data8_0",
3109 	"mmc0_ctrl_0",
3110 	"mmc0_data1_1",
3111 	"mmc0_data4_1",
3112 	"mmc0_data8_1",
3113 	"mmc0_ctrl_1",
3114 };
3115 
3116 static const char * const scifa0_groups[] = {
3117 	"scifa0_data",
3118 	"scifa0_clk",
3119 	"scifa0_ctrl",
3120 };
3121 
3122 static const char * const scifa1_groups[] = {
3123 	"scifa1_data",
3124 	"scifa1_clk",
3125 	"scifa1_ctrl",
3126 };
3127 
3128 static const char * const scifa2_groups[] = {
3129 	"scifa2_data",
3130 	"scifa2_clk_0",
3131 	"scifa2_clk_1",
3132 	"scifa2_ctrl",
3133 };
3134 
3135 static const char * const scifa3_groups[] = {
3136 	"scifa3_data_0",
3137 	"scifa3_clk_0",
3138 	"scifa3_ctrl_0",
3139 	"scifa3_data_1",
3140 	"scifa3_clk_1",
3141 	"scifa3_ctrl_1",
3142 };
3143 
3144 static const char * const scifa4_groups[] = {
3145 	"scifa4_data_0",
3146 	"scifa4_data_1",
3147 	"scifa4_data_2",
3148 	"scifa4_clk_0",
3149 	"scifa4_clk_1",
3150 };
3151 
3152 static const char * const scifa5_groups[] = {
3153 	"scifa5_data_0",
3154 	"scifa5_data_1",
3155 	"scifa5_data_2",
3156 	"scifa5_clk_0",
3157 	"scifa5_clk_1",
3158 };
3159 
3160 static const char * const scifa6_groups[] = {
3161 	"scifa6_data",
3162 	"scifa6_clk",
3163 };
3164 
3165 static const char * const scifa7_groups[] = {
3166 	"scifa7_data",
3167 };
3168 
3169 static const char * const scifb_groups[] = {
3170 	"scifb_data_0",
3171 	"scifb_clk_0",
3172 	"scifb_ctrl_0",
3173 	"scifb_data_1",
3174 	"scifb_clk_1",
3175 	"scifb_ctrl_1",
3176 };
3177 
3178 static const char * const sdhi0_groups[] = {
3179 	"sdhi0_data1",
3180 	"sdhi0_data4",
3181 	"sdhi0_ctrl",
3182 	"sdhi0_cd",
3183 	"sdhi0_wp",
3184 };
3185 
3186 static const char * const sdhi1_groups[] = {
3187 	"sdhi1_data1",
3188 	"sdhi1_data4",
3189 	"sdhi1_ctrl",
3190 	"sdhi1_cd",
3191 	"sdhi1_wp",
3192 };
3193 
3194 static const char * const sdhi2_groups[] = {
3195 	"sdhi2_data1",
3196 	"sdhi2_data4",
3197 	"sdhi2_ctrl",
3198 	"sdhi2_cd_0",
3199 	"sdhi2_wp_0",
3200 	"sdhi2_cd_1",
3201 	"sdhi2_wp_1",
3202 };
3203 
3204 static const char * const tpu0_groups[] = {
3205 	"tpu0_to0",
3206 	"tpu0_to1",
3207 	"tpu0_to2_0",
3208 	"tpu0_to2_1",
3209 	"tpu0_to3",
3210 };
3211 
3212 static const struct sh_pfc_function pinmux_functions[] = {
3213 	SH_PFC_FUNCTION(bsc),
3214 	SH_PFC_FUNCTION(ceu0),
3215 	SH_PFC_FUNCTION(ceu1),
3216 	SH_PFC_FUNCTION(fsia),
3217 	SH_PFC_FUNCTION(fsib),
3218 	SH_PFC_FUNCTION(gether),
3219 	SH_PFC_FUNCTION(hdmi),
3220 	SH_PFC_FUNCTION(intc),
3221 	SH_PFC_FUNCTION(lcd0),
3222 	SH_PFC_FUNCTION(lcd1),
3223 	SH_PFC_FUNCTION(mmc0),
3224 	SH_PFC_FUNCTION(scifa0),
3225 	SH_PFC_FUNCTION(scifa1),
3226 	SH_PFC_FUNCTION(scifa2),
3227 	SH_PFC_FUNCTION(scifa3),
3228 	SH_PFC_FUNCTION(scifa4),
3229 	SH_PFC_FUNCTION(scifa5),
3230 	SH_PFC_FUNCTION(scifa6),
3231 	SH_PFC_FUNCTION(scifa7),
3232 	SH_PFC_FUNCTION(scifb),
3233 	SH_PFC_FUNCTION(sdhi0),
3234 	SH_PFC_FUNCTION(sdhi1),
3235 	SH_PFC_FUNCTION(sdhi2),
3236 	SH_PFC_FUNCTION(tpu0),
3237 };
3238 
3239 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3240 	PORTCR(0,	0xe6050000), /* PORT0CR */
3241 	PORTCR(1,	0xe6050001), /* PORT1CR */
3242 	PORTCR(2,	0xe6050002), /* PORT2CR */
3243 	PORTCR(3,	0xe6050003), /* PORT3CR */
3244 	PORTCR(4,	0xe6050004), /* PORT4CR */
3245 	PORTCR(5,	0xe6050005), /* PORT5CR */
3246 	PORTCR(6,	0xe6050006), /* PORT6CR */
3247 	PORTCR(7,	0xe6050007), /* PORT7CR */
3248 	PORTCR(8,	0xe6050008), /* PORT8CR */
3249 	PORTCR(9,	0xe6050009), /* PORT9CR */
3250 	PORTCR(10,	0xe605000a), /* PORT10CR */
3251 	PORTCR(11,	0xe605000b), /* PORT11CR */
3252 	PORTCR(12,	0xe605000c), /* PORT12CR */
3253 	PORTCR(13,	0xe605000d), /* PORT13CR */
3254 	PORTCR(14,	0xe605000e), /* PORT14CR */
3255 	PORTCR(15,	0xe605000f), /* PORT15CR */
3256 	PORTCR(16,	0xe6050010), /* PORT16CR */
3257 	PORTCR(17,	0xe6050011), /* PORT17CR */
3258 	PORTCR(18,	0xe6050012), /* PORT18CR */
3259 	PORTCR(19,	0xe6050013), /* PORT19CR */
3260 	PORTCR(20,	0xe6050014), /* PORT20CR */
3261 	PORTCR(21,	0xe6050015), /* PORT21CR */
3262 	PORTCR(22,	0xe6050016), /* PORT22CR */
3263 	PORTCR(23,	0xe6050017), /* PORT23CR */
3264 	PORTCR(24,	0xe6050018), /* PORT24CR */
3265 	PORTCR(25,	0xe6050019), /* PORT25CR */
3266 	PORTCR(26,	0xe605001a), /* PORT26CR */
3267 	PORTCR(27,	0xe605001b), /* PORT27CR */
3268 	PORTCR(28,	0xe605001c), /* PORT28CR */
3269 	PORTCR(29,	0xe605001d), /* PORT29CR */
3270 	PORTCR(30,	0xe605001e), /* PORT30CR */
3271 	PORTCR(31,	0xe605001f), /* PORT31CR */
3272 	PORTCR(32,	0xe6050020), /* PORT32CR */
3273 	PORTCR(33,	0xe6050021), /* PORT33CR */
3274 	PORTCR(34,	0xe6050022), /* PORT34CR */
3275 	PORTCR(35,	0xe6050023), /* PORT35CR */
3276 	PORTCR(36,	0xe6050024), /* PORT36CR */
3277 	PORTCR(37,	0xe6050025), /* PORT37CR */
3278 	PORTCR(38,	0xe6050026), /* PORT38CR */
3279 	PORTCR(39,	0xe6050027), /* PORT39CR */
3280 	PORTCR(40,	0xe6050028), /* PORT40CR */
3281 	PORTCR(41,	0xe6050029), /* PORT41CR */
3282 	PORTCR(42,	0xe605002a), /* PORT42CR */
3283 	PORTCR(43,	0xe605002b), /* PORT43CR */
3284 	PORTCR(44,	0xe605002c), /* PORT44CR */
3285 	PORTCR(45,	0xe605002d), /* PORT45CR */
3286 	PORTCR(46,	0xe605002e), /* PORT46CR */
3287 	PORTCR(47,	0xe605002f), /* PORT47CR */
3288 	PORTCR(48,	0xe6050030), /* PORT48CR */
3289 	PORTCR(49,	0xe6050031), /* PORT49CR */
3290 	PORTCR(50,	0xe6050032), /* PORT50CR */
3291 	PORTCR(51,	0xe6050033), /* PORT51CR */
3292 	PORTCR(52,	0xe6050034), /* PORT52CR */
3293 	PORTCR(53,	0xe6050035), /* PORT53CR */
3294 	PORTCR(54,	0xe6050036), /* PORT54CR */
3295 	PORTCR(55,	0xe6050037), /* PORT55CR */
3296 	PORTCR(56,	0xe6050038), /* PORT56CR */
3297 	PORTCR(57,	0xe6050039), /* PORT57CR */
3298 	PORTCR(58,	0xe605003a), /* PORT58CR */
3299 	PORTCR(59,	0xe605003b), /* PORT59CR */
3300 	PORTCR(60,	0xe605003c), /* PORT60CR */
3301 	PORTCR(61,	0xe605003d), /* PORT61CR */
3302 	PORTCR(62,	0xe605003e), /* PORT62CR */
3303 	PORTCR(63,	0xe605003f), /* PORT63CR */
3304 	PORTCR(64,	0xe6050040), /* PORT64CR */
3305 	PORTCR(65,	0xe6050041), /* PORT65CR */
3306 	PORTCR(66,	0xe6050042), /* PORT66CR */
3307 	PORTCR(67,	0xe6050043), /* PORT67CR */
3308 	PORTCR(68,	0xe6050044), /* PORT68CR */
3309 	PORTCR(69,	0xe6050045), /* PORT69CR */
3310 	PORTCR(70,	0xe6050046), /* PORT70CR */
3311 	PORTCR(71,	0xe6050047), /* PORT71CR */
3312 	PORTCR(72,	0xe6050048), /* PORT72CR */
3313 	PORTCR(73,	0xe6050049), /* PORT73CR */
3314 	PORTCR(74,	0xe605004a), /* PORT74CR */
3315 	PORTCR(75,	0xe605004b), /* PORT75CR */
3316 	PORTCR(76,	0xe605004c), /* PORT76CR */
3317 	PORTCR(77,	0xe605004d), /* PORT77CR */
3318 	PORTCR(78,	0xe605004e), /* PORT78CR */
3319 	PORTCR(79,	0xe605004f), /* PORT79CR */
3320 	PORTCR(80,	0xe6050050), /* PORT80CR */
3321 	PORTCR(81,	0xe6050051), /* PORT81CR */
3322 	PORTCR(82,	0xe6050052), /* PORT82CR */
3323 	PORTCR(83,	0xe6050053), /* PORT83CR */
3324 
3325 	PORTCR(84,	0xe6051054), /* PORT84CR */
3326 	PORTCR(85,	0xe6051055), /* PORT85CR */
3327 	PORTCR(86,	0xe6051056), /* PORT86CR */
3328 	PORTCR(87,	0xe6051057), /* PORT87CR */
3329 	PORTCR(88,	0xe6051058), /* PORT88CR */
3330 	PORTCR(89,	0xe6051059), /* PORT89CR */
3331 	PORTCR(90,	0xe605105a), /* PORT90CR */
3332 	PORTCR(91,	0xe605105b), /* PORT91CR */
3333 	PORTCR(92,	0xe605105c), /* PORT92CR */
3334 	PORTCR(93,	0xe605105d), /* PORT93CR */
3335 	PORTCR(94,	0xe605105e), /* PORT94CR */
3336 	PORTCR(95,	0xe605105f), /* PORT95CR */
3337 	PORTCR(96,	0xe6051060), /* PORT96CR */
3338 	PORTCR(97,	0xe6051061), /* PORT97CR */
3339 	PORTCR(98,	0xe6051062), /* PORT98CR */
3340 	PORTCR(99,	0xe6051063), /* PORT99CR */
3341 	PORTCR(100,	0xe6051064), /* PORT100CR */
3342 	PORTCR(101,	0xe6051065), /* PORT101CR */
3343 	PORTCR(102,	0xe6051066), /* PORT102CR */
3344 	PORTCR(103,	0xe6051067), /* PORT103CR */
3345 	PORTCR(104,	0xe6051068), /* PORT104CR */
3346 	PORTCR(105,	0xe6051069), /* PORT105CR */
3347 	PORTCR(106,	0xe605106a), /* PORT106CR */
3348 	PORTCR(107,	0xe605106b), /* PORT107CR */
3349 	PORTCR(108,	0xe605106c), /* PORT108CR */
3350 	PORTCR(109,	0xe605106d), /* PORT109CR */
3351 	PORTCR(110,	0xe605106e), /* PORT110CR */
3352 	PORTCR(111,	0xe605106f), /* PORT111CR */
3353 	PORTCR(112,	0xe6051070), /* PORT112CR */
3354 	PORTCR(113,	0xe6051071), /* PORT113CR */
3355 	PORTCR(114,	0xe6051072), /* PORT114CR */
3356 
3357 	PORTCR(115,	0xe6052073), /* PORT115CR */
3358 	PORTCR(116,	0xe6052074), /* PORT116CR */
3359 	PORTCR(117,	0xe6052075), /* PORT117CR */
3360 	PORTCR(118,	0xe6052076), /* PORT118CR */
3361 	PORTCR(119,	0xe6052077), /* PORT119CR */
3362 	PORTCR(120,	0xe6052078), /* PORT120CR */
3363 	PORTCR(121,	0xe6052079), /* PORT121CR */
3364 	PORTCR(122,	0xe605207a), /* PORT122CR */
3365 	PORTCR(123,	0xe605207b), /* PORT123CR */
3366 	PORTCR(124,	0xe605207c), /* PORT124CR */
3367 	PORTCR(125,	0xe605207d), /* PORT125CR */
3368 	PORTCR(126,	0xe605207e), /* PORT126CR */
3369 	PORTCR(127,	0xe605207f), /* PORT127CR */
3370 	PORTCR(128,	0xe6052080), /* PORT128CR */
3371 	PORTCR(129,	0xe6052081), /* PORT129CR */
3372 	PORTCR(130,	0xe6052082), /* PORT130CR */
3373 	PORTCR(131,	0xe6052083), /* PORT131CR */
3374 	PORTCR(132,	0xe6052084), /* PORT132CR */
3375 	PORTCR(133,	0xe6052085), /* PORT133CR */
3376 	PORTCR(134,	0xe6052086), /* PORT134CR */
3377 	PORTCR(135,	0xe6052087), /* PORT135CR */
3378 	PORTCR(136,	0xe6052088), /* PORT136CR */
3379 	PORTCR(137,	0xe6052089), /* PORT137CR */
3380 	PORTCR(138,	0xe605208a), /* PORT138CR */
3381 	PORTCR(139,	0xe605208b), /* PORT139CR */
3382 	PORTCR(140,	0xe605208c), /* PORT140CR */
3383 	PORTCR(141,	0xe605208d), /* PORT141CR */
3384 	PORTCR(142,	0xe605208e), /* PORT142CR */
3385 	PORTCR(143,	0xe605208f), /* PORT143CR */
3386 	PORTCR(144,	0xe6052090), /* PORT144CR */
3387 	PORTCR(145,	0xe6052091), /* PORT145CR */
3388 	PORTCR(146,	0xe6052092), /* PORT146CR */
3389 	PORTCR(147,	0xe6052093), /* PORT147CR */
3390 	PORTCR(148,	0xe6052094), /* PORT148CR */
3391 	PORTCR(149,	0xe6052095), /* PORT149CR */
3392 	PORTCR(150,	0xe6052096), /* PORT150CR */
3393 	PORTCR(151,	0xe6052097), /* PORT151CR */
3394 	PORTCR(152,	0xe6052098), /* PORT152CR */
3395 	PORTCR(153,	0xe6052099), /* PORT153CR */
3396 	PORTCR(154,	0xe605209a), /* PORT154CR */
3397 	PORTCR(155,	0xe605209b), /* PORT155CR */
3398 	PORTCR(156,	0xe605209c), /* PORT156CR */
3399 	PORTCR(157,	0xe605209d), /* PORT157CR */
3400 	PORTCR(158,	0xe605209e), /* PORT158CR */
3401 	PORTCR(159,	0xe605209f), /* PORT159CR */
3402 	PORTCR(160,	0xe60520a0), /* PORT160CR */
3403 	PORTCR(161,	0xe60520a1), /* PORT161CR */
3404 	PORTCR(162,	0xe60520a2), /* PORT162CR */
3405 	PORTCR(163,	0xe60520a3), /* PORT163CR */
3406 	PORTCR(164,	0xe60520a4), /* PORT164CR */
3407 	PORTCR(165,	0xe60520a5), /* PORT165CR */
3408 	PORTCR(166,	0xe60520a6), /* PORT166CR */
3409 	PORTCR(167,	0xe60520a7), /* PORT167CR */
3410 	PORTCR(168,	0xe60520a8), /* PORT168CR */
3411 	PORTCR(169,	0xe60520a9), /* PORT169CR */
3412 	PORTCR(170,	0xe60520aa), /* PORT170CR */
3413 	PORTCR(171,	0xe60520ab), /* PORT171CR */
3414 	PORTCR(172,	0xe60520ac), /* PORT172CR */
3415 	PORTCR(173,	0xe60520ad), /* PORT173CR */
3416 	PORTCR(174,	0xe60520ae), /* PORT174CR */
3417 	PORTCR(175,	0xe60520af), /* PORT175CR */
3418 	PORTCR(176,	0xe60520b0), /* PORT176CR */
3419 	PORTCR(177,	0xe60520b1), /* PORT177CR */
3420 	PORTCR(178,	0xe60520b2), /* PORT178CR */
3421 	PORTCR(179,	0xe60520b3), /* PORT179CR */
3422 	PORTCR(180,	0xe60520b4), /* PORT180CR */
3423 	PORTCR(181,	0xe60520b5), /* PORT181CR */
3424 	PORTCR(182,	0xe60520b6), /* PORT182CR */
3425 	PORTCR(183,	0xe60520b7), /* PORT183CR */
3426 	PORTCR(184,	0xe60520b8), /* PORT184CR */
3427 	PORTCR(185,	0xe60520b9), /* PORT185CR */
3428 	PORTCR(186,	0xe60520ba), /* PORT186CR */
3429 	PORTCR(187,	0xe60520bb), /* PORT187CR */
3430 	PORTCR(188,	0xe60520bc), /* PORT188CR */
3431 	PORTCR(189,	0xe60520bd), /* PORT189CR */
3432 	PORTCR(190,	0xe60520be), /* PORT190CR */
3433 	PORTCR(191,	0xe60520bf), /* PORT191CR */
3434 	PORTCR(192,	0xe60520c0), /* PORT192CR */
3435 	PORTCR(193,	0xe60520c1), /* PORT193CR */
3436 	PORTCR(194,	0xe60520c2), /* PORT194CR */
3437 	PORTCR(195,	0xe60520c3), /* PORT195CR */
3438 	PORTCR(196,	0xe60520c4), /* PORT196CR */
3439 	PORTCR(197,	0xe60520c5), /* PORT197CR */
3440 	PORTCR(198,	0xe60520c6), /* PORT198CR */
3441 	PORTCR(199,	0xe60520c7), /* PORT199CR */
3442 	PORTCR(200,	0xe60520c8), /* PORT200CR */
3443 	PORTCR(201,	0xe60520c9), /* PORT201CR */
3444 	PORTCR(202,	0xe60520ca), /* PORT202CR */
3445 	PORTCR(203,	0xe60520cb), /* PORT203CR */
3446 	PORTCR(204,	0xe60520cc), /* PORT204CR */
3447 	PORTCR(205,	0xe60520cd), /* PORT205CR */
3448 	PORTCR(206,	0xe60520ce), /* PORT206CR */
3449 	PORTCR(207,	0xe60520cf), /* PORT207CR */
3450 	PORTCR(208,	0xe60520d0), /* PORT208CR */
3451 	PORTCR(209,	0xe60520d1), /* PORT209CR */
3452 
3453 	PORTCR(210,	0xe60530d2), /* PORT210CR */
3454 	PORTCR(211,	0xe60530d3), /* PORT211CR */
3455 
3456 	{ PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
3457 			MSEL1CR_31_0,	MSEL1CR_31_1,
3458 			MSEL1CR_30_0,	MSEL1CR_30_1,
3459 			MSEL1CR_29_0,	MSEL1CR_29_1,
3460 			MSEL1CR_28_0,	MSEL1CR_28_1,
3461 			MSEL1CR_27_0,	MSEL1CR_27_1,
3462 			MSEL1CR_26_0,	MSEL1CR_26_1,
3463 			0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3464 			0, 0, 0, 0, 0, 0, 0, 0,
3465 			MSEL1CR_16_0,	MSEL1CR_16_1,
3466 			MSEL1CR_15_0,	MSEL1CR_15_1,
3467 			MSEL1CR_14_0,	MSEL1CR_14_1,
3468 			MSEL1CR_13_0,	MSEL1CR_13_1,
3469 			MSEL1CR_12_0,	MSEL1CR_12_1,
3470 			0, 0, 0, 0,
3471 			MSEL1CR_9_0,	MSEL1CR_9_1,
3472 			0, 0,
3473 			MSEL1CR_7_0,	MSEL1CR_7_1,
3474 			MSEL1CR_6_0,	MSEL1CR_6_1,
3475 			MSEL1CR_5_0,	MSEL1CR_5_1,
3476 			MSEL1CR_4_0,	MSEL1CR_4_1,
3477 			MSEL1CR_3_0,	MSEL1CR_3_1,
3478 			MSEL1CR_2_0,	MSEL1CR_2_1,
3479 			0, 0,
3480 			MSEL1CR_0_0,	MSEL1CR_0_1,
3481 		}
3482 	},
3483 	{ PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
3484 			0, 0, 0, 0, 0, 0, 0, 0,
3485 			0, 0, 0, 0, 0, 0, 0, 0,
3486 			0, 0, 0, 0, 0, 0, 0, 0,
3487 			0, 0, 0, 0, 0, 0, 0, 0,
3488 			MSEL3CR_15_0,	MSEL3CR_15_1,
3489 			0, 0, 0, 0, 0, 0, 0, 0,
3490 			0, 0, 0, 0, 0, 0, 0, 0,
3491 			MSEL3CR_6_0,	MSEL3CR_6_1,
3492 			0, 0, 0, 0, 0, 0, 0, 0,
3493 			0, 0, 0, 0,
3494 			}
3495 	},
3496 	{ PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
3497 			0, 0, 0, 0, 0, 0, 0, 0,
3498 			0, 0, 0, 0, 0, 0, 0, 0,
3499 			0, 0, 0, 0, 0, 0, 0, 0,
3500 			MSEL4CR_19_0,	MSEL4CR_19_1,
3501 			MSEL4CR_18_0,	MSEL4CR_18_1,
3502 			0, 0, 0, 0,
3503 			MSEL4CR_15_0,	MSEL4CR_15_1,
3504 			0, 0, 0, 0, 0, 0, 0, 0,
3505 			MSEL4CR_10_0,	MSEL4CR_10_1,
3506 			0, 0, 0, 0, 0, 0,
3507 			MSEL4CR_6_0,	MSEL4CR_6_1,
3508 			0, 0,
3509 			MSEL4CR_4_0,	MSEL4CR_4_1,
3510 			0, 0, 0, 0,
3511 			MSEL4CR_1_0,	MSEL4CR_1_1,
3512 			0, 0,
3513 		}
3514 	},
3515 	{ PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
3516 			MSEL5CR_31_0,	MSEL5CR_31_1,
3517 			MSEL5CR_30_0,	MSEL5CR_30_1,
3518 			MSEL5CR_29_0,	MSEL5CR_29_1,
3519 			0, 0,
3520 			MSEL5CR_27_0,	MSEL5CR_27_1,
3521 			0, 0,
3522 			MSEL5CR_25_0,	MSEL5CR_25_1,
3523 			0, 0,
3524 			MSEL5CR_23_0,	MSEL5CR_23_1,
3525 			0, 0,
3526 			MSEL5CR_21_0,	MSEL5CR_21_1,
3527 			0, 0,
3528 			MSEL5CR_19_0,	MSEL5CR_19_1,
3529 			0, 0,
3530 			MSEL5CR_17_0,	MSEL5CR_17_1,
3531 			0, 0,
3532 			MSEL5CR_15_0,	MSEL5CR_15_1,
3533 			MSEL5CR_14_0,	MSEL5CR_14_1,
3534 			MSEL5CR_13_0,	MSEL5CR_13_1,
3535 			MSEL5CR_12_0,	MSEL5CR_12_1,
3536 			MSEL5CR_11_0,	MSEL5CR_11_1,
3537 			MSEL5CR_10_0,	MSEL5CR_10_1,
3538 			0, 0,
3539 			MSEL5CR_8_0,	MSEL5CR_8_1,
3540 			MSEL5CR_7_0,	MSEL5CR_7_1,
3541 			MSEL5CR_6_0,	MSEL5CR_6_1,
3542 			MSEL5CR_5_0,	MSEL5CR_5_1,
3543 			MSEL5CR_4_0,	MSEL5CR_4_1,
3544 			MSEL5CR_3_0,	MSEL5CR_3_1,
3545 			MSEL5CR_2_0,	MSEL5CR_2_1,
3546 			0, 0,
3547 			MSEL5CR_0_0,	MSEL5CR_0_1,
3548 		}
3549 	},
3550 	{ },
3551 };
3552 
3553 static const struct pinmux_data_reg pinmux_data_regs[] = {
3554 	{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
3555 		PORT31_DATA,	PORT30_DATA,	PORT29_DATA,	PORT28_DATA,
3556 		PORT27_DATA,	PORT26_DATA,	PORT25_DATA,	PORT24_DATA,
3557 		PORT23_DATA,	PORT22_DATA,	PORT21_DATA,	PORT20_DATA,
3558 		PORT19_DATA,	PORT18_DATA,	PORT17_DATA,	PORT16_DATA,
3559 		PORT15_DATA,	PORT14_DATA,	PORT13_DATA,	PORT12_DATA,
3560 		PORT11_DATA,	PORT10_DATA,	PORT9_DATA,	PORT8_DATA,
3561 		PORT7_DATA,	PORT6_DATA,	PORT5_DATA,	PORT4_DATA,
3562 		PORT3_DATA,	PORT2_DATA,	PORT1_DATA,	PORT0_DATA }
3563 	},
3564 	{ PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
3565 		PORT63_DATA,	PORT62_DATA,	PORT61_DATA,	PORT60_DATA,
3566 		PORT59_DATA,	PORT58_DATA,	PORT57_DATA,	PORT56_DATA,
3567 		PORT55_DATA,	PORT54_DATA,	PORT53_DATA,	PORT52_DATA,
3568 		PORT51_DATA,	PORT50_DATA,	PORT49_DATA,	PORT48_DATA,
3569 		PORT47_DATA,	PORT46_DATA,	PORT45_DATA,	PORT44_DATA,
3570 		PORT43_DATA,	PORT42_DATA,	PORT41_DATA,	PORT40_DATA,
3571 		PORT39_DATA,	PORT38_DATA,	PORT37_DATA,	PORT36_DATA,
3572 		PORT35_DATA,	PORT34_DATA,	PORT33_DATA,	PORT32_DATA }
3573 	},
3574 	{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
3575 		0, 0, 0, 0,
3576 		0, 0, 0, 0,
3577 		0, 0, 0, 0,
3578 		PORT83_DATA,	PORT82_DATA,	PORT81_DATA,	PORT80_DATA,
3579 		PORT79_DATA,	PORT78_DATA,	PORT77_DATA,	PORT76_DATA,
3580 		PORT75_DATA,	PORT74_DATA,	PORT73_DATA,	PORT72_DATA,
3581 		PORT71_DATA,	PORT70_DATA,	PORT69_DATA,	PORT68_DATA,
3582 		PORT67_DATA,	PORT66_DATA,	PORT65_DATA,	PORT64_DATA }
3583 	},
3584 	{ PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
3585 		PORT95_DATA,	PORT94_DATA,	PORT93_DATA,	PORT92_DATA,
3586 		PORT91_DATA,	PORT90_DATA,	PORT89_DATA,	PORT88_DATA,
3587 		PORT87_DATA,	PORT86_DATA,	PORT85_DATA,	PORT84_DATA,
3588 		0, 0, 0, 0,
3589 		0, 0, 0, 0,
3590 		0, 0, 0, 0,
3591 		0, 0, 0, 0,
3592 		0, 0, 0, 0 }
3593 	},
3594 	{ PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
3595 		0, 0, 0, 0,
3596 		0, 0, 0, 0,
3597 		0, 0, 0, 0,
3598 		0,		PORT114_DATA,	PORT113_DATA,	PORT112_DATA,
3599 		PORT111_DATA,	PORT110_DATA,	PORT109_DATA,	PORT108_DATA,
3600 		PORT107_DATA,	PORT106_DATA,	PORT105_DATA,	PORT104_DATA,
3601 		PORT103_DATA,	PORT102_DATA,	PORT101_DATA,	PORT100_DATA,
3602 		PORT99_DATA,	PORT98_DATA,	PORT97_DATA,	PORT96_DATA }
3603 	},
3604 	{ PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
3605 		PORT127_DATA,	PORT126_DATA,	PORT125_DATA,	PORT124_DATA,
3606 		PORT123_DATA,	PORT122_DATA,	PORT121_DATA,	PORT120_DATA,
3607 		PORT119_DATA,	PORT118_DATA,	PORT117_DATA,	PORT116_DATA,
3608 		PORT115_DATA,	0, 0, 0,
3609 		0, 0, 0, 0,
3610 		0, 0, 0, 0,
3611 		0, 0, 0, 0,
3612 		0, 0, 0, 0 }
3613 	},
3614 	{ PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
3615 		PORT159_DATA,	PORT158_DATA,	PORT157_DATA,	PORT156_DATA,
3616 		PORT155_DATA,	PORT154_DATA,	PORT153_DATA,	PORT152_DATA,
3617 		PORT151_DATA,	PORT150_DATA,	PORT149_DATA,	PORT148_DATA,
3618 		PORT147_DATA,	PORT146_DATA,	PORT145_DATA,	PORT144_DATA,
3619 		PORT143_DATA,	PORT142_DATA,	PORT141_DATA,	PORT140_DATA,
3620 		PORT139_DATA,	PORT138_DATA,	PORT137_DATA,	PORT136_DATA,
3621 		PORT135_DATA,	PORT134_DATA,	PORT133_DATA,	PORT132_DATA,
3622 		PORT131_DATA,	PORT130_DATA,	PORT129_DATA,	PORT128_DATA }
3623 	},
3624 	{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
3625 		PORT191_DATA,	PORT190_DATA,	PORT189_DATA,	PORT188_DATA,
3626 		PORT187_DATA,	PORT186_DATA,	PORT185_DATA,	PORT184_DATA,
3627 		PORT183_DATA,	PORT182_DATA,	PORT181_DATA,	PORT180_DATA,
3628 		PORT179_DATA,	PORT178_DATA,	PORT177_DATA,	PORT176_DATA,
3629 		PORT175_DATA,	PORT174_DATA,	PORT173_DATA,	PORT172_DATA,
3630 		PORT171_DATA,	PORT170_DATA,	PORT169_DATA,	PORT168_DATA,
3631 		PORT167_DATA,	PORT166_DATA,	PORT165_DATA,	PORT164_DATA,
3632 		PORT163_DATA,	PORT162_DATA,	PORT161_DATA,	PORT160_DATA }
3633 	},
3634 	{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
3635 		0, 0, 0, 0,
3636 		0, 0, 0, 0,
3637 		0, 0, 0, 0,
3638 		0, 0,				PORT209_DATA,	PORT208_DATA,
3639 		PORT207_DATA,	PORT206_DATA,	PORT205_DATA,	PORT204_DATA,
3640 		PORT203_DATA,	PORT202_DATA,	PORT201_DATA,	PORT200_DATA,
3641 		PORT199_DATA,	PORT198_DATA,	PORT197_DATA,	PORT196_DATA,
3642 		PORT195_DATA,	PORT194_DATA,	PORT193_DATA,	PORT192_DATA }
3643 	},
3644 	{ PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
3645 		0, 0, 0, 0,
3646 		0, 0, 0, 0,
3647 		0, 0, 0, 0,
3648 		PORT211_DATA,	PORT210_DATA, 0, 0,
3649 		0, 0, 0, 0,
3650 		0, 0, 0, 0,
3651 		0, 0, 0, 0,
3652 		0, 0, 0, 0 }
3653 	},
3654 	{ },
3655 };
3656 
3657 static const struct pinmux_irq pinmux_irqs[] = {
3658 	PINMUX_IRQ(irq_pin(0), 2,   13),	/* IRQ0A */
3659 	PINMUX_IRQ(irq_pin(1), 20),		/* IRQ1A */
3660 	PINMUX_IRQ(irq_pin(2), 11,  12),	/* IRQ2A */
3661 	PINMUX_IRQ(irq_pin(3), 10,  14),	/* IRQ3A */
3662 	PINMUX_IRQ(irq_pin(4), 15,  172),	/* IRQ4A */
3663 	PINMUX_IRQ(irq_pin(5), 0,   1),		/* IRQ5A */
3664 	PINMUX_IRQ(irq_pin(6), 121, 173),	/* IRQ6A */
3665 	PINMUX_IRQ(irq_pin(7), 120, 209),	/* IRQ7A */
3666 	PINMUX_IRQ(irq_pin(8), 119),		/* IRQ8A */
3667 	PINMUX_IRQ(irq_pin(9), 118, 210),	/* IRQ9A */
3668 	PINMUX_IRQ(irq_pin(10), 19),		/* IRQ10A */
3669 	PINMUX_IRQ(irq_pin(11), 104),		/* IRQ11A */
3670 	PINMUX_IRQ(irq_pin(12), 42,  97),	/* IRQ12A */
3671 	PINMUX_IRQ(irq_pin(13), 64,  98),	/* IRQ13A */
3672 	PINMUX_IRQ(irq_pin(14), 63,  99),	/* IRQ14A */
3673 	PINMUX_IRQ(irq_pin(15), 62,  100),	/* IRQ15A */
3674 	PINMUX_IRQ(irq_pin(16), 68,  211),	/* IRQ16A */
3675 	PINMUX_IRQ(irq_pin(17), 69),		/* IRQ17A */
3676 	PINMUX_IRQ(irq_pin(18), 70),		/* IRQ18A */
3677 	PINMUX_IRQ(irq_pin(19), 71),		/* IRQ19A */
3678 	PINMUX_IRQ(irq_pin(20), 67),		/* IRQ20A */
3679 	PINMUX_IRQ(irq_pin(21), 202),		/* IRQ21A */
3680 	PINMUX_IRQ(irq_pin(22), 95),		/* IRQ22A */
3681 	PINMUX_IRQ(irq_pin(23), 96),		/* IRQ23A */
3682 	PINMUX_IRQ(irq_pin(24), 180),		/* IRQ24A */
3683 	PINMUX_IRQ(irq_pin(25), 38),		/* IRQ25A */
3684 	PINMUX_IRQ(irq_pin(26), 58,  81),	/* IRQ26A */
3685 	PINMUX_IRQ(irq_pin(27), 57,  168),	/* IRQ27A */
3686 	PINMUX_IRQ(irq_pin(28), 56,  169),	/* IRQ28A */
3687 	PINMUX_IRQ(irq_pin(29), 50,  170),	/* IRQ29A */
3688 	PINMUX_IRQ(irq_pin(30), 49,  171),	/* IRQ30A */
3689 	PINMUX_IRQ(irq_pin(31), 41,  167),	/* IRQ31A */
3690 };
3691 
3692 #define PORTnCR_PULMD_OFF	(0 << 6)
3693 #define PORTnCR_PULMD_DOWN	(2 << 6)
3694 #define PORTnCR_PULMD_UP	(3 << 6)
3695 #define PORTnCR_PULMD_MASK	(3 << 6)
3696 
3697 struct r8a7740_portcr_group {
3698 	unsigned int end_pin;
3699 	unsigned int offset;
3700 };
3701 
3702 static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
3703 	{ 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
3704 };
3705 
r8a7740_pinmux_portcr(struct sh_pfc * pfc,unsigned int pin)3706 static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
3707 {
3708 	unsigned int i;
3709 
3710 	for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) {
3711 		const struct r8a7740_portcr_group *group =
3712 			&r8a7740_portcr_offsets[i];
3713 
3714 		if (pin <= group->end_pin)
3715 			return pfc->windows->virt + group->offset + pin;
3716 	}
3717 
3718 	return NULL;
3719 }
3720 
r8a7740_pinmux_get_bias(struct sh_pfc * pfc,unsigned int pin)3721 static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
3722 {
3723 	void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
3724 	u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
3725 
3726 	switch (value) {
3727 	case PORTnCR_PULMD_UP:
3728 		return PIN_CONFIG_BIAS_PULL_UP;
3729 	case PORTnCR_PULMD_DOWN:
3730 		return PIN_CONFIG_BIAS_PULL_DOWN;
3731 	case PORTnCR_PULMD_OFF:
3732 	default:
3733 		return PIN_CONFIG_BIAS_DISABLE;
3734 	}
3735 }
3736 
r8a7740_pinmux_set_bias(struct sh_pfc * pfc,unsigned int pin,unsigned int bias)3737 static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3738 				   unsigned int bias)
3739 {
3740 	void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
3741 	u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
3742 
3743 	switch (bias) {
3744 	case PIN_CONFIG_BIAS_PULL_UP:
3745 		value |= PORTnCR_PULMD_UP;
3746 		break;
3747 	case PIN_CONFIG_BIAS_PULL_DOWN:
3748 		value |= PORTnCR_PULMD_DOWN;
3749 		break;
3750 	}
3751 
3752 	iowrite8(value, addr);
3753 }
3754 
3755 static const struct sh_pfc_soc_operations r8a7740_pfc_ops = {
3756 	.get_bias = r8a7740_pinmux_get_bias,
3757 	.set_bias = r8a7740_pinmux_set_bias,
3758 };
3759 
3760 const struct sh_pfc_soc_info r8a7740_pinmux_info = {
3761 	.name		= "r8a7740_pfc",
3762 	.ops		= &r8a7740_pfc_ops,
3763 
3764 	.input		= { PINMUX_INPUT_BEGIN,
3765 			    PINMUX_INPUT_END },
3766 	.output		= { PINMUX_OUTPUT_BEGIN,
3767 			    PINMUX_OUTPUT_END },
3768 	.function	= { PINMUX_FUNCTION_BEGIN,
3769 			    PINMUX_FUNCTION_END },
3770 
3771 	.pins		= pinmux_pins,
3772 	.nr_pins	= ARRAY_SIZE(pinmux_pins),
3773 	.groups		= pinmux_groups,
3774 	.nr_groups	= ARRAY_SIZE(pinmux_groups),
3775 	.functions	= pinmux_functions,
3776 	.nr_functions	= ARRAY_SIZE(pinmux_functions),
3777 
3778 	.cfg_regs	= pinmux_config_regs,
3779 	.data_regs	= pinmux_data_regs,
3780 
3781 	.gpio_data	= pinmux_data,
3782 	.gpio_data_size	= ARRAY_SIZE(pinmux_data),
3783 
3784 	.gpio_irq	= pinmux_irqs,
3785 	.gpio_irq_size	= ARRAY_SIZE(pinmux_irqs),
3786 };
3787