Searched refs:it_page_shift (Results 1 – 10 of 10) sorted by relevance
254 1 << tbl->it_page_shift); in iommu_range_alloc()256 boundary_size = ALIGN(1UL << 32, 1 << tbl->it_page_shift); in iommu_range_alloc()260 boundary_size >> tbl->it_page_shift, align_mask); in iommu_range_alloc()322 ret = entry << tbl->it_page_shift; /* Set the return dma address */ in iommu_alloc()354 entry = dma_addr >> tbl->it_page_shift; in iommu_free_check()403 entry = dma_addr >> tbl->it_page_shift; in __iommu_free()472 if (tbl->it_page_shift < PAGE_SHIFT && slen >= PAGE_SIZE && in ppc_iommu_map_sg()474 align = PAGE_SHIFT - tbl->it_page_shift; in ppc_iommu_map_sg()476 mask >> tbl->it_page_shift, align); in ppc_iommu_map_sg()491 dma_addr = entry << tbl->it_page_shift; in ppc_iommu_map_sg()[all …]
86 if (tbl->it_offset > (mask >> tbl->it_page_shift)) { in dma_iommu_dma_supported()89 mask, tbl->it_offset << tbl->it_page_shift); in dma_iommu_dma_supported()
1191 tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K; in vio_build_iommu_table()1192 tbl->it_size = size >> tbl->it_page_shift; in vio_build_iommu_table()1194 tbl->it_offset = offset >> tbl->it_page_shift; in vio_build_iommu_table()
39 #define IOMMU_PAGE_SIZE(tblptr) (ASM_CONST(1) << (tblptr)->it_page_shift)40 #define IOMMU_PAGE_MASK(tblptr) (~((1 << (tblptr)->it_page_shift) - 1))77 unsigned long it_page_shift;/* table iommu page size */ member91 return __ilog2((size - 1) >> tbl->it_page_shift) + 1; in get_iommu_order()
143 iommu_table_iobmap.it_page_shift = IOBMAP_PAGE_SHIFT; in iommu_table_iobmap_setup()147 0x80000000 >> iommu_table_iobmap.it_page_shift; in iommu_table_iobmap_setup()
489 tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K; in iommu_table_setparms()492 tbl->it_offset = phb->dma_window_base_cur >> tbl->it_page_shift; in iommu_table_setparms()503 tbl->it_size = phb->dma_window_size >> tbl->it_page_shift; in iommu_table_setparms()541 tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K; in iommu_table_setparms_lpar()545 tbl->it_offset = offset >> tbl->it_page_shift; in iommu_table_setparms_lpar()546 tbl->it_size = size >> tbl->it_page_shift; in iommu_table_setparms_lpar()
590 rpn = __pa(uaddr) >> tbl->it_page_shift; in pnv_tce_build()594 (rpn++ << tbl->it_page_shift)); in pnv_tce_build()658 tbl->it_page_shift = page_shift; in pnv_pci_setup_iommu_table()659 tbl->it_offset = dma_offset >> tbl->it_page_shift; in pnv_pci_setup_iommu_table()
1683 const unsigned shift = tbl->it_page_shift; in pnv_pci_ioda1_tce_invalidate()1730 const unsigned shift = tbl->it_page_shift; in pnv_pci_ioda2_tce_invalidate()
201 for (i = 0; i < npages; i++, uaddr += (1 << tbl->it_page_shift)) in tce_build_cell()491 window->table.it_page_shift = IOMMU_PAGE_SHIFT_4K; in cell_iommu_setup_window()493 (offset >> window->table.it_page_shift) + pte_offset; in cell_iommu_setup_window()494 window->table.it_size = size >> window->table.it_page_shift; in cell_iommu_setup_window()
295 iommu_table_dart.it_page_shift = IOMMU_PAGE_SHIFT_4K; in iommu_table_dart_setup()