| H A D | stv0900_sw.c | 38 int stv0900_check_signal_presence(struct stv0900_internal *intp, stv0900_check_signal_presence() argument
47 carr_offset = (stv0900_read_reg(intp, CFR2) << 8) stv0900_check_signal_presence()
48 | stv0900_read_reg(intp, CFR1); stv0900_check_signal_presence()
50 agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8) stv0900_check_signal_presence()
51 | stv0900_read_reg(intp, AGC2I0); stv0900_check_signal_presence()
52 max_carrier = intp->srch_range[demod] / 1000; stv0900_check_signal_presence()
56 max_carrier /= intp->mclk / 1000; stv0900_check_signal_presence()
68 static void stv0900_get_sw_loop_params(struct stv0900_internal *intp, stv0900_get_sw_loop_params() argument
77 srate = intp->symbol_rate[demod]; stv0900_get_sw_loop_params()
78 max_carrier = intp->srch_range[demod] / 1000; stv0900_get_sw_loop_params()
80 standard = intp->srch_standard[demod]; stv0900_get_sw_loop_params()
83 max_carrier /= intp->mclk / 1000; stv0900_get_sw_loop_params()
89 freq_inc /= intp->mclk >> 10; stv0900_get_sw_loop_params()
135 static int stv0900_search_carr_sw_loop(struct stv0900_internal *intp, stv0900_search_carr_sw_loop() argument
145 max_carrier = intp->srch_range[demod] / 1000; stv0900_search_carr_sw_loop()
149 max_carrier /= intp->mclk / 1000; stv0900_search_carr_sw_loop()
162 stv0900_write_reg(intp, DMDISTATE, 0x1c); stv0900_search_carr_sw_loop()
163 stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff); stv0900_search_carr_sw_loop()
164 stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff); stv0900_search_carr_sw_loop()
165 stv0900_write_reg(intp, DMDISTATE, 0x18); stv0900_search_carr_sw_loop()
166 stv0900_write_bits(intp, ALGOSWRST, 1); stv0900_search_carr_sw_loop()
168 if (intp->chip_id == 0x12) { stv0900_search_carr_sw_loop()
169 stv0900_write_bits(intp, RST_HWARE, 1); stv0900_search_carr_sw_loop()
170 stv0900_write_bits(intp, RST_HWARE, 0); stv0900_search_carr_sw_loop()
182 lock = stv0900_get_demod_lock(intp, demod, Timeout); stv0900_search_carr_sw_loop()
183 no_signal = stv0900_check_signal_presence(intp, demod); stv0900_search_carr_sw_loop()
191 stv0900_write_bits(intp, ALGOSWRST, 0); stv0900_search_carr_sw_loop()
196 static int stv0900_sw_algo(struct stv0900_internal *intp, stv0900_sw_algo() argument
208 stv0900_get_sw_loop_params(intp, &fqc_inc, &sft_stp_tout, stv0900_sw_algo()
210 switch (intp->srch_standard[demod]) { stv0900_sw_algo()
213 if (intp->chip_id >= 0x20) stv0900_sw_algo()
214 stv0900_write_reg(intp, CARFREQ, 0x3b); stv0900_sw_algo()
216 stv0900_write_reg(intp, CARFREQ, 0xef); stv0900_sw_algo()
218 stv0900_write_reg(intp, DMDCFGMD, 0x49); stv0900_sw_algo()
222 if (intp->chip_id >= 0x20) stv0900_sw_algo()
223 stv0900_write_reg(intp, CORRELABS, 0x79); stv0900_sw_algo()
225 stv0900_write_reg(intp, CORRELABS, 0x68); stv0900_sw_algo()
227 stv0900_write_reg(intp, DMDCFGMD, 0x89); stv0900_sw_algo()
233 if (intp->chip_id >= 0x20) { stv0900_sw_algo()
234 stv0900_write_reg(intp, CARFREQ, 0x3b); stv0900_sw_algo()
235 stv0900_write_reg(intp, CORRELABS, 0x79); stv0900_sw_algo()
237 stv0900_write_reg(intp, CARFREQ, 0xef); stv0900_sw_algo()
238 stv0900_write_reg(intp, CORRELABS, 0x68); stv0900_sw_algo()
241 stv0900_write_reg(intp, DMDCFGMD, 0xc9); stv0900_sw_algo()
248 lock = stv0900_search_carr_sw_loop(intp, stv0900_sw_algo()
254 no_signal = stv0900_check_signal_presence(intp, demod); stv0900_sw_algo()
260 if (intp->chip_id >= 0x20) { stv0900_sw_algo()
261 stv0900_write_reg(intp, CARFREQ, 0x49); stv0900_sw_algo()
262 stv0900_write_reg(intp, CORRELABS, 0x9e); stv0900_sw_algo()
264 stv0900_write_reg(intp, CARFREQ, 0xed); stv0900_sw_algo()
265 stv0900_write_reg(intp, CORRELABS, 0x88); stv0900_sw_algo()
268 if ((stv0900_get_bits(intp, HEADER_MODE) == stv0900_sw_algo()
272 s2fw = stv0900_get_bits(intp, FLYWHEEL_CPT); stv0900_sw_algo()
276 s2fw = stv0900_get_bits(intp, stv0900_sw_algo()
284 if (intp->chip_id >= 0x20) stv0900_sw_algo()
285 stv0900_write_reg(intp, stv0900_sw_algo()
289 stv0900_write_reg(intp, stv0900_sw_algo()
293 stv0900_write_reg(intp, stv0900_sw_algo()
308 static u32 stv0900_get_symbol_rate(struct stv0900_internal *intp, stv0900_get_symbol_rate() argument
314 srate = (stv0900_get_bits(intp, SYMB_FREQ3) << 24) + stv0900_get_symbol_rate()
315 (stv0900_get_bits(intp, SYMB_FREQ2) << 16) + stv0900_get_symbol_rate()
316 (stv0900_get_bits(intp, SYMB_FREQ1) << 8) + stv0900_get_symbol_rate()
317 (stv0900_get_bits(intp, SYMB_FREQ0)); stv0900_get_symbol_rate()
319 srate, stv0900_get_bits(intp, SYMB_FREQ0), stv0900_get_symbol_rate()
320 stv0900_get_bits(intp, SYMB_FREQ1), stv0900_get_symbol_rate()
321 stv0900_get_bits(intp, SYMB_FREQ2), stv0900_get_symbol_rate()
322 stv0900_get_bits(intp, SYMB_FREQ3)); stv0900_get_symbol_rate()
336 static void stv0900_set_symbol_rate(struct stv0900_internal *intp, stv0900_set_symbol_rate() argument
356 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f); stv0900_set_symbol_rate()
357 stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff)); stv0900_set_symbol_rate()
360 static void stv0900_set_max_symbol_rate(struct stv0900_internal *intp, stv0900_set_max_symbol_rate() argument
380 stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f); stv0900_set_max_symbol_rate()
381 stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff)); stv0900_set_max_symbol_rate()
383 stv0900_write_reg(intp, SFRUP1, 0x7f); stv0900_set_max_symbol_rate()
384 stv0900_write_reg(intp, SFRUP1 + 1, 0xff); stv0900_set_max_symbol_rate()
388 static void stv0900_set_min_symbol_rate(struct stv0900_internal *intp, stv0900_set_min_symbol_rate() argument
408 stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff); stv0900_set_min_symbol_rate()
409 stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff)); stv0900_set_min_symbol_rate()
412 static s32 stv0900_get_timing_offst(struct stv0900_internal *intp, stv0900_get_timing_offst() argument
419 timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) + stv0900_get_timing_offst()
420 (stv0900_read_reg(intp, TMGREG2 + 1) << 8) + stv0900_get_timing_offst()
421 (stv0900_read_reg(intp, TMGREG2 + 2)); stv0900_get_timing_offst()
435 static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *intp, stv0900_set_dvbs2_rolloff() argument
440 if (intp->chip_id == 0x10) { stv0900_set_dvbs2_rolloff()
441 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1); stv0900_set_dvbs2_rolloff()
442 rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03; stv0900_set_dvbs2_rolloff()
443 stv0900_write_bits(intp, ROLLOFF_CONTROL, rolloff); stv0900_set_dvbs2_rolloff()
444 } else if (intp->chip_id <= 0x20) stv0900_set_dvbs2_rolloff()
445 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0); stv0900_set_dvbs2_rolloff()
447 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0); stv0900_set_dvbs2_rolloff()
470 static int stv0900_check_timing_lock(struct stv0900_internal *intp, stv0900_check_timing_lock() argument
480 car_freq = stv0900_read_reg(intp, CARFREQ); stv0900_check_timing_lock()
481 tmg_th_high = stv0900_read_reg(intp, TMGTHRISE); stv0900_check_timing_lock()
482 tmg_th_low = stv0900_read_reg(intp, TMGTHFALL); stv0900_check_timing_lock()
483 stv0900_write_reg(intp, TMGTHRISE, 0x20); stv0900_check_timing_lock()
484 stv0900_write_reg(intp, TMGTHFALL, 0x0); stv0900_check_timing_lock()
485 stv0900_write_bits(intp, CFR_AUTOSCAN, 0); stv0900_check_timing_lock()
486 stv0900_write_reg(intp, RTC, 0x80); stv0900_check_timing_lock()
487 stv0900_write_reg(intp, RTCS2, 0x40); stv0900_check_timing_lock()
488 stv0900_write_reg(intp, CARFREQ, 0x0); stv0900_check_timing_lock()
489 stv0900_write_reg(intp, CFRINIT1, 0x0); stv0900_check_timing_lock()
490 stv0900_write_reg(intp, CFRINIT0, 0x0); stv0900_check_timing_lock()
491 stv0900_write_reg(intp, AGC2REF, 0x65); stv0900_check_timing_lock()
492 stv0900_write_reg(intp, DMDISTATE, 0x18); stv0900_check_timing_lock()
496 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2) stv0900_check_timing_lock()
505 stv0900_write_reg(intp, AGC2REF, 0x38); stv0900_check_timing_lock()
506 stv0900_write_reg(intp, RTC, 0x88); stv0900_check_timing_lock()
507 stv0900_write_reg(intp, RTCS2, 0x68); stv0900_check_timing_lock()
508 stv0900_write_reg(intp, CARFREQ, car_freq); stv0900_check_timing_lock()
509 stv0900_write_reg(intp, TMGTHRISE, tmg_th_high); stv0900_check_timing_lock()
510 stv0900_write_reg(intp, TMGTHFALL, tmg_th_low); stv0900_check_timing_lock()
519 struct stv0900_internal *intp = state->internal; stv0900_get_demod_cold_lock() local
534 srate = intp->symbol_rate[d]; stv0900_get_demod_cold_lock()
535 search_range = intp->srch_range[d]; stv0900_get_demod_cold_lock()
542 lock = stv0900_get_demod_lock(intp, d, locktimeout); stv0900_get_demod_cold_lock()
548 if (stv0900_check_timing_lock(intp, d) == TRUE) { stv0900_get_demod_cold_lock()
549 stv0900_write_reg(intp, DMDISTATE, 0x1f); stv0900_get_demod_cold_lock()
550 stv0900_write_reg(intp, DMDISTATE, 0x15); stv0900_get_demod_cold_lock()
551 lock = stv0900_get_demod_lock(intp, d, demod_timeout); stv0900_get_demod_cold_lock()
558 if (intp->chip_id <= 0x20) { stv0900_get_demod_cold_lock()
595 if (intp->chip_id <= 0x20) { stv0900_get_demod_cold_lock()
596 tuner_freq = intp->freq[d]; stv0900_get_demod_cold_lock()
597 intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d], stv0900_get_demod_cold_lock()
598 intp->rolloff) + intp->symbol_rate[d]; stv0900_get_demod_cold_lock()
608 if (intp->chip_id <= 0x20) { stv0900_get_demod_cold_lock()
609 if (intp->tuner_type[d] == 3) stv0900_get_demod_cold_lock()
610 stv0900_set_tuner_auto(intp, tuner_freq, stv0900_get_demod_cold_lock()
611 intp->bw[d], demod); stv0900_get_demod_cold_lock()
613 stv0900_set_tuner(fe, tuner_freq, intp->bw[d]); stv0900_get_demod_cold_lock()
615 stv0900_write_reg(intp, DMDISTATE, 0x1c); stv0900_get_demod_cold_lock()
616 stv0900_write_reg(intp, CFRINIT1, 0); stv0900_get_demod_cold_lock()
617 stv0900_write_reg(intp, CFRINIT0, 0); stv0900_get_demod_cold_lock()
618 stv0900_write_reg(intp, DMDISTATE, 0x1f); stv0900_get_demod_cold_lock()
619 stv0900_write_reg(intp, DMDISTATE, 0x15); stv0900_get_demod_cold_lock()
621 stv0900_write_reg(intp, DMDISTATE, 0x1c); stv0900_get_demod_cold_lock()
622 freq = (tuner_freq * 65536) / (intp->mclk / 1000); stv0900_get_demod_cold_lock()
623 stv0900_write_bits(intp, CFR_INIT1, MSB(freq)); stv0900_get_demod_cold_lock()
624 stv0900_write_bits(intp, CFR_INIT0, LSB(freq)); stv0900_get_demod_cold_lock()
625 stv0900_write_reg(intp, DMDISTATE, 0x1f); stv0900_get_demod_cold_lock()
626 stv0900_write_reg(intp, DMDISTATE, 0x05); stv0900_get_demod_cold_lock()
629 lock = stv0900_get_demod_lock(intp, d, timeout); stv0900_get_demod_cold_lock()
686 static void stv0900_set_viterbi_tracq(struct stv0900_internal *intp, stv0900_set_viterbi_tracq() argument
694 stv0900_write_reg(intp, vth_reg++, 0xd0); stv0900_set_viterbi_tracq()
695 stv0900_write_reg(intp, vth_reg++, 0x7d); stv0900_set_viterbi_tracq()
696 stv0900_write_reg(intp, vth_reg++, 0x53); stv0900_set_viterbi_tracq()
697 stv0900_write_reg(intp, vth_reg++, 0x2f); stv0900_set_viterbi_tracq()
698 stv0900_write_reg(intp, vth_reg++, 0x24); stv0900_set_viterbi_tracq()
699 stv0900_write_reg(intp, vth_reg++, 0x1f); stv0900_set_viterbi_tracq()
702 static void stv0900_set_viterbi_standard(struct stv0900_internal *intp, stv0900_set_viterbi_standard() argument
712 stv0900_write_reg(intp, FECM, 0x10); stv0900_set_viterbi_standard()
713 stv0900_write_reg(intp, PRVIT, 0x3f); stv0900_set_viterbi_standard()
717 stv0900_write_reg(intp, FECM, 0x00); stv0900_set_viterbi_standard()
721 stv0900_write_reg(intp, PRVIT, 0x2f); stv0900_set_viterbi_standard()
724 stv0900_write_reg(intp, PRVIT, 0x01); stv0900_set_viterbi_standard()
727 stv0900_write_reg(intp, PRVIT, 0x02); stv0900_set_viterbi_standard()
730 stv0900_write_reg(intp, PRVIT, 0x04); stv0900_set_viterbi_standard()
733 stv0900_write_reg(intp, PRVIT, 0x08); stv0900_set_viterbi_standard()
736 stv0900_write_reg(intp, PRVIT, 0x20); stv0900_set_viterbi_standard()
743 stv0900_write_reg(intp, FECM, 0x80); stv0900_set_viterbi_standard()
747 stv0900_write_reg(intp, PRVIT, 0x13); stv0900_set_viterbi_standard()
750 stv0900_write_reg(intp, PRVIT, 0x01); stv0900_set_viterbi_standard()
753 stv0900_write_reg(intp, PRVIT, 0x02); stv0900_set_viterbi_standard()
756 stv0900_write_reg(intp, PRVIT, 0x10); stv0900_set_viterbi_standard()
765 static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *intp, stv0900_get_vit_fec() argument
769 s32 rate_fld = stv0900_get_bits(intp, VIT_CURPUN); stv0900_get_vit_fec()
798 static void stv0900_set_dvbs1_track_car_loop(struct stv0900_internal *intp, stv0900_set_dvbs1_track_car_loop() argument
802 if (intp->chip_id >= 0x30) { stv0900_set_dvbs1_track_car_loop()
804 stv0900_write_reg(intp, ACLC, 0x2b); stv0900_set_dvbs1_track_car_loop()
805 stv0900_write_reg(intp, BCLC, 0x1a); stv0900_set_dvbs1_track_car_loop()
807 stv0900_write_reg(intp, ACLC, 0x0c); stv0900_set_dvbs1_track_car_loop()
808 stv0900_write_reg(intp, BCLC, 0x1b); stv0900_set_dvbs1_track_car_loop()
810 stv0900_write_reg(intp, ACLC, 0x2c); stv0900_set_dvbs1_track_car_loop()
811 stv0900_write_reg(intp, BCLC, 0x1c); stv0900_set_dvbs1_track_car_loop()
815 stv0900_write_reg(intp, ACLC, 0x1a); stv0900_set_dvbs1_track_car_loop()
816 stv0900_write_reg(intp, BCLC, 0x09); stv0900_set_dvbs1_track_car_loop()
824 struct stv0900_internal *intp = state->internal; stv0900_track_optimization() local
842 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod); stv0900_track_optimization()
843 srate += stv0900_get_timing_offst(intp, srate, demod); stv0900_track_optimization()
845 switch (intp->result[demod].standard) { stv0900_track_optimization()
849 if (intp->srch_standard[demod] == STV0900_AUTO_SEARCH) { stv0900_track_optimization()
850 stv0900_write_bits(intp, DVBS1_ENABLE, 1); stv0900_track_optimization()
851 stv0900_write_bits(intp, DVBS2_ENABLE, 0); stv0900_track_optimization()
854 stv0900_write_bits(intp, ROLLOFF_CONTROL, intp->rolloff); stv0900_track_optimization()
855 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1); stv0900_track_optimization()
857 if (intp->chip_id < 0x30) { stv0900_track_optimization()
858 stv0900_write_reg(intp, ERRCTRL1, 0x75); stv0900_track_optimization()
862 if (stv0900_get_vit_fec(intp, demod) == STV0900_FEC_1_2) { stv0900_track_optimization()
863 stv0900_write_reg(intp, GAUSSR0, 0x98); stv0900_track_optimization()
864 stv0900_write_reg(intp, CCIR0, 0x18); stv0900_track_optimization()
866 stv0900_write_reg(intp, GAUSSR0, 0x18); stv0900_track_optimization()
867 stv0900_write_reg(intp, CCIR0, 0x18); stv0900_track_optimization()
870 stv0900_write_reg(intp, ERRCTRL1, 0x75); stv0900_track_optimization()
874 stv0900_write_bits(intp, DVBS1_ENABLE, 0); stv0900_track_optimization()
875 stv0900_write_bits(intp, DVBS2_ENABLE, 1); stv0900_track_optimization()
876 stv0900_write_reg(intp, ACLC, 0); stv0900_track_optimization()
877 stv0900_write_reg(intp, BCLC, 0); stv0900_track_optimization()
878 if (intp->result[demod].frame_len == STV0900_LONG_FRAME) { stv0900_track_optimization()
879 foundModcod = stv0900_get_bits(intp, DEMOD_MODCOD); stv0900_track_optimization()
880 pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01; stv0900_track_optimization()
884 intp->chip_id); stv0900_track_optimization()
886 stv0900_write_reg(intp, ACLC2S2Q, aclc); stv0900_track_optimization()
888 stv0900_write_reg(intp, ACLC2S2Q, 0x2a); stv0900_track_optimization()
889 stv0900_write_reg(intp, ACLC2S28, aclc); stv0900_track_optimization()
892 if ((intp->demod_mode == STV0900_SINGLE) && stv0900_track_optimization()
895 stv0900_write_reg(intp, ACLC2S2Q, 0x2a); stv0900_track_optimization()
896 stv0900_write_reg(intp, ACLC2S216A, stv0900_track_optimization()
899 stv0900_write_reg(intp, ACLC2S2Q, 0x2a); stv0900_track_optimization()
900 stv0900_write_reg(intp, ACLC2S232A, stv0900_track_optimization()
906 modulation = intp->result[demod].modulation; stv0900_track_optimization()
908 modulation, intp->chip_id); stv0900_track_optimization()
910 stv0900_write_reg(intp, ACLC2S2Q, aclc); stv0900_track_optimization()
912 stv0900_write_reg(intp, ACLC2S2Q, 0x2a); stv0900_track_optimization()
913 stv0900_write_reg(intp, ACLC2S28, aclc); stv0900_track_optimization()
915 stv0900_write_reg(intp, ACLC2S2Q, 0x2a); stv0900_track_optimization()
916 stv0900_write_reg(intp, ACLC2S216A, aclc); stv0900_track_optimization()
918 stv0900_write_reg(intp, ACLC2S2Q, 0x2a); stv0900_track_optimization()
919 stv0900_write_reg(intp, ACLC2S232A, aclc); stv0900_track_optimization()
924 if (intp->chip_id <= 0x11) { stv0900_track_optimization()
925 if (intp->demod_mode != STV0900_SINGLE) stv0900_track_optimization()
926 stv0900_activate_s2_modcod(intp, demod); stv0900_track_optimization()
930 stv0900_write_reg(intp, ERRCTRL1, 0x67); stv0900_track_optimization()
935 stv0900_write_bits(intp, DVBS1_ENABLE, 1); stv0900_track_optimization()
936 stv0900_write_bits(intp, DVBS2_ENABLE, 1); stv0900_track_optimization()
940 freq1 = stv0900_read_reg(intp, CFR2); stv0900_track_optimization()
941 freq0 = stv0900_read_reg(intp, CFR1); stv0900_track_optimization()
942 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) { stv0900_track_optimization()
943 stv0900_write_reg(intp, SFRSTEP, 0x00); stv0900_track_optimization()
944 stv0900_write_bits(intp, SCAN_ENABLE, 0); stv0900_track_optimization()
945 stv0900_write_bits(intp, CFR_AUTOSCAN, 0); stv0900_track_optimization()
946 stv0900_write_reg(intp, TMGCFG2, 0xc1); stv0900_track_optimization()
947 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod); stv0900_track_optimization()
949 if (intp->result[demod].standard != STV0900_DVBS2_STANDARD) stv0900_track_optimization()
950 stv0900_set_dvbs1_track_car_loop(intp, demod, srate); stv0900_track_optimization()
954 if (intp->chip_id >= 0x20) { stv0900_track_optimization()
955 if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) || stv0900_track_optimization()
956 (intp->srch_standard[demod] == stv0900_track_optimization()
958 (intp->srch_standard[demod] == stv0900_track_optimization()
960 stv0900_write_reg(intp, VAVSRVIT, 0x0a); stv0900_track_optimization()
961 stv0900_write_reg(intp, VITSCALE, 0x0); stv0900_track_optimization()
965 if (intp->chip_id < 0x20) stv0900_track_optimization()
966 stv0900_write_reg(intp, CARHDR, 0x08); stv0900_track_optimization()
968 if (intp->chip_id == 0x10) stv0900_track_optimization()
969 stv0900_write_reg(intp, CORRELEXP, 0x0a); stv0900_track_optimization()
971 stv0900_write_reg(intp, AGC2REF, 0x38); stv0900_track_optimization()
973 if ((intp->chip_id >= 0x20) || stv0900_track_optimization()
975 (intp->symbol_rate[demod] < 10000000)) { stv0900_track_optimization()
976 stv0900_write_reg(intp, CFRINIT1, freq1); stv0900_track_optimization()
977 stv0900_write_reg(intp, CFRINIT0, freq0); stv0900_track_optimization()
978 intp->bw[demod] = stv0900_carrier_width(srate, stv0900_track_optimization()
979 intp->rolloff) + 10000000; stv0900_track_optimization()
981 if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) { stv0900_track_optimization()
982 if (intp->srch_algo[demod] != STV0900_WARM_START) { stv0900_track_optimization()
983 if (intp->tuner_type[demod] == 3) stv0900_track_optimization()
984 stv0900_set_tuner_auto(intp, stv0900_track_optimization()
985 intp->freq[demod], stv0900_track_optimization()
986 intp->bw[demod], stv0900_track_optimization()
990 intp->bw[demod]); stv0900_track_optimization()
994 if ((intp->srch_algo[demod] == STV0900_BLIND_SEARCH) || stv0900_track_optimization()
995 (intp->symbol_rate[demod] < 10000000)) stv0900_track_optimization()
1003 if (stv0900_get_demod_lock(intp, demod, timed / 2) == FALSE) { stv0900_track_optimization()
1004 stv0900_write_reg(intp, DMDISTATE, 0x1f); stv0900_track_optimization()
1005 stv0900_write_reg(intp, CFRINIT1, freq1); stv0900_track_optimization()
1006 stv0900_write_reg(intp, CFRINIT0, freq0); stv0900_track_optimization()
1007 stv0900_write_reg(intp, DMDISTATE, 0x18); stv0900_track_optimization()
1009 while ((stv0900_get_demod_lock(intp, stv0900_track_optimization()
1013 stv0900_write_reg(intp, DMDISTATE, 0x1f); stv0900_track_optimization()
1014 stv0900_write_reg(intp, CFRINIT1, freq1); stv0900_track_optimization()
1015 stv0900_write_reg(intp, CFRINIT0, freq0); stv0900_track_optimization()
1016 stv0900_write_reg(intp, DMDISTATE, 0x18); stv0900_track_optimization()
1023 if (intp->chip_id >= 0x20) stv0900_track_optimization()
1024 stv0900_write_reg(intp, CARFREQ, 0x49); stv0900_track_optimization()
1026 if ((intp->result[demod].standard == STV0900_DVBS1_STANDARD) || stv0900_track_optimization()
1027 (intp->result[demod].standard == STV0900_DSS_STANDARD)) stv0900_track_optimization()
1028 stv0900_set_viterbi_tracq(intp, demod); stv0900_track_optimization()
1032 static int stv0900_get_fec_lock(struct stv0900_internal *intp, stv0900_get_fec_lock() argument
1041 dmd_state = stv0900_get_bits(intp, HEADER_MODE); stv0900_get_fec_lock()
1051 lock = stv0900_get_bits(intp, PKTDELIN_LOCK); stv0900_get_fec_lock()
1054 lock = stv0900_get_bits(intp, LOCKEDVIT); stv0900_get_fec_lock()
1072 static int stv0900_wait_for_lock(struct stv0900_internal *intp, stv0900_wait_for_lock() argument
1081 lock = stv0900_get_demod_lock(intp, demod, dmd_timeout); stv0900_wait_for_lock()
1084 lock = stv0900_get_fec_lock(intp, demod, fec_timeout); stv0900_wait_for_lock()
1093 lock = stv0900_get_bits(intp, TSFIFO_LINEOK); stv0900_wait_for_lock()
1114 struct stv0900_internal *intp = state->internal; stv0900_get_standard() local
1117 int hdr_mode = stv0900_get_bits(intp, HEADER_MODE); stv0900_get_standard()
1124 if (stv0900_get_bits(intp, DSS_DVB) == 1) stv0900_get_standard()
1139 static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk, stv0900_get_carr_freq() argument
1148 derot = (stv0900_get_bits(intp, CAR_FREQ2) << 16) + stv0900_get_carr_freq()
1149 (stv0900_get_bits(intp, CAR_FREQ1) << 8) + stv0900_get_carr_freq()
1150 (stv0900_get_bits(intp, CAR_FREQ0)); stv0900_get_carr_freq()
1188 struct stv0900_internal *intp = state->internal; stv0900_get_signal_params() local
1191 struct stv0900_signal_info *result = &intp->result[demod]; stv0900_get_signal_params()
1200 if (intp->srch_algo[d] == STV0900_BLIND_SEARCH) { stv0900_get_signal_params()
1201 timing = stv0900_read_reg(intp, TMGREG2); stv0900_get_signal_params()
1203 stv0900_write_reg(intp, SFRSTEP, 0x5c); stv0900_get_signal_params()
1206 timing = stv0900_read_reg(intp, TMGREG2); stv0900_get_signal_params()
1213 if (intp->tuner_type[demod] == 3) stv0900_get_signal_params()
1214 result->frequency = stv0900_get_freq_auto(intp, d); stv0900_get_signal_params()
1218 offsetFreq = stv0900_get_carr_freq(intp, intp->mclk, d) / 1000; stv0900_get_signal_params()
1220 result->symbol_rate = stv0900_get_symbol_rate(intp, intp->mclk, d); stv0900_get_signal_params()
1221 srate_offset = stv0900_get_timing_offst(intp, result->symbol_rate, d); stv0900_get_signal_params()
1223 result->fec = stv0900_get_vit_fec(intp, d); stv0900_get_signal_params()
1224 result->modcode = stv0900_get_bits(intp, DEMOD_MODCOD); stv0900_get_signal_params()
1225 result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01; stv0900_get_signal_params()
1226 result->frame_len = ((u32)stv0900_get_bits(intp, DEMOD_TYPE)) >> 1; stv0900_get_signal_params()
1227 result->rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS); stv0900_get_signal_params()
1233 result->spectrum = stv0900_get_bits(intp, SPECINV_DEMOD); stv0900_get_signal_params()
1247 result->spectrum = stv0900_get_bits(intp, IQINV); stv0900_get_signal_params()
1254 if ((intp->srch_algo[d] == STV0900_BLIND_SEARCH) || stv0900_get_signal_params()
1255 (intp->symbol_rate[d] < 10000000)) { stv0900_get_signal_params()
1256 offsetFreq = result->frequency - intp->freq[d]; stv0900_get_signal_params()
1257 if (intp->tuner_type[demod] == 3) stv0900_get_signal_params()
1258 intp->freq[d] = stv0900_get_freq_auto(intp, d); stv0900_get_signal_params()
1260 intp->freq[d] = stv0900_get_tuner_freq(fe); stv0900_get_signal_params()
1262 if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500)) stv0900_get_signal_params()
1269 } else if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500)) stv0900_get_signal_params()
1281 struct stv0900_internal *intp = state->internal; stv0900_dvbs1_acq_workaround() local
1291 intp->result[demod].locked = FALSE; stv0900_dvbs1_acq_workaround()
1293 if (stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) { stv0900_dvbs1_acq_workaround()
1294 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod); stv0900_dvbs1_acq_workaround()
1295 srate += stv0900_get_timing_offst(intp, srate, demod); stv0900_dvbs1_acq_workaround()
1296 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) stv0900_dvbs1_acq_workaround()
1297 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod); stv0900_dvbs1_acq_workaround()
1301 freq1 = stv0900_read_reg(intp, CFR2); stv0900_dvbs1_acq_workaround()
1302 freq0 = stv0900_read_reg(intp, CFR1); stv0900_dvbs1_acq_workaround()
1303 stv0900_write_bits(intp, CFR_AUTOSCAN, 0); stv0900_dvbs1_acq_workaround()
1304 stv0900_write_bits(intp, SPECINV_CONTROL, stv0900_dvbs1_acq_workaround()
1306 stv0900_write_reg(intp, DMDISTATE, 0x1c); stv0900_dvbs1_acq_workaround()
1307 stv0900_write_reg(intp, CFRINIT1, freq1); stv0900_dvbs1_acq_workaround()
1308 stv0900_write_reg(intp, CFRINIT0, freq0); stv0900_dvbs1_acq_workaround()
1309 stv0900_write_reg(intp, DMDISTATE, 0x18); stv0900_dvbs1_acq_workaround()
1310 if (stv0900_wait_for_lock(intp, demod, stv0900_dvbs1_acq_workaround()
1312 intp->result[demod].locked = TRUE; stv0900_dvbs1_acq_workaround()
1316 stv0900_write_bits(intp, SPECINV_CONTROL, stv0900_dvbs1_acq_workaround()
1318 stv0900_write_reg(intp, DMDISTATE, 0x1c); stv0900_dvbs1_acq_workaround()
1319 stv0900_write_reg(intp, CFRINIT1, freq1); stv0900_dvbs1_acq_workaround()
1320 stv0900_write_reg(intp, CFRINIT0, freq0); stv0900_dvbs1_acq_workaround()
1321 stv0900_write_reg(intp, DMDISTATE, 0x18); stv0900_dvbs1_acq_workaround()
1322 if (stv0900_wait_for_lock(intp, demod, stv0900_dvbs1_acq_workaround()
1324 intp->result[demod].locked = TRUE; stv0900_dvbs1_acq_workaround()
1332 intp->result[demod].locked = FALSE; stv0900_dvbs1_acq_workaround()
1337 static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *intp, stv0900_blind_check_agc2_min_level() argument
1348 stv0900_write_reg(intp, AGC2REF, 0x38); stv0900_blind_check_agc2_min_level()
1349 stv0900_write_bits(intp, SCAN_ENABLE, 0); stv0900_blind_check_agc2_min_level()
1350 stv0900_write_bits(intp, CFR_AUTOSCAN, 0); stv0900_blind_check_agc2_min_level()
1352 stv0900_write_bits(intp, AUTO_GUP, 1); stv0900_blind_check_agc2_min_level()
1353 stv0900_write_bits(intp, AUTO_GLOW, 1); stv0900_blind_check_agc2_min_level()
1355 stv0900_write_reg(intp, DMDT0M, 0x0); stv0900_blind_check_agc2_min_level()
1357 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod); stv0900_blind_check_agc2_min_level()
1358 nb_steps = -1 + (intp->srch_range[demod] / 1000000); stv0900_blind_check_agc2_min_level()
1367 freq_step = (1000000 << 8) / (intp->mclk >> 8); stv0900_blind_check_agc2_min_level()
1378 stv0900_write_reg(intp, DMDISTATE, 0x5C); stv0900_blind_check_agc2_min_level()
1379 stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff); stv0900_blind_check_agc2_min_level()
1380 stv0900_write_reg(intp, CFRINIT0, init_freq & 0xff); stv0900_blind_check_agc2_min_level()
1381 stv0900_write_reg(intp, DMDISTATE, 0x58); stv0900_blind_check_agc2_min_level()
1386 agc2level += (stv0900_read_reg(intp, AGC2I1) << 8) stv0900_blind_check_agc2_min_level()
1387 | stv0900_read_reg(intp, AGC2I0); stv0900_blind_check_agc2_min_level()
1402 struct stv0900_internal *intp = state->internal; stv0900_search_srate_coarse() local
1415 if (intp->chip_id >= 0x30) stv0900_search_srate_coarse()
1420 stv0900_write_bits(intp, DEMOD_MODE, 0x1f); stv0900_search_srate_coarse()
1421 stv0900_write_reg(intp, TMGCFG, 0x12); stv0900_search_srate_coarse()
1422 stv0900_write_reg(intp, TMGTHRISE, 0xf0); stv0900_search_srate_coarse()
1423 stv0900_write_reg(intp, TMGTHFALL, 0xe0); stv0900_search_srate_coarse()
1424 stv0900_write_bits(intp, SCAN_ENABLE, 1); stv0900_search_srate_coarse()
1425 stv0900_write_bits(intp, CFR_AUTOSCAN, 1); stv0900_search_srate_coarse()
1426 stv0900_write_reg(intp, SFRUP1, 0x83); stv0900_search_srate_coarse()
1427 stv0900_write_reg(intp, SFRUP0, 0xc0); stv0900_search_srate_coarse()
1428 stv0900_write_reg(intp, SFRLOW1, 0x82); stv0900_search_srate_coarse()
1429 stv0900_write_reg(intp, SFRLOW0, 0xa0); stv0900_search_srate_coarse()
1430 stv0900_write_reg(intp, DMDT0M, 0x0); stv0900_search_srate_coarse()
1431 stv0900_write_reg(intp, AGC2REF, 0x50); stv0900_search_srate_coarse()
1433 if (intp->chip_id >= 0x30) { stv0900_search_srate_coarse()
1434 stv0900_write_reg(intp, CARFREQ, 0x99); stv0900_search_srate_coarse()
1435 stv0900_write_reg(intp, SFRSTEP, 0x98); stv0900_search_srate_coarse()
1436 } else if (intp->chip_id >= 0x20) { stv0900_search_srate_coarse()
1437 stv0900_write_reg(intp, CARFREQ, 0x6a); stv0900_search_srate_coarse()
1438 stv0900_write_reg(intp, SFRSTEP, 0x95); stv0900_search_srate_coarse()
1440 stv0900_write_reg(intp, CARFREQ, 0xed); stv0900_search_srate_coarse()
1441 stv0900_write_reg(intp, SFRSTEP, 0x73); stv0900_search_srate_coarse()
1444 if (intp->symbol_rate[demod] <= 2000000) stv0900_search_srate_coarse()
1446 else if (intp->symbol_rate[demod] <= 5000000) stv0900_search_srate_coarse()
1448 else if (intp->symbol_rate[demod] <= 12000000) stv0900_search_srate_coarse()
1453 nb_steps = -1 + ((intp->srch_range[demod] / 1000) / currier_step); stv0900_search_srate_coarse()
1461 currier_step = (intp->srch_range[demod] / 1000) / 10; stv0900_search_srate_coarse()
1467 tuner_freq = intp->freq[demod]; stv0900_search_srate_coarse()
1470 stv0900_write_reg(intp, DMDISTATE, 0x5f); stv0900_search_srate_coarse()
1471 stv0900_write_bits(intp, DEMOD_MODE, 0); stv0900_search_srate_coarse()
1476 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2) stv0900_search_srate_coarse()
1479 agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) | stv0900_search_srate_coarse()
1480 stv0900_read_reg(intp, AGC2I0); stv0900_search_srate_coarse()
1484 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod); stv0900_search_srate_coarse()
1503 if (intp->tuner_type[demod] == 3) stv0900_search_srate_coarse()
1504 stv0900_set_tuner_auto(intp, tuner_freq, stv0900_search_srate_coarse()
1505 intp->bw[demod], demod); stv0900_search_srate_coarse()
1508 intp->bw[demod]); stv0900_search_srate_coarse()
1515 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod); stv0900_search_srate_coarse()
1523 struct stv0900_internal *intp = state->internal; stv0900_search_srate_fine() local
1532 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod); stv0900_search_srate_fine()
1537 symbmax /= (intp->mclk / 1000); stv0900_search_srate_fine()
1541 symbmin /= (intp->mclk / 1000); stv0900_search_srate_fine()
1544 symb /= (intp->mclk / 1000); stv0900_search_srate_fine()
1548 symbmax /= (intp->mclk / 100); stv0900_search_srate_fine()
1552 symbmin /= (intp->mclk / 100); stv0900_search_srate_fine()
1555 symb /= (intp->mclk / 100); stv0900_search_srate_fine()
1559 coarse_freq = (stv0900_read_reg(intp, CFR2) << 8) stv0900_search_srate_fine()
1560 | stv0900_read_reg(intp, CFR1); stv0900_search_srate_fine()
1562 if (symbcomp < intp->symbol_rate[demod]) stv0900_search_srate_fine()
1565 stv0900_write_reg(intp, DMDISTATE, 0x1f); stv0900_search_srate_fine()
1566 stv0900_write_reg(intp, TMGCFG2, 0xc1); stv0900_search_srate_fine()
1567 stv0900_write_reg(intp, TMGTHRISE, 0x20); stv0900_search_srate_fine()
1568 stv0900_write_reg(intp, TMGTHFALL, 0x00); stv0900_search_srate_fine()
1569 stv0900_write_reg(intp, TMGCFG, 0xd2); stv0900_search_srate_fine()
1570 stv0900_write_bits(intp, CFR_AUTOSCAN, 0); stv0900_search_srate_fine()
1571 stv0900_write_reg(intp, AGC2REF, 0x38); stv0900_search_srate_fine()
1573 if (intp->chip_id >= 0x30) stv0900_search_srate_fine()
1574 stv0900_write_reg(intp, CARFREQ, 0x79); stv0900_search_srate_fine()
1575 else if (intp->chip_id >= 0x20) stv0900_search_srate_fine()
1576 stv0900_write_reg(intp, CARFREQ, 0x49); stv0900_search_srate_fine()
1578 stv0900_write_reg(intp, CARFREQ, 0xed); stv0900_search_srate_fine()
1580 stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f); stv0900_search_srate_fine()
1581 stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff)); stv0900_search_srate_fine()
1583 stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f); stv0900_search_srate_fine()
1584 stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff)); stv0900_search_srate_fine()
1586 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff); stv0900_search_srate_fine()
1587 stv0900_write_reg(intp, SFRINIT0, (symb & 0xff)); stv0900_search_srate_fine()
1589 stv0900_write_reg(intp, DMDT0M, 0x20); stv0900_search_srate_fine()
1590 stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff); stv0900_search_srate_fine()
1591 stv0900_write_reg(intp, CFRINIT0, coarse_freq & 0xff); stv0900_search_srate_fine()
1592 stv0900_write_reg(intp, DMDISTATE, 0x15); stv0900_search_srate_fine()
1601 struct stv0900_internal *intp = state->internal; stv0900_blind_search_algo() local
1620 if (intp->chip_id < 0x20) { stv0900_blind_search_algo()
1628 if (intp->chip_id <= 0x20) stv0900_blind_search_algo()
1633 agc2_int = stv0900_blind_check_agc2_min_level(intp, demod); stv0900_blind_search_algo()
1639 if (intp->chip_id == 0x10) stv0900_blind_search_algo()
1640 stv0900_write_reg(intp, CORRELEXP, 0xaa); stv0900_blind_search_algo()
1642 if (intp->chip_id < 0x20) stv0900_blind_search_algo()
1643 stv0900_write_reg(intp, CARHDR, 0x55); stv0900_blind_search_algo()
1645 stv0900_write_reg(intp, CARHDR, 0x20); stv0900_blind_search_algo()
1647 if (intp->chip_id <= 0x20) stv0900_blind_search_algo()
1648 stv0900_write_reg(intp, CARCFG, 0xc4); stv0900_blind_search_algo()
1650 stv0900_write_reg(intp, CARCFG, 0x6); stv0900_blind_search_algo()
1652 stv0900_write_reg(intp, RTCS2, 0x44); stv0900_blind_search_algo()
1654 if (intp->chip_id >= 0x20) { stv0900_blind_search_algo()
1655 stv0900_write_reg(intp, EQUALCFG, 0x41); stv0900_blind_search_algo()
1656 stv0900_write_reg(intp, FFECFG, 0x41); stv0900_blind_search_algo()
1657 stv0900_write_reg(intp, VITSCALE, 0x82); stv0900_blind_search_algo()
1658 stv0900_write_reg(intp, VAVSRVIT, 0x0); stv0900_blind_search_algo()
1664 stv0900_write_reg(intp, KREFTMG, k_ref_tmg); stv0900_blind_search_algo()
1673 lock = stv0900_get_demod_lock(intp, stv0900_blind_search_algo()
1683 agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8) stv0900_blind_search_algo()
1684 | stv0900_read_reg(intp, AGC2I0); stv0900_blind_search_algo()
1689 dstatus2 = stv0900_read_reg(intp, DSTATUS2); stv0900_blind_search_algo()
1709 static void stv0900_set_viterbi_acq(struct stv0900_internal *intp, stv0900_set_viterbi_acq() argument
1716 stv0900_write_reg(intp, vth_reg++, 0x96); stv0900_set_viterbi_acq()
1717 stv0900_write_reg(intp, vth_reg++, 0x64); stv0900_set_viterbi_acq()
1718 stv0900_write_reg(intp, vth_reg++, 0x36); stv0900_set_viterbi_acq()
1719 stv0900_write_reg(intp, vth_reg++, 0x23); stv0900_set_viterbi_acq()
1720 stv0900_write_reg(intp, vth_reg++, 0x1e); stv0900_set_viterbi_acq()
1721 stv0900_write_reg(intp, vth_reg++, 0x19); stv0900_set_viterbi_acq()
1724 static void stv0900_set_search_standard(struct stv0900_internal *intp, stv0900_set_search_standard() argument
1730 switch (intp->srch_standard[demod]) { stv0900_set_search_standard()
1746 switch (intp->srch_standard[demod]) { stv0900_set_search_standard()
1749 stv0900_write_bits(intp, DVBS1_ENABLE, 1); stv0900_set_search_standard()
1750 stv0900_write_bits(intp, DVBS2_ENABLE, 0); stv0900_set_search_standard()
1751 stv0900_write_bits(intp, STOP_CLKVIT, 0); stv0900_set_search_standard()
1752 stv0900_set_dvbs1_track_car_loop(intp, stv0900_set_search_standard()
1754 intp->symbol_rate[demod]); stv0900_set_search_standard()
1755 stv0900_write_reg(intp, CAR2CFG, 0x22); stv0900_set_search_standard()
1757 stv0900_set_viterbi_acq(intp, demod); stv0900_set_search_standard()
1758 stv0900_set_viterbi_standard(intp, stv0900_set_search_standard()
1759 intp->srch_standard[demod], stv0900_set_search_standard()
1760 intp->fec[demod], demod); stv0900_set_search_standard()
1764 stv0900_write_bits(intp, DVBS1_ENABLE, 0); stv0900_set_search_standard()
1765 stv0900_write_bits(intp, DVBS2_ENABLE, 1); stv0900_set_search_standard()
1766 stv0900_write_bits(intp, STOP_CLKVIT, 1); stv0900_set_search_standard()
1767 stv0900_write_reg(intp, ACLC, 0x1a); stv0900_set_search_standard()
1768 stv0900_write_reg(intp, BCLC, 0x09); stv0900_set_search_standard()
1769 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/ stv0900_set_search_standard()
1770 stv0900_write_reg(intp, CAR2CFG, 0x26); stv0900_set_search_standard()
1772 stv0900_write_reg(intp, CAR2CFG, 0x66); stv0900_set_search_standard()
1774 if (intp->demod_mode != STV0900_SINGLE) { stv0900_set_search_standard()
1775 if (intp->chip_id <= 0x11) stv0900_set_search_standard()
1776 stv0900_stop_all_s2_modcod(intp, demod); stv0900_set_search_standard()
1778 stv0900_activate_s2_modcod(intp, demod); stv0900_set_search_standard()
1781 stv0900_activate_s2_modcod_single(intp, demod); stv0900_set_search_standard()
1783 stv0900_set_viterbi_tracq(intp, demod); stv0900_set_search_standard()
1788 stv0900_write_bits(intp, DVBS1_ENABLE, 1); stv0900_set_search_standard()
1789 stv0900_write_bits(intp, DVBS2_ENABLE, 1); stv0900_set_search_standard()
1790 stv0900_write_bits(intp, STOP_CLKVIT, 0); stv0900_set_search_standard()
1791 stv0900_write_reg(intp, ACLC, 0x1a); stv0900_set_search_standard()
1792 stv0900_write_reg(intp, BCLC, 0x09); stv0900_set_search_standard()
1793 stv0900_set_dvbs1_track_car_loop(intp, stv0900_set_search_standard()
1795 intp->symbol_rate[demod]); stv0900_set_search_standard()
1796 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/ stv0900_set_search_standard()
1797 stv0900_write_reg(intp, CAR2CFG, 0x26); stv0900_set_search_standard()
1799 stv0900_write_reg(intp, CAR2CFG, 0x66); stv0900_set_search_standard()
1801 if (intp->demod_mode != STV0900_SINGLE) { stv0900_set_search_standard()
1802 if (intp->chip_id <= 0x11) stv0900_set_search_standard()
1803 stv0900_stop_all_s2_modcod(intp, demod); stv0900_set_search_standard()
1805 stv0900_activate_s2_modcod(intp, demod); stv0900_set_search_standard()
1808 stv0900_activate_s2_modcod_single(intp, demod); stv0900_set_search_standard()
1810 stv0900_set_viterbi_tracq(intp, demod); stv0900_set_search_standard()
1811 stv0900_set_viterbi_standard(intp, stv0900_set_search_standard()
1812 intp->srch_standard[demod], stv0900_set_search_standard()
1813 intp->fec[demod], demod); stv0900_set_search_standard()
1822 struct stv0900_internal *intp = state->internal; stv0900_algo() local
1836 algo = intp->srch_algo[demod]; stv0900_algo()
1837 stv0900_write_bits(intp, RST_HWARE, 1); stv0900_algo()
1838 stv0900_write_reg(intp, DMDISTATE, 0x5c); stv0900_algo()
1839 if (intp->chip_id >= 0x20) { stv0900_algo()
1840 if (intp->symbol_rate[demod] > 5000000) stv0900_algo()
1841 stv0900_write_reg(intp, CORRELABS, 0x9e); stv0900_algo()
1843 stv0900_write_reg(intp, CORRELABS, 0x82); stv0900_algo()
1845 stv0900_write_reg(intp, CORRELABS, 0x88); stv0900_algo()
1848 intp->symbol_rate[demod], stv0900_algo()
1849 intp->srch_algo[demod]); stv0900_algo()
1851 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) { stv0900_algo()
1852 intp->bw[demod] = 2 * 36000000; stv0900_algo()
1854 stv0900_write_reg(intp, TMGCFG2, 0xc0); stv0900_algo()
1855 stv0900_write_reg(intp, CORRELMANT, 0x70); stv0900_algo()
1857 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod); stv0900_algo()
1859 stv0900_write_reg(intp, DMDT0M, 0x20); stv0900_algo()
1860 stv0900_write_reg(intp, TMGCFG, 0xd2); stv0900_algo()
1862 if (intp->symbol_rate[demod] < 2000000) stv0900_algo()
1863 stv0900_write_reg(intp, CORRELMANT, 0x63); stv0900_algo()
1865 stv0900_write_reg(intp, CORRELMANT, 0x70); stv0900_algo()
1867 stv0900_write_reg(intp, AGC2REF, 0x38); stv0900_algo()
1869 intp->bw[demod] = stv0900_algo()
1870 stv0900_carrier_width(intp->symbol_rate[demod], stv0900_algo()
1871 intp->rolloff); stv0900_algo()
1872 if (intp->chip_id >= 0x20) { stv0900_algo()
1873 stv0900_write_reg(intp, KREFTMG, 0x5a); stv0900_algo()
1875 if (intp->srch_algo[demod] == STV0900_COLD_START) { stv0900_algo()
1876 intp->bw[demod] += 10000000; stv0900_algo()
1877 intp->bw[demod] *= 15; stv0900_algo()
1878 intp->bw[demod] /= 10; stv0900_algo()
1879 } else if (intp->srch_algo[demod] == STV0900_WARM_START) stv0900_algo()
1880 intp->bw[demod] += 10000000; stv0900_algo()
1883 stv0900_write_reg(intp, KREFTMG, 0xc1); stv0900_algo()
1884 intp->bw[demod] += 10000000; stv0900_algo()
1885 intp->bw[demod] *= 15; stv0900_algo()
1886 intp->bw[demod] /= 10; stv0900_algo()
1889 stv0900_write_reg(intp, TMGCFG2, 0xc1); stv0900_algo()
1891 stv0900_set_symbol_rate(intp, intp->mclk, stv0900_algo()
1892 intp->symbol_rate[demod], demod); stv0900_algo()
1893 stv0900_set_max_symbol_rate(intp, intp->mclk, stv0900_algo()
1894 intp->symbol_rate[demod], demod); stv0900_algo()
1895 stv0900_set_min_symbol_rate(intp, intp->mclk, stv0900_algo()
1896 intp->symbol_rate[demod], demod); stv0900_algo()
1897 if (intp->symbol_rate[demod] >= 10000000) stv0900_algo()
1904 if (intp->tuner_type[demod] == 3) stv0900_algo()
1905 stv0900_set_tuner_auto(intp, intp->freq[demod], stv0900_algo()
1906 intp->bw[demod], demod); stv0900_algo()
1908 stv0900_set_tuner(fe, intp->freq[demod], intp->bw[demod]); stv0900_algo()
1910 agc1_power = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1), stv0900_algo()
1911 stv0900_get_bits(intp, AGCIQ_VALUE0)); stv0900_algo()
1917 aq_power += (stv0900_get_bits(intp, POWER_I) + stv0900_algo()
1918 stv0900_get_bits(intp, POWER_Q)) / 2; stv0900_algo()
1924 intp->result[demod].locked = FALSE; stv0900_algo()
1928 stv0900_write_bits(intp, SPECINV_CONTROL, stv0900_algo()
1929 intp->srch_iq_inv[demod]); stv0900_algo()
1930 if (intp->chip_id <= 0x20) /*cut 2.0*/ stv0900_algo()
1931 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1); stv0900_algo()
1933 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 1); stv0900_algo()
1935 stv0900_set_search_standard(intp, demod); stv0900_algo()
1937 if (intp->srch_algo[demod] != STV0900_BLIND_SEARCH) stv0900_algo()
1938 stv0900_start_search(intp, demod); stv0900_algo()
1944 if (intp->chip_id == 0x12) { stv0900_algo()
1945 stv0900_write_bits(intp, RST_HWARE, 0); stv0900_algo()
1947 stv0900_write_bits(intp, RST_HWARE, 1); stv0900_algo()
1948 stv0900_write_bits(intp, RST_HWARE, 0); stv0900_algo()
1956 lock = stv0900_get_demod_lock(intp, demod, demod_timeout); stv0900_algo()
1960 if (stv0900_check_timing_lock(intp, demod) == TRUE) stv0900_algo()
1961 lock = stv0900_sw_algo(intp, demod); stv0900_algo()
1970 if (intp->chip_id <= 0x11) { stv0900_algo()
1976 stv0900_write_bits(intp, RST_HWARE, 0); stv0900_algo()
1978 stv0900_write_bits(intp, RST_HWARE, 0); stv0900_algo()
1980 stv0900_write_bits(intp, RST_HWARE, 1); stv0900_algo()
1981 stv0900_write_bits(intp, RST_HWARE, 0); stv0900_algo()
1984 } else if (intp->chip_id >= 0x20) { stv0900_algo()
1985 stv0900_write_bits(intp, RST_HWARE, 0); stv0900_algo()
1987 stv0900_write_bits(intp, RST_HWARE, 1); stv0900_algo()
1988 stv0900_write_bits(intp, RST_HWARE, 0); stv0900_algo()
1991 if (stv0900_wait_for_lock(intp, demod, stv0900_algo()
1994 intp->result[demod].locked = TRUE; stv0900_algo()
1995 if (intp->result[demod].standard == stv0900_algo()
1997 stv0900_set_dvbs2_rolloff(intp, demod); stv0900_algo()
1998 stv0900_write_bits(intp, RESET_UPKO_COUNT, 1); stv0900_algo()
1999 stv0900_write_bits(intp, RESET_UPKO_COUNT, 0); stv0900_algo()
2000 stv0900_write_reg(intp, ERRCTRL1, 0x67); stv0900_algo()
2002 stv0900_write_reg(intp, ERRCTRL1, 0x75); stv0900_algo()
2005 stv0900_write_reg(intp, FBERCPT4, 0); stv0900_algo()
2006 stv0900_write_reg(intp, ERRCTRL2, 0xc1); stv0900_algo()
2010 no_signal = stv0900_check_signal_presence(intp, demod); stv0900_algo()
2012 intp->result[demod].locked = FALSE; stv0900_algo()
2019 if (intp->chip_id > 0x11) { stv0900_algo()
2020 intp->result[demod].locked = FALSE; stv0900_algo()
2024 if ((stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) && stv0900_algo()
2025 (intp->srch_iq_inv[demod] <= STV0900_IQ_AUTO_NORMAL_FIRST)) stv0900_algo()
|
| H A D | stv0900_core.c | 132 void stv0900_write_reg(struct stv0900_internal *intp, u16 reg_addr, stv0900_write_reg() argument
138 .addr = intp->i2c_addr, stv0900_write_reg()
148 ret = i2c_transfer(intp->i2c_adap, &i2cmsg, 1); stv0900_write_reg()
153 u8 stv0900_read_reg(struct stv0900_internal *intp, u16 reg) stv0900_read_reg() argument
160 .addr = intp->i2c_addr, stv0900_read_reg()
165 .addr = intp->i2c_addr, stv0900_read_reg()
172 ret = i2c_transfer(intp->i2c_adap, msg, 2); stv0900_read_reg()
194 void stv0900_write_bits(struct stv0900_internal *intp, u32 label, u8 val) stv0900_write_bits() argument
198 reg = stv0900_read_reg(intp, (label >> 16) & 0xffff); stv0900_write_bits()
204 stv0900_write_reg(intp, (label >> 16) & 0xffff, reg); stv0900_write_bits()
208 u8 stv0900_get_bits(struct stv0900_internal *intp, u32 label) stv0900_get_bits() argument
215 val = stv0900_read_reg(intp, label >> 16); stv0900_get_bits()
221 static enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *intp) stv0900_initialize() argument
225 if (intp == NULL) stv0900_initialize()
228 intp->chip_id = stv0900_read_reg(intp, R0900_MID); stv0900_initialize()
230 if (intp->errs != STV0900_NO_ERROR) stv0900_initialize()
231 return intp->errs; stv0900_initialize()
234 stv0900_write_reg(intp, R0900_P1_DMDISTATE, 0x5c); stv0900_initialize()
235 stv0900_write_reg(intp, R0900_P2_DMDISTATE, 0x5c); stv0900_initialize()
237 stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x6c); stv0900_initialize()
238 stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x6f); stv0900_initialize()
239 stv0900_write_reg(intp, R0900_P1_I2CRPT, 0x20); stv0900_initialize()
240 stv0900_write_reg(intp, R0900_P2_I2CRPT, 0x20); stv0900_initialize()
241 stv0900_write_reg(intp, R0900_NCOARSE, 0x13); stv0900_initialize()
243 stv0900_write_reg(intp, R0900_I2CCFG, 0x08); stv0900_initialize()
245 switch (intp->clkmode) { stv0900_initialize()
248 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 stv0900_initialize()
249 | intp->clkmode); stv0900_initialize()
253 i = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL); stv0900_initialize()
254 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | i); stv0900_initialize()
260 stv0900_write_reg(intp, STV0900_InitVal[i][0], stv0900_initialize()
263 if (stv0900_read_reg(intp, R0900_MID) >= 0x20) { stv0900_initialize()
264 stv0900_write_reg(intp, R0900_TSGENERAL, 0x0c); stv0900_initialize()
266 stv0900_write_reg(intp, STV0900_Cut20_AddOnVal[i][0], stv0900_initialize()
270 stv0900_write_reg(intp, R0900_P1_FSPYCFG, 0x6c); stv0900_initialize()
271 stv0900_write_reg(intp, R0900_P2_FSPYCFG, 0x6c); stv0900_initialize()
273 stv0900_write_reg(intp, R0900_P1_PDELCTRL2, 0x01); stv0900_initialize()
274 stv0900_write_reg(intp, R0900_P2_PDELCTRL2, 0x21); stv0900_initialize()
276 stv0900_write_reg(intp, R0900_P1_PDELCTRL3, 0x20); stv0900_initialize()
277 stv0900_write_reg(intp, R0900_P2_PDELCTRL3, 0x20); stv0900_initialize()
279 stv0900_write_reg(intp, R0900_TSTRES0, 0x80); stv0900_initialize()
280 stv0900_write_reg(intp, R0900_TSTRES0, 0x00); stv0900_initialize()
285 static u32 stv0900_get_mclk_freq(struct stv0900_internal *intp, u32 ext_clk) stv0900_get_mclk_freq() argument
289 div = stv0900_get_bits(intp, F0900_M_DIV); stv0900_get_mclk_freq()
290 ad_div = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6); stv0900_get_mclk_freq()
299 static enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *intp, u32 mclk) stv0900_set_mclk() argument
303 if (intp == NULL) stv0900_set_mclk()
306 if (intp->errs) stv0900_set_mclk()
310 intp->quartz); stv0900_set_mclk()
312 clk_sel = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6); stv0900_set_mclk()
313 m_div = ((clk_sel * mclk) / intp->quartz) - 1; stv0900_set_mclk()
314 stv0900_write_bits(intp, F0900_M_DIV, m_div); stv0900_set_mclk()
315 intp->mclk = stv0900_get_mclk_freq(intp, stv0900_set_mclk()
316 intp->quartz); stv0900_set_mclk()
324 m_div = intp->mclk / 704000; stv0900_set_mclk()
325 stv0900_write_reg(intp, R0900_P1_F22TX, m_div); stv0900_set_mclk()
326 stv0900_write_reg(intp, R0900_P1_F22RX, m_div); stv0900_set_mclk()
328 stv0900_write_reg(intp, R0900_P2_F22TX, m_div); stv0900_set_mclk()
329 stv0900_write_reg(intp, R0900_P2_F22RX, m_div); stv0900_set_mclk()
331 if ((intp->errs)) stv0900_set_mclk()
337 static u32 stv0900_get_err_count(struct stv0900_internal *intp, int cntr, stv0900_get_err_count() argument
345 hsb = stv0900_get_bits(intp, ERR_CNT12); stv0900_get_err_count()
346 msb = stv0900_get_bits(intp, ERR_CNT11); stv0900_get_err_count()
347 lsb = stv0900_get_bits(intp, ERR_CNT10); stv0900_get_err_count()
350 hsb = stv0900_get_bits(intp, ERR_CNT22); stv0900_get_err_count()
351 msb = stv0900_get_bits(intp, ERR_CNT21); stv0900_get_err_count()
352 lsb = stv0900_get_bits(intp, ERR_CNT20); stv0900_get_err_count()
364 struct stv0900_internal *intp = state->internal; stv0900_i2c_gate_ctrl() local
367 stv0900_write_bits(intp, I2CT_ON, enable); stv0900_i2c_gate_ctrl()
372 static void stv0900_set_ts_parallel_serial(struct stv0900_internal *intp, stv0900_set_ts_parallel_serial() argument
379 if (intp->chip_id >= 0x20) { stv0900_set_ts_parallel_serial()
387 stv0900_write_reg(intp, R0900_TSGENERAL, stv0900_set_ts_parallel_serial()
392 stv0900_write_reg(intp, R0900_TSGENERAL, stv0900_set_ts_parallel_serial()
394 stv0900_write_bits(intp, stv0900_set_ts_parallel_serial()
396 stv0900_write_bits(intp, stv0900_set_ts_parallel_serial()
398 stv0900_write_reg(intp, stv0900_set_ts_parallel_serial()
400 stv0900_write_reg(intp, stv0900_set_ts_parallel_serial()
412 stv0900_write_reg(intp, stv0900_set_ts_parallel_serial()
417 stv0900_write_reg(intp, stv0900_set_ts_parallel_serial()
432 stv0900_write_reg(intp, R0900_TSGENERAL1X, stv0900_set_ts_parallel_serial()
437 stv0900_write_reg(intp, R0900_TSGENERAL1X, stv0900_set_ts_parallel_serial()
439 stv0900_write_bits(intp, stv0900_set_ts_parallel_serial()
441 stv0900_write_bits(intp, stv0900_set_ts_parallel_serial()
443 stv0900_write_reg(intp, R0900_P1_TSSPEED, stv0900_set_ts_parallel_serial()
445 stv0900_write_reg(intp, R0900_P2_TSSPEED, stv0900_set_ts_parallel_serial()
458 stv0900_write_reg(intp, R0900_TSGENERAL1X, stv0900_set_ts_parallel_serial()
463 stv0900_write_reg(intp, R0900_TSGENERAL1X, stv0900_set_ts_parallel_serial()
475 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00); stv0900_set_ts_parallel_serial()
476 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00); stv0900_set_ts_parallel_serial()
479 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00); stv0900_set_ts_parallel_serial()
480 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01); stv0900_set_ts_parallel_serial()
483 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01); stv0900_set_ts_parallel_serial()
484 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00); stv0900_set_ts_parallel_serial()
487 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01); stv0900_set_ts_parallel_serial()
488 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01); stv0900_set_ts_parallel_serial()
496 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00); stv0900_set_ts_parallel_serial()
497 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00); stv0900_set_ts_parallel_serial()
500 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00); stv0900_set_ts_parallel_serial()
501 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01); stv0900_set_ts_parallel_serial()
504 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01); stv0900_set_ts_parallel_serial()
505 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00); stv0900_set_ts_parallel_serial()
508 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01); stv0900_set_ts_parallel_serial()
509 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01); stv0900_set_ts_parallel_serial()
515 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1); stv0900_set_ts_parallel_serial()
516 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0); stv0900_set_ts_parallel_serial()
517 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1); stv0900_set_ts_parallel_serial()
518 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0); stv0900_set_ts_parallel_serial()
564 u32 stv0900_get_freq_auto(struct stv0900_internal *intp, int demod) stv0900_get_freq_auto() argument
572 freq = (stv0900_get_bits(intp, TUN_RFFREQ2) << 10) + stv0900_get_freq_auto()
573 (stv0900_get_bits(intp, TUN_RFFREQ1) << 2) + stv0900_get_freq_auto()
574 stv0900_get_bits(intp, TUN_RFFREQ0); stv0900_get_freq_auto()
578 round = (stv0900_get_bits(intp, TUN_RFRESTE1) >> 2) + stv0900_get_freq_auto()
579 stv0900_get_bits(intp, TUN_RFRESTE0); stv0900_get_freq_auto()
586 void stv0900_set_tuner_auto(struct stv0900_internal *intp, u32 Frequency, stv0900_set_tuner_auto() argument
595 stv0900_write_bits(intp, TUN_RFFREQ2, (tunerFrequency >> 10)); stv0900_set_tuner_auto()
596 stv0900_write_bits(intp, TUN_RFFREQ1, (tunerFrequency >> 2) & 0xff); stv0900_set_tuner_auto()
597 stv0900_write_bits(intp, TUN_RFFREQ0, (tunerFrequency & 0x03)); stv0900_set_tuner_auto()
599 stv0900_write_bits(intp, TUN_BW, Bandwidth / 2000000); stv0900_set_tuner_auto()
601 stv0900_write_reg(intp, TNRLD, 1); stv0900_set_tuner_auto()
604 static s32 stv0900_get_rf_level(struct stv0900_internal *intp, stv0900_get_rf_level() argument
619 agc_gain = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1), stv0900_get_rf_level()
620 stv0900_get_bits(intp, AGCIQ_VALUE0)); stv0900_get_rf_level()
676 struct stv0900_internal *intp = state->internal; stv0900_carr_get_quality() local
697 if (stv0900_get_bits(intp, LOCK_DEFINITIF)) { stv0900_carr_get_quality()
702 regval += MAKEWORD(stv0900_get_bits(intp, stv0900_carr_get_quality()
704 stv0900_get_bits(intp, stv0900_carr_get_quality()
742 struct stv0900_internal *intp = state->internal; stv0900_read_ucblocks() local
752 err_val1 = stv0900_read_reg(intp, BBFCRCKO1); stv0900_read_ucblocks()
753 err_val0 = stv0900_read_reg(intp, BBFCRCKO0); stv0900_read_ucblocks()
757 err_val1 = stv0900_read_reg(intp, UPCRCKO1); stv0900_read_ucblocks()
758 err_val0 = stv0900_read_reg(intp, UPCRCKO0); stv0900_read_ucblocks()
782 static u32 stv0900_get_ber(struct stv0900_internal *intp, stv0900_get_ber() argument
788 demod_state = stv0900_get_bits(intp, HEADER_MODE); stv0900_get_ber()
800 ber += stv0900_get_err_count(intp, 0, demod); stv0900_get_ber()
804 if (stv0900_get_bits(intp, PRFVIT)) { stv0900_get_ber()
814 ber += stv0900_get_err_count(intp, 0, demod); stv0900_get_ber()
818 if (stv0900_get_bits(intp, PKTDELIN_LOCK)) { stv0900_get_ber()
839 int stv0900_get_demod_lock(struct stv0900_internal *intp, stv0900_get_demod_lock() argument
848 dmd_state = stv0900_get_bits(intp, HEADER_MODE); stv0900_get_demod_lock()
858 lock = stv0900_get_bits(intp, LOCK_DEFINITIF); stv0900_get_demod_lock()
876 void stv0900_stop_all_s2_modcod(struct stv0900_internal *intp, stv0900_stop_all_s2_modcod() argument
887 stv0900_write_reg(intp, regflist + i, 0xff); stv0900_stop_all_s2_modcod()
890 void stv0900_activate_s2_modcod(struct stv0900_internal *intp, stv0900_activate_s2_modcod() argument
901 if (intp->chip_id <= 0x11) { stv0900_activate_s2_modcod()
904 mod_code = stv0900_read_reg(intp, PLHMODCOD); stv0900_activate_s2_modcod()
930 stv0900_write_reg(intp, reg_index, stv0900_activate_s2_modcod()
933 stv0900_write_reg(intp, reg_index, stv0900_activate_s2_modcod()
937 } else if (intp->chip_id >= 0x12) { stv0900_activate_s2_modcod()
939 stv0900_write_reg(intp, MODCODLST0 + reg_index, 0xff); stv0900_activate_s2_modcod()
941 stv0900_write_reg(intp, MODCODLSTE, 0xff); stv0900_activate_s2_modcod()
942 stv0900_write_reg(intp, MODCODLSTF, 0xcf); stv0900_activate_s2_modcod()
944 stv0900_write_reg(intp, MODCODLST7 + reg_index, 0xcc); stv0900_activate_s2_modcod()
950 void stv0900_activate_s2_modcod_single(struct stv0900_internal *intp, stv0900_activate_s2_modcod_single() argument
957 stv0900_write_reg(intp, MODCODLST0, 0xff); stv0900_activate_s2_modcod_single()
958 stv0900_write_reg(intp, MODCODLST1, 0xf0); stv0900_activate_s2_modcod_single()
959 stv0900_write_reg(intp, MODCODLSTF, 0x0f); stv0900_activate_s2_modcod_single()
961 stv0900_write_reg(intp, MODCODLST2 + reg_index, 0); stv0900_activate_s2_modcod_single()
970 void stv0900_start_search(struct stv0900_internal *intp, stv0900_start_search() argument
976 stv0900_write_bits(intp, DEMOD_MODE, 0x1f); stv0900_start_search()
977 if (intp->chip_id == 0x10) stv0900_start_search()
978 stv0900_write_reg(intp, CORRELEXP, 0xaa); stv0900_start_search()
980 if (intp->chip_id < 0x20) stv0900_start_search()
981 stv0900_write_reg(intp, CARHDR, 0x55); stv0900_start_search()
983 if (intp->chip_id <= 0x20) { stv0900_start_search()
984 if (intp->symbol_rate[0] <= 5000000) { stv0900_start_search()
985 stv0900_write_reg(intp, CARCFG, 0x44); stv0900_start_search()
986 stv0900_write_reg(intp, CFRUP1, 0x0f); stv0900_start_search()
987 stv0900_write_reg(intp, CFRUP0, 0xff); stv0900_start_search()
988 stv0900_write_reg(intp, CFRLOW1, 0xf0); stv0900_start_search()
989 stv0900_write_reg(intp, CFRLOW0, 0x00); stv0900_start_search()
990 stv0900_write_reg(intp, RTCS2, 0x68); stv0900_start_search()
992 stv0900_write_reg(intp, CARCFG, 0xc4); stv0900_start_search()
993 stv0900_write_reg(intp, RTCS2, 0x44); stv0900_start_search()
997 if (intp->symbol_rate[demod] <= 5000000) stv0900_start_search()
998 stv0900_write_reg(intp, RTCS2, 0x68); stv0900_start_search()
1000 stv0900_write_reg(intp, RTCS2, 0x44); stv0900_start_search()
1002 stv0900_write_reg(intp, CARCFG, 0x46); stv0900_start_search()
1003 if (intp->srch_algo[demod] == STV0900_WARM_START) { stv0900_start_search()
1005 freq /= (intp->mclk / 1000); stv0900_start_search()
1008 freq = (intp->srch_range[demod] / 2000); stv0900_start_search()
1009 if (intp->symbol_rate[demod] <= 5000000) stv0900_start_search()
1015 freq /= (intp->mclk / 1000); stv0900_start_search()
1019 stv0900_write_bits(intp, CFR_UP1, MSB(freq_s16)); stv0900_start_search()
1020 stv0900_write_bits(intp, CFR_UP0, LSB(freq_s16)); stv0900_start_search()
1022 stv0900_write_bits(intp, CFR_LOW1, MSB(freq_s16)); stv0900_start_search()
1023 stv0900_write_bits(intp, CFR_LOW0, LSB(freq_s16)); stv0900_start_search()
1026 stv0900_write_reg(intp, CFRINIT1, 0); stv0900_start_search()
1027 stv0900_write_reg(intp, CFRINIT0, 0); stv0900_start_search()
1029 if (intp->chip_id >= 0x20) { stv0900_start_search()
1030 stv0900_write_reg(intp, EQUALCFG, 0x41); stv0900_start_search()
1031 stv0900_write_reg(intp, FFECFG, 0x41); stv0900_start_search()
1033 if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) || stv0900_start_search()
1034 (intp->srch_standard[demod] == STV0900_SEARCH_DSS) || stv0900_start_search()
1035 (intp->srch_standard[demod] == STV0900_AUTO_SEARCH)) { stv0900_start_search()
1036 stv0900_write_reg(intp, VITSCALE, stv0900_start_search()
1038 stv0900_write_reg(intp, VAVSRVIT, 0x0); stv0900_start_search()
1042 stv0900_write_reg(intp, SFRSTEP, 0x00); stv0900_start_search()
1043 stv0900_write_reg(intp, TMGTHRISE, 0xe0); stv0900_start_search()
1044 stv0900_write_reg(intp, TMGTHFALL, 0xc0); stv0900_start_search()
1045 stv0900_write_bits(intp, SCAN_ENABLE, 0); stv0900_start_search()
1046 stv0900_write_bits(intp, CFR_AUTOSCAN, 0); stv0900_start_search()
1047 stv0900_write_bits(intp, S1S2_SEQUENTIAL, 0); stv0900_start_search()
1048 stv0900_write_reg(intp, RTC, 0x88); stv0900_start_search()
1049 if (intp->chip_id >= 0x20) { stv0900_start_search()
1050 if (intp->symbol_rate[demod] < 2000000) { stv0900_start_search()
1051 if (intp->chip_id <= 0x20) stv0900_start_search()
1052 stv0900_write_reg(intp, CARFREQ, 0x39); stv0900_start_search()
1054 stv0900_write_reg(intp, CARFREQ, 0x89); stv0900_start_search()
1056 stv0900_write_reg(intp, CARHDR, 0x40); stv0900_start_search()
1057 } else if (intp->symbol_rate[demod] < 10000000) { stv0900_start_search()
1058 stv0900_write_reg(intp, CARFREQ, 0x4c); stv0900_start_search()
1059 stv0900_write_reg(intp, CARHDR, 0x20); stv0900_start_search()
1061 stv0900_write_reg(intp, CARFREQ, 0x4b); stv0900_start_search()
1062 stv0900_write_reg(intp, CARHDR, 0x20); stv0900_start_search()
1066 if (intp->symbol_rate[demod] < 10000000) stv0900_start_search()
1067 stv0900_write_reg(intp, CARFREQ, 0xef); stv0900_start_search()
1069 stv0900_write_reg(intp, CARFREQ, 0xed); stv0900_start_search()
1072 switch (intp->srch_algo[demod]) { stv0900_start_search()
1074 stv0900_write_reg(intp, DMDISTATE, 0x1f); stv0900_start_search()
1075 stv0900_write_reg(intp, DMDISTATE, 0x18); stv0900_start_search()
1078 stv0900_write_reg(intp, DMDISTATE, 0x1f); stv0900_start_search()
1079 stv0900_write_reg(intp, DMDISTATE, 0x15); stv0900_start_search()
1269 enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *intp, stv0900_st_dvbs2_single() argument
1280 if ((intp->demod_mode != STV0900_DUAL) stv0900_st_dvbs2_single()
1281 || (stv0900_get_bits(intp, F0900_DDEMOD) != 1)) { stv0900_st_dvbs2_single()
1282 stv0900_write_reg(intp, R0900_GENCFG, 0x1d); stv0900_st_dvbs2_single()
1284 intp->demod_mode = STV0900_DUAL; stv0900_st_dvbs2_single()
1286 stv0900_write_bits(intp, F0900_FRESFEC, 1); stv0900_st_dvbs2_single()
1287 stv0900_write_bits(intp, F0900_FRESFEC, 0); stv0900_st_dvbs2_single()
1290 stv0900_write_reg(intp, stv0900_st_dvbs2_single()
1294 stv0900_write_reg(intp, stv0900_st_dvbs2_single()
1298 stv0900_write_reg(intp, R0900_P1_MODCODLSTE, 0xff); stv0900_st_dvbs2_single()
1299 stv0900_write_reg(intp, R0900_P1_MODCODLSTF, 0xcf); stv0900_st_dvbs2_single()
1302 stv0900_write_reg(intp, stv0900_st_dvbs2_single()
1306 stv0900_write_reg(intp, stv0900_st_dvbs2_single()
1310 stv0900_write_reg(intp, R0900_P2_MODCODLSTE, 0xff); stv0900_st_dvbs2_single()
1311 stv0900_write_reg(intp, R0900_P2_MODCODLSTF, 0xcf); stv0900_st_dvbs2_single()
1317 stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_1); stv0900_st_dvbs2_single()
1318 stv0900_activate_s2_modcod_single(intp, stv0900_st_dvbs2_single()
1320 stv0900_write_reg(intp, R0900_GENCFG, 0x06); stv0900_st_dvbs2_single()
1322 stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_2); stv0900_st_dvbs2_single()
1323 stv0900_activate_s2_modcod_single(intp, stv0900_st_dvbs2_single()
1325 stv0900_write_reg(intp, R0900_GENCFG, 0x04); stv0900_st_dvbs2_single()
1328 intp->demod_mode = STV0900_SINGLE; stv0900_st_dvbs2_single()
1330 stv0900_write_bits(intp, F0900_FRESFEC, 1); stv0900_st_dvbs2_single()
1331 stv0900_write_bits(intp, F0900_FRESFEC, 0); stv0900_st_dvbs2_single()
1332 stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 1); stv0900_st_dvbs2_single()
1333 stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 0); stv0900_st_dvbs2_single()
1334 stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 1); stv0900_st_dvbs2_single()
1335 stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 0); stv0900_st_dvbs2_single()
1348 struct stv0900_internal *intp = NULL; stv0900_init_internal() local
1397 intp = state->internal; stv0900_init_internal()
1399 intp->demod_mode = p_init->demod_mode; stv0900_init_internal()
1400 stv0900_st_dvbs2_single(intp, intp->demod_mode, STV0900_DEMOD_1); stv0900_init_internal()
1401 intp->chip_id = stv0900_read_reg(intp, R0900_MID); stv0900_init_internal()
1402 intp->rolloff = p_init->rolloff; stv0900_init_internal()
1403 intp->quartz = p_init->dmd_ref_clk; stv0900_init_internal()
1405 stv0900_write_bits(intp, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff); stv0900_init_internal()
1406 stv0900_write_bits(intp, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff); stv0900_init_internal()
1408 intp->ts_config = p_init->ts_config; stv0900_init_internal()
1409 if (intp->ts_config == NULL) stv0900_init_internal()
1410 stv0900_set_ts_parallel_serial(intp, stv0900_init_internal()
1414 for (i = 0; intp->ts_config[i].addr != 0xffff; i++) stv0900_init_internal()
1415 stv0900_write_reg(intp, stv0900_init_internal()
1416 intp->ts_config[i].addr, stv0900_init_internal()
1417 intp->ts_config[i].val); stv0900_init_internal()
1419 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1); stv0900_init_internal()
1420 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0); stv0900_init_internal()
1421 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1); stv0900_init_internal()
1422 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0); stv0900_init_internal()
1425 intp->tuner_type[0] = p_init->tuner1_type; stv0900_init_internal()
1426 intp->tuner_type[1] = p_init->tuner2_type; stv0900_init_internal()
1430 stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x3c); stv0900_init_internal()
1431 stv0900_write_reg(intp, R0900_P1_TNRCFG2, 0x86); stv0900_init_internal()
1432 stv0900_write_reg(intp, R0900_P1_TNRCFG3, 0x18); stv0900_init_internal()
1433 stv0900_write_reg(intp, R0900_P1_TNRXTAL, 27); /* 27MHz */ stv0900_init_internal()
1434 stv0900_write_reg(intp, R0900_P1_TNRSTEPS, 0x05); stv0900_init_internal()
1435 stv0900_write_reg(intp, R0900_P1_TNRGAIN, 0x17); stv0900_init_internal()
1436 stv0900_write_reg(intp, R0900_P1_TNRADJ, 0x1f); stv0900_init_internal()
1437 stv0900_write_reg(intp, R0900_P1_TNRCTL2, 0x0); stv0900_init_internal()
1438 stv0900_write_bits(intp, F0900_P1_TUN_TYPE, 3); stv0900_init_internal()
1442 stv0900_write_bits(intp, F0900_P1_TUN_TYPE, 6); stv0900_init_internal()
1446 stv0900_write_bits(intp, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress); stv0900_init_internal()
1449 stv0900_write_reg(intp, R0900_TSTTNR1, 0x26); stv0900_init_internal()
1455 stv0900_write_reg(intp, R0900_P1_TNRLD, 1); /* hw tuner */ stv0900_init_internal()
1460 stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x3c); stv0900_init_internal()
1461 stv0900_write_reg(intp, R0900_P2_TNRCFG2, 0x86); stv0900_init_internal()
1462 stv0900_write_reg(intp, R0900_P2_TNRCFG3, 0x18); stv0900_init_internal()
1463 stv0900_write_reg(intp, R0900_P2_TNRXTAL, 27); /* 27MHz */ stv0900_init_internal()
1464 stv0900_write_reg(intp, R0900_P2_TNRSTEPS, 0x05); stv0900_init_internal()
1465 stv0900_write_reg(intp, R0900_P2_TNRGAIN, 0x17); stv0900_init_internal()
1466 stv0900_write_reg(intp, R0900_P2_TNRADJ, 0x1f); stv0900_init_internal()
1467 stv0900_write_reg(intp, R0900_P2_TNRCTL2, 0x0); stv0900_init_internal()
1468 stv0900_write_bits(intp, F0900_P2_TUN_TYPE, 3); stv0900_init_internal()
1472 stv0900_write_bits(intp, F0900_P2_TUN_TYPE, 6); stv0900_init_internal()
1476 stv0900_write_bits(intp, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress); stv0900_init_internal()
1479 stv0900_write_reg(intp, R0900_TSTTNR3, 0x26); stv0900_init_internal()
1485 stv0900_write_reg(intp, R0900_P2_TNRLD, 1); /* hw tuner */ stv0900_init_internal()
1487 stv0900_write_bits(intp, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inv); stv0900_init_internal()
1488 stv0900_write_bits(intp, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inv); stv0900_init_internal()
1489 stv0900_set_mclk(intp, 135000000); stv0900_init_internal()
1492 switch (intp->clkmode) { stv0900_init_internal()
1495 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | intp->clkmode); stv0900_init_internal()
1498 selosci = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL); stv0900_init_internal()
1499 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | selosci); stv0900_init_internal()
1504 intp->mclk = stv0900_get_mclk_freq(intp, intp->quartz); stv0900_init_internal()
1505 if (intp->errs) stv0900_init_internal()
1511 static int stv0900_status(struct stv0900_internal *intp, stv0900_status() argument
1519 demod_state = stv0900_get_bits(intp, HEADER_MODE); stv0900_status()
1527 locked = stv0900_get_bits(intp, LOCK_DEFINITIF) && stv0900_status()
1528 stv0900_get_bits(intp, PKTDELIN_LOCK) && stv0900_status()
1529 stv0900_get_bits(intp, TSFIFO_LINEOK); stv0900_status()
1532 locked = stv0900_get_bits(intp, LOCK_DEFINITIF) && stv0900_status()
1533 stv0900_get_bits(intp, LOCKEDVIT) && stv0900_status()
1534 stv0900_get_bits(intp, TSFIFO_LINEOK); stv0900_status()
1542 tsbitrate0_val = stv0900_read_reg(intp, TSBITRATE0); stv0900_status()
1543 tsbitrate1_val = stv0900_read_reg(intp, TSBITRATE1); stv0900_status()
1545 bitrate = (stv0900_get_mclk_freq(intp, intp->quartz)/1000000) stv0900_status()
1554 static int stv0900_set_mis(struct stv0900_internal *intp, stv0900_set_mis() argument
1561 stv0900_write_bits(intp, FILTER_EN, 0); stv0900_set_mis()
1564 stv0900_write_bits(intp, FILTER_EN, 1); stv0900_set_mis()
1565 stv0900_write_reg(intp, ISIENTRY, mis); stv0900_set_mis()
1566 stv0900_write_reg(intp, ISIBITENA, 0xff); stv0900_set_mis()
1576 struct stv0900_internal *intp = state->internal; stv0900_search() local
1581 struct stv0900_signal_info p_result = intp->result[demod]; stv0900_search()
1593 stv0900_set_mis(intp, demod, c->stream_id); stv0900_search()
1608 intp->srch_standard[demod] = p_search.standard; stv0900_search()
1609 intp->symbol_rate[demod] = p_search.symbol_rate; stv0900_search()
1610 intp->srch_range[demod] = p_search.search_range; stv0900_search()
1611 intp->freq[demod] = p_search.frequency; stv0900_search()
1612 intp->srch_algo[demod] = p_search.search_algo; stv0900_search()
1613 intp->srch_iq_inv[demod] = p_search.iq_inversion; stv0900_search()
1614 intp->fec[demod] = p_search.fec; stv0900_search()
1616 (intp->errs == STV0900_NO_ERROR)) { stv0900_search()
1617 p_result.locked = intp->result[demod].locked; stv0900_search()
1618 p_result.standard = intp->result[demod].standard; stv0900_search()
1619 p_result.frequency = intp->result[demod].frequency; stv0900_search()
1620 p_result.symbol_rate = intp->result[demod].symbol_rate; stv0900_search()
1621 p_result.fec = intp->result[demod].fec; stv0900_search()
1622 p_result.modcode = intp->result[demod].modcode; stv0900_search()
1623 p_result.pilot = intp->result[demod].pilot; stv0900_search()
1624 p_result.frame_len = intp->result[demod].frame_len; stv0900_search()
1625 p_result.spectrum = intp->result[demod].spectrum; stv0900_search()
1626 p_result.rolloff = intp->result[demod].rolloff; stv0900_search()
1627 p_result.modulation = intp->result[demod].modulation; stv0900_search()
1630 switch (intp->err[demod]) { stv0900_search()
1679 struct stv0900_internal *intp = state->internal; stv0900_stop_ts() local
1683 stv0900_write_bits(intp, RST_HWARE, 1); stv0900_stop_ts()
1685 stv0900_write_bits(intp, RST_HWARE, 0); stv0900_stop_ts()
1693 struct stv0900_internal *intp = state->internal; stv0900_diseqc_init() local
1696 stv0900_write_bits(intp, DISTX_MODE, state->config->diseqc_mode); stv0900_diseqc_init()
1697 stv0900_write_bits(intp, DISEQC_RESET, 1); stv0900_diseqc_init()
1698 stv0900_write_bits(intp, DISEQC_RESET, 0); stv0900_diseqc_init()
1713 static int stv0900_diseqc_send(struct stv0900_internal *intp , u8 *data, stv0900_diseqc_send()
1718 stv0900_write_bits(intp, DIS_PRECHARGE, 1); stv0900_diseqc_send()
1720 while (stv0900_get_bits(intp, FIFO_FULL)) stv0900_diseqc_send()
1722 stv0900_write_reg(intp, DISTXDATA, data[i]); stv0900_diseqc_send()
1726 stv0900_write_bits(intp, DIS_PRECHARGE, 0); stv0900_diseqc_send()
1728 while ((stv0900_get_bits(intp, TX_IDLE) != 1) && (i < 10)) { stv0900_diseqc_send()
1750 struct stv0900_internal *intp = state->internal; stv0900_send_burst() local
1757 stv0900_write_bits(intp, DISTX_MODE, 3);/* Unmodulated */ stv0900_send_burst()
1759 stv0900_diseqc_send(intp, &data, 1, state->demod); stv0900_send_burst()
1762 stv0900_write_bits(intp, DISTX_MODE, 2);/* Modulated */ stv0900_send_burst()
1764 stv0900_diseqc_send(intp, &data, 1, state->demod); stv0900_send_burst()
1775 struct stv0900_internal *intp = state->internal; stv0900_recv_slave_reply() local
1781 while ((stv0900_get_bits(intp, RX_END) != 1) && (i < 10)) { stv0900_recv_slave_reply()
1786 if (stv0900_get_bits(intp, RX_END)) { stv0900_recv_slave_reply()
1787 reply->msg_len = stv0900_get_bits(intp, FIFO_BYTENBR); stv0900_recv_slave_reply()
1790 reply->msg[i] = stv0900_read_reg(intp, DISRXDATA); stv0900_recv_slave_reply()
1799 struct stv0900_internal *intp = state->internal; stv0900_set_tone() local
1807 stv0900_write_bits(intp, DISTX_MODE, 0); stv0900_set_tone()
1808 stv0900_write_bits(intp, DISEQC_RESET, 1); stv0900_set_tone()
1810 stv0900_write_bits(intp, DISEQC_RESET, 0); stv0900_set_tone()
1815 stv0900_write_bits(intp, DISTX_MODE, stv0900_set_tone()
1818 stv0900_write_bits(intp, DISEQC_RESET, 1); stv0900_set_tone()
1819 stv0900_write_bits(intp, DISEQC_RESET, 0); stv0900_set_tone()
1864 struct stv0900_internal *intp = state->internal; stv0900_get_frontend() local
1866 struct stv0900_signal_info p_result = intp->result[demod]; stv0900_get_frontend()
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