1 /* 2 * R8A7790 processor support 3 * 4 * Copyright (C) 2013 Renesas Electronics Corporation 5 * Copyright (C) 2013 Magnus Damm 6 * Copyright (C) 2012 Renesas Solutions Corp. 7 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; version 2 of the 12 * License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 */ 23 24 #include <linux/kernel.h> 25 #include <linux/platform_data/gpio-rcar.h> 26 27 #include "core.h" 28 #include "sh_pfc.h" 29 30 #define CPU_ALL_PORT(fn, sfx) \ 31 PORT_GP_32(0, fn, sfx), \ 32 PORT_GP_32(1, fn, sfx), \ 33 PORT_GP_32(2, fn, sfx), \ 34 PORT_GP_32(3, fn, sfx), \ 35 PORT_GP_32(4, fn, sfx), \ 36 PORT_GP_32(5, fn, sfx) 37 38 enum { 39 PINMUX_RESERVED = 0, 40 41 PINMUX_DATA_BEGIN, 42 GP_ALL(DATA), 43 PINMUX_DATA_END, 44 45 PINMUX_FUNCTION_BEGIN, 46 GP_ALL(FN), 47 48 /* GPSR0 */ 49 FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12, 50 FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27, 51 FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12, 52 FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26, 53 FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9, 54 FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22, 55 FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8, 56 FN_IP3_14_12, FN_IP3_17_15, 57 58 /* GPSR1 */ 59 FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26, 60 FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9, 61 FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21, 62 FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6, 63 FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18, 64 FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0, 65 FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11, 66 67 /* GPSR2 */ 68 FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4, 69 FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14, 70 FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22, 71 FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7, 72 FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23, 73 FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6, 74 FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13, 75 76 /* GPSR3 */ 77 FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4, 78 FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18, 79 FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26, 80 FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11, 81 FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26, 82 FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9, 83 FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18, 84 85 /* GPSR4 */ 86 FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30, 87 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8, 88 FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20, 89 FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0, 90 FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13, 91 FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26, 92 FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9, 93 FN_IP14_15_12, FN_IP14_18_16, 94 95 /* GPSR5 */ 96 FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28, 97 FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12, 98 FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20, 99 FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0, 100 FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7, 101 FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0, 102 FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22, 103 104 /* IPSR0 */ 105 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, 106 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, 107 FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, 108 FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B, 109 FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4, 110 FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, 111 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5, 112 FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, 113 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6, 114 FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, 115 FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, 116 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1, 117 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 118 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, 119 120 /* IPSR1 */ 121 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 122 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10, 123 FN_SCIFA1_TXD_C, FN_AVB_TXD2, 124 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11, 125 FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 126 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, 127 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, 128 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, 129 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, 130 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14, 131 FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, 132 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, 133 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, 134 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, 135 FN_A0, FN_PWM3, FN_A1, FN_PWM4, 136 137 /* IPSR2 */ 138 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3, 139 FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B, 140 FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 141 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7, 142 FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, 143 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, 144 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B, 145 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, 146 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B, 147 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, 148 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 149 150 /* IPSR3 */ 151 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, 152 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 153 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, 154 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, 155 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, 156 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, 157 FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B, 158 FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B, 159 FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N, 160 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18, 161 FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B, 162 FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK, 163 FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, 164 165 /* IPSR4 */ 166 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 167 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, 168 FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7, 169 FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3, 170 FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, 171 FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6, 172 FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N, 173 FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, 174 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, 175 FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B, 176 FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B, 177 FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK, 178 FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B, 179 FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, 180 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 181 182 /* IPSR5 */ 183 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, 184 FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, 185 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B, 186 FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX, 187 FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2, 188 FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N, 189 FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B, 190 FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N, 191 FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3, 192 FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, 193 FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK, 194 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 195 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, 196 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, 197 FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, 198 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, 199 FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N, 200 FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C, 201 FN_SSI_WS78_B, 202 203 /* IPSR6 */ 204 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, 205 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 206 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, 207 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1, 208 FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C, 209 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, 210 FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, 211 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 212 FN_ETH_CRS_DV, FN_STP_ISCLK_0_B, 213 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, 214 FN_I2C2_SCL_E, FN_ETH_RX_ER, 215 FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, 216 FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0, 217 FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, 218 FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, 219 FN_HRX0_E, FN_STP_ISSYNC_0_B, 220 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, 221 FN_RX1_E, FN_ETH_LINK, FN_HTX0_E, 222 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 223 FN_ETH_REF_CLK, FN_HCTS0_N_E, 224 FN_STP_IVCXO27_1_B, FN_HRX0_F, 225 226 /* IPSR7 */ 227 FN_ETH_MDIO, FN_HRTS0_N_E, 228 FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1, 229 FN_HTX0_F, FN_BPFCLK_G, 230 FN_ETH_TX_EN, FN_SIM0_CLK_C, 231 FN_HRTS0_N_F, FN_ETH_MAGIC, 232 FN_SIM0_RST_C, FN_ETH_TXD0, 233 FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C, 234 FN_ETH_MDC, FN_STP_ISD_1_B, 235 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0, 236 FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, 237 FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C, 238 FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C, 239 FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, 240 FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1, 241 FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK, 242 FN_ATACS00_N, FN_AVB_RXD1, 243 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 244 245 /* IPSR8 */ 246 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 247 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, 248 FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, 249 FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, 250 FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, 251 FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 252 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 253 FN_VI1_CLK, FN_AVB_RX_DV, 254 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, 255 FN_AVB_CRS, FN_VI1_DATA1_VI1_B1, 256 FN_SCIFA1_RXD_D, FN_AVB_MDC, 257 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 258 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, 259 FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, 260 FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5, 261 FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, 262 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD, 263 FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 264 265 /* IPSR9 */ 266 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 267 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 268 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 269 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 270 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, 271 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B, 272 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP, 273 FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, 274 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, 275 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, 276 FN_AVB_TX_EN, FN_SD1_CMD, 277 FN_AVB_TX_ER, FN_SCIFB0_SCK_B, 278 FN_SD1_DAT0, FN_AVB_TX_CLK, 279 FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK, 280 FN_SCIFB0_TXD_B, FN_SD1_DAT2, 281 FN_AVB_COL, FN_SCIFB0_CTS_N_B, 282 FN_SD1_DAT3, FN_AVB_RXD0, 283 FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6, 284 FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, 285 FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B, 286 FN_VI3_CLK_B, 287 288 /* IPSR10 */ 289 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, 290 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, 291 FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, 292 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, 293 FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, 294 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, 295 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, 296 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, 297 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, 298 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, 299 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 300 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, 301 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, 302 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 303 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, 304 FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3, 305 FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, 306 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, 307 FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4, 308 FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, 309 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, 310 FN_GLO_I0_B, FN_VI3_DATA6_B, 311 312 /* IPSR11 */ 313 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, 314 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, 315 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 316 FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD, 317 FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 318 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2, 319 FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3, 320 FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, 321 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP, 322 FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, 323 FN_FMIN_E, FN_FMIN_F, 324 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 325 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, 326 FN_I2C2_SDA_B, FN_MLB_DAT, 327 FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, 328 FN_SSI_SCK0129, FN_CAN_CLK_B, 329 FN_MOUT0, 330 331 /* IPSR12 */ 332 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 333 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 334 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 335 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, 336 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, 337 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34, 338 FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, 339 FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0, 340 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 341 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, 342 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 343 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, 344 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 345 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, 346 FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK, 347 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, 348 FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD, 349 FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, 350 FN_CAN_DEBUGOUT4, 351 352 /* IPSR13 */ 353 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, 354 FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6, 355 FN_SCIFB1_CTS_N, FN_BPFCLK_D, 356 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, 357 FN_BPFCLK_F, FN_SSI_WS6, 358 FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, 359 FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6, 360 FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5, 361 FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1, 362 FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6, 363 FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1, 364 FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7, 365 FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7, 366 FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, 367 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, 368 FN_BPFCLK_E, FN_SSI_SDATA7_B, 369 FN_FMIN_G, FN_SSI_SDATA8, 370 FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, 371 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9, 372 FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, 373 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA, 374 FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 375 376 /* IPSR14 */ 377 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, 378 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, 379 FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, 380 FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C, 381 FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0, 382 FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1, 383 FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N, 384 FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3, 385 FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, 386 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N, 387 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 388 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, 389 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 390 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, 391 FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK, 392 FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK, 393 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, 394 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, 395 FN_HRTS0_N_C, 396 397 /* IPSR15 */ 398 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, 399 FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN, 400 FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL, 401 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17, 402 FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0, 403 FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0, 404 FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3, 405 FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, 406 FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, 407 FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, 408 FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0, 409 FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23, 410 FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0, 411 FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1, 412 FN_DU2_DG6, FN_LCDOUT14, 413 414 /* IPSR16 */ 415 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, 416 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 417 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, 418 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 419 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC, 420 FN_TCLK1_B, 421 422 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 423 FN_SEL_SCIF1_4, 424 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 425 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 426 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, 427 FN_SEL_SCIFB1_4, 428 FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6, 429 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3, 430 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, 431 FN_SEL_SCFA_0, FN_SEL_SCFA_1, 432 FN_SEL_SOF1_0, FN_SEL_SOF1_1, 433 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 434 FN_SEL_SSI6_0, FN_SEL_SSI6_1, 435 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 436 FN_SEL_VI3_0, FN_SEL_VI3_1, 437 FN_SEL_VI2_0, FN_SEL_VI2_1, 438 FN_SEL_VI1_0, FN_SEL_VI1_1, 439 FN_SEL_VI0_0, FN_SEL_VI0_1, 440 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 441 FN_SEL_LBS_0, FN_SEL_LBS_1, 442 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 443 FN_SEL_SOF3_0, FN_SEL_SOF3_1, 444 FN_SEL_SOF0_0, FN_SEL_SOF0_1, 445 446 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 447 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, 448 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, 449 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 450 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, 451 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 452 FN_SEL_CAN1_0, FN_SEL_CAN1_1, 453 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, 454 FN_SEL_ADI_0, FN_SEL_ADI_1, 455 FN_SEL_SSP_0, FN_SEL_SSP_1, 456 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, 457 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 458 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3, 459 FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 460 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 461 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 462 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 463 464 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, 465 FN_SEL_IIC0_0, FN_SEL_IIC0_1, 466 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 467 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, 468 FN_SEL_IIC2_4, 469 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 470 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 471 FN_SEL_I2C2_4, 472 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 473 PINMUX_FUNCTION_END, 474 475 PINMUX_MARK_BEGIN, 476 477 VI1_DATA7_VI1_B7_MARK, 478 479 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, 480 USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK, 481 DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK, 482 483 D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK, 484 D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK, 485 VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK, 486 VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK, 487 VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK, 488 SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK, 489 VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK, 490 SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK, 491 VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK, 492 IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, 493 I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK, 494 VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK, 495 D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, 496 VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK, 497 498 D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, 499 VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK, 500 SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, 501 VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK, 502 SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, 503 VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK, 504 D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK, 505 VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK, 506 D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK, 507 VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK, 508 SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK, 509 VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK, 510 D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK, 511 VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK, 512 A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK, 513 514 A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK, 515 PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK, 516 TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK, 517 A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK, 518 SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK, 519 A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK, 520 VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK, 521 A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK, 522 VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK, 523 A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK, 524 VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK, 525 526 A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK, 527 VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK, 528 A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK, 529 VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK, 530 A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK, 531 MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK, 532 VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK, 533 ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK, 534 ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK, 535 A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK, 536 AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK, 537 ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK, 538 VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK, 539 540 A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK, 541 A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK, 542 VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK, 543 VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK, 544 VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK, 545 VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK, 546 VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK, 547 VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK, 548 CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK, 549 VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK, 550 VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK, 551 MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK, 552 HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK, 553 VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK, 554 VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK, 555 556 EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK, 557 VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK, 558 EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK, 559 VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK, 560 INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK, 561 MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK, 562 VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK, 563 I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK, 564 CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK, 565 CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK, 566 VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK, 567 INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, 568 VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK, 569 WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK, 570 VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK, 571 IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK, 572 VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK, 573 MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK, 574 VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK, 575 SSI_WS78_B_MARK, 576 577 DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK, 578 VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK, 579 DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK, 580 SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK, 581 INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, 582 DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, 583 MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, 584 SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, 585 ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK, 586 TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK, 587 I2C2_SCL_E_MARK, ETH_RX_ER_MARK, 588 STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, 589 IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK, 590 STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, 591 SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, 592 HRX0_E_MARK, STP_ISSYNC_0_B_MARK, 593 TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK, 594 RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK, 595 STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK, 596 ETH_REF_CLK_MARK, HCTS0_N_E_MARK, 597 STP_IVCXO27_1_B_MARK, HRX0_F_MARK, 598 599 ETH_MDIO_MARK, HRTS0_N_E_MARK, 600 SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK, 601 HTX0_F_MARK, BPFCLK_G_MARK, 602 ETH_TX_EN_MARK, SIM0_CLK_C_MARK, 603 HRTS0_N_F_MARK, ETH_MAGIC_MARK, 604 SIM0_RST_C_MARK, ETH_TXD0_MARK, 605 STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK, 606 ETH_MDC_MARK, STP_ISD_1_B_MARK, 607 TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK, 608 SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK, 609 GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK, 610 STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK, 611 PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK, 612 PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK, 613 AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK, 614 ATACS00_N_MARK, AVB_RXD1_MARK, 615 VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, 616 617 VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK, 618 VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK, 619 AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK, 620 AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK, 621 AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK, 622 AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK, 623 VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK, 624 VI1_CLK_MARK, AVB_RX_DV_MARK, 625 VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK, 626 AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK, 627 SCIFA1_RXD_D_MARK, AVB_MDC_MARK, 628 VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK, 629 VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK, 630 AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK, 631 AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK, 632 AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK, 633 SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK, 634 SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK, 635 636 SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK, 637 SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK, 638 SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK, 639 SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK, 640 SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK, 641 GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK, 642 I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK, 643 MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK, 644 GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK, 645 I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, 646 AVB_TX_EN_MARK, SD1_CMD_MARK, 647 AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK, 648 SD1_DAT0_MARK, AVB_TX_CLK_MARK, 649 SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK, 650 SCIFB0_TXD_B_MARK, SD1_DAT2_MARK, 651 AVB_COL_MARK, SCIFB0_CTS_N_B_MARK, 652 SD1_DAT3_MARK, AVB_RXD0_MARK, 653 SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK, 654 TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK, 655 IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK, 656 VI3_CLK_B_MARK, 657 658 SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK, 659 GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK, 660 SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK, 661 VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK, 662 VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK, 663 VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK, 664 TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK, 665 SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK, 666 VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK, 667 TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK, 668 SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, 669 VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK, 670 TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK, 671 SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, 672 VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK, 673 GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK, 674 MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK, 675 HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK, 676 VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK, 677 TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK, 678 VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK, 679 GLO_I0_B_MARK, VI3_DATA6_B_MARK, 680 681 SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK, 682 GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK, 683 TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK, 684 SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK, 685 MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK, 686 SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK, 687 MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK, 688 SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK, 689 VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK, 690 MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK, 691 FMIN_E_MARK, FMIN_F_MARK, 692 MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK, 693 MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK, 694 I2C2_SDA_B_MARK, MLB_DAT_MARK, 695 SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK, 696 SSI_SCK0129_MARK, CAN_CLK_B_MARK, 697 MOUT0_MARK, 698 699 SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK, 700 SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK, 701 SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK, 702 SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK, 703 SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK, 704 MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK, 705 STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK, 706 CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK, 707 SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK, 708 SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK, 709 MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK, 710 SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK, 711 MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK, 712 SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK, 713 CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK, 714 IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK, 715 CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK, 716 IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK, 717 CAN_DEBUGOUT4_MARK, 718 719 SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK, 720 LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK, 721 SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, 722 DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK, 723 BPFCLK_F_MARK, SSI_WS6_MARK, 724 SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK, 725 LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK, 726 FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK, 727 CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK, 728 SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK, 729 CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK, 730 SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK, 731 LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK, 732 STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK, 733 TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK, 734 BPFCLK_E_MARK, SSI_SDATA7_B_MARK, 735 FMIN_G_MARK, SSI_SDATA8_MARK, 736 STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK, 737 CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK, 738 STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK, 739 SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK, 740 SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK, 741 742 AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK, 743 DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK, 744 REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK, 745 MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK, 746 I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK, 747 DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK, 748 TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK, 749 HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK, 750 LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK, 751 SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK, 752 MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK, 753 SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK, 754 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, 755 SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK, 756 LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK, 757 CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK, 758 SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK, 759 MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK, 760 HRTS0_N_C_MARK, 761 762 SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK, 763 LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK, 764 TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK, 765 SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK, 766 IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK, 767 DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK, 768 DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK, 769 LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK, 770 LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK, 771 LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK, 772 DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK, 773 SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK, 774 HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK, 775 DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK, 776 DU2_DG6_MARK, LCDOUT14_MARK, 777 778 MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK, 779 DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK, 780 MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK, 781 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK, 782 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK, 783 TCLK1_B_MARK, 784 785 IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK, 786 IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK, 787 PINMUX_MARK_END, 788 }; 789 790 static const u16 pinmux_data[] = { 791 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 792 793 PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7), 794 PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), 795 PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS), 796 PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN), 797 PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC), 798 PINMUX_DATA(AVS1_MARK, FN_AVS1), 799 PINMUX_DATA(AVS2_MARK, FN_AVS2), 800 PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0), 801 PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2), 802 803 PINMUX_IPSR_DATA(IP0_2_0, D0), 804 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1), 805 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0), 806 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0), 807 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1), 808 PINMUX_IPSR_DATA(IP0_5_3, D1), 809 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1), 810 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0), 811 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0), 812 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1), 813 PINMUX_IPSR_DATA(IP0_8_6, D2), 814 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1), 815 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0), 816 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0), 817 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1), 818 PINMUX_IPSR_DATA(IP0_11_9, D3), 819 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1), 820 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0), 821 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0), 822 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1), 823 PINMUX_IPSR_DATA(IP0_15_12, D4), 824 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5), 825 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2), 826 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0), 827 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0), 828 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1), 829 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1), 830 PINMUX_IPSR_DATA(IP0_19_16, D5), 831 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5), 832 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2), 833 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0), 834 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0), 835 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1), 836 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1), 837 PINMUX_IPSR_DATA(IP0_22_20, D6), 838 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2), 839 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0), 840 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0), 841 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1), 842 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2), 843 PINMUX_IPSR_DATA(IP0_26_23, D7), 844 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1), 845 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2), 846 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0), 847 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0), 848 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1), 849 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2), 850 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, TCLK1, SEL_TMU1_0), 851 PINMUX_IPSR_DATA(IP0_30_27, D8), 852 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), 853 PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0), 854 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0), 855 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1), 856 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0), 857 858 PINMUX_IPSR_DATA(IP1_3_0, D9), 859 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2), 860 PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1), 861 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0), 862 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1), 863 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0), 864 PINMUX_IPSR_DATA(IP1_7_4, D10), 865 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2), 866 PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2), 867 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0), 868 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1), 869 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0), 870 PINMUX_IPSR_DATA(IP1_11_8, D11), 871 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2), 872 PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3), 873 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0), 874 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1), 875 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0), 876 PINMUX_IPSR_DATA(IP1_14_12, D12), 877 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2), 878 PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4), 879 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0), 880 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1), 881 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0), 882 PINMUX_IPSR_DATA(IP1_17_15, D13), 883 PINMUX_IPSR_DATA(IP1_17_15, AVB_TXD5), 884 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0), 885 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1), 886 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0), 887 PINMUX_IPSR_DATA(IP1_21_18, D14), 888 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2), 889 PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6), 890 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1), 891 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0), 892 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1), 893 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0), 894 PINMUX_IPSR_DATA(IP1_25_22, D15), 895 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2), 896 PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7), 897 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1), 898 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0), 899 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1), 900 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0), 901 PINMUX_IPSR_DATA(IP1_27_26, A0), 902 PINMUX_IPSR_DATA(IP1_27_26, PWM3), 903 PINMUX_IPSR_DATA(IP1_29_28, A1), 904 PINMUX_IPSR_DATA(IP1_29_28, PWM4), 905 906 PINMUX_IPSR_DATA(IP2_2_0, A2), 907 PINMUX_IPSR_DATA(IP2_2_0, PWM5), 908 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1), 909 PINMUX_IPSR_DATA(IP2_5_3, A3), 910 PINMUX_IPSR_DATA(IP2_5_3, PWM6), 911 PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1), 912 PINMUX_IPSR_DATA(IP2_8_6, A4), 913 PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1), 914 PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0), 915 PINMUX_IPSR_DATA(IP2_11_9, A5), 916 PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1), 917 PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1), 918 PINMUX_IPSR_DATA(IP2_14_12, A6), 919 PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1), 920 PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2), 921 PINMUX_IPSR_DATA(IP2_17_15, A7), 922 PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1), 923 PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B), 924 PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3), 925 PINMUX_IPSR_DATA(IP2_21_18, A8), 926 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1), 927 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1), 928 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0), 929 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1), 930 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2), 931 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, RX2_B, SEL_SCIF2_1), 932 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1), 933 PINMUX_IPSR_DATA(IP2_25_22, A9), 934 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1), 935 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1), 936 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0), 937 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1), 938 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2), 939 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, TX2_B, SEL_SCIF2_1), 940 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1), 941 PINMUX_IPSR_DATA(IP2_28_26, A10), 942 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1), 943 PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC), 944 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0), 945 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1), 946 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1), 947 948 PINMUX_IPSR_DATA(IP3_3_0, A11), 949 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1), 950 PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK), 951 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0), 952 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1), 953 PINMUX_IPSR_DATA(IP3_3_0, VI2_G0), 954 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1), 955 PINMUX_IPSR_DATA(IP3_7_4, A12), 956 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1), 957 PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD), 958 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0), 959 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1), 960 PINMUX_IPSR_DATA(IP3_7_4, VI2_G1), 961 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1), 962 PINMUX_IPSR_DATA(IP3_11_8, A13), 963 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1), 964 PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2), 965 PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD), 966 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0), 967 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1), 968 PINMUX_IPSR_DATA(IP3_11_8, VI2_G2), 969 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1), 970 PINMUX_IPSR_DATA(IP3_14_12, A14), 971 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1), 972 PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N), 973 PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1), 974 PINMUX_IPSR_DATA(IP3_17_15, A15), 975 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1), 976 PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N), 977 PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2), 978 PINMUX_IPSR_DATA(IP3_19_18, A16), 979 PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N), 980 PINMUX_IPSR_DATA(IP3_22_20, A17), 981 PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1), 982 PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N), 983 PINMUX_IPSR_DATA(IP3_25_23, A18), 984 PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1), 985 PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N), 986 PINMUX_IPSR_DATA(IP3_28_26, A19), 987 PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1), 988 PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N), 989 PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1), 990 PINMUX_IPSR_DATA(IP3_31_29, A20), 991 PINMUX_IPSR_DATA(IP3_31_29, SPCLK), 992 PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0), 993 PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1), 994 PINMUX_IPSR_DATA(IP3_31_29, VI2_G4), 995 996 PINMUX_IPSR_DATA(IP4_2_0, A21), 997 PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0), 998 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0), 999 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1), 1000 PINMUX_IPSR_DATA(IP4_2_0, VI2_G5), 1001 PINMUX_IPSR_DATA(IP4_5_3, A22), 1002 PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1), 1003 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0), 1004 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1), 1005 PINMUX_IPSR_DATA(IP4_5_3, VI2_G6), 1006 PINMUX_IPSR_DATA(IP4_8_6, A23), 1007 PINMUX_IPSR_DATA(IP4_8_6, IO2), 1008 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0), 1009 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1), 1010 PINMUX_IPSR_DATA(IP4_8_6, VI2_G7), 1011 PINMUX_IPSR_DATA(IP4_11_9, A24), 1012 PINMUX_IPSR_DATA(IP4_11_9, IO3), 1013 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0), 1014 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1), 1015 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0), 1016 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1), 1017 PINMUX_IPSR_DATA(IP4_14_12, A25), 1018 PINMUX_IPSR_DATA(IP4_14_12, SSL), 1019 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0), 1020 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1), 1021 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0), 1022 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1), 1023 PINMUX_IPSR_DATA(IP4_17_15, CS0_N), 1024 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0), 1025 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1), 1026 PINMUX_IPSR_DATA(IP4_17_15, VI2_G3), 1027 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1), 1028 PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26), 1029 PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN), 1030 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0), 1031 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1), 1032 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0), 1033 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1), 1034 PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N), 1035 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1), 1036 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0), 1037 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1), 1038 PINMUX_IPSR_DATA(IP4_23_21, VI2_R0), 1039 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1), 1040 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1), 1041 PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N), 1042 PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK), 1043 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1), 1044 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0), 1045 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1), 1046 PINMUX_IPSR_DATA(IP4_26_24, VI2_R1), 1047 PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N), 1048 PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN), 1049 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1), 1050 PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB), 1051 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0), 1052 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1), 1053 PINMUX_IPSR_DATA(IP4_29_27, VI2_R2), 1054 1055 PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N), 1056 PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG), 1057 PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD), 1058 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0), 1059 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1), 1060 PINMUX_IPSR_DATA(IP5_2_0, VI2_R3), 1061 PINMUX_IPSR_DATA(IP5_5_3, EX_CS4_N), 1062 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1), 1063 PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N), 1064 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0), 1065 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, IIC1_SCL, SEL_IIC1_0), 1066 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1), 1067 PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N), 1068 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, I2C1_SCL, SEL_I2C1_0), 1069 PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N), 1070 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0), 1071 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1), 1072 PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N), 1073 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0), 1074 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1), 1075 PINMUX_IPSR_DATA(IP5_9_6, VI2_R4), 1076 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, IIC1_SDA, SEL_IIC1_0), 1077 PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N), 1078 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, I2C1_SDA, SEL_I2C1_0), 1079 PINMUX_IPSR_DATA(IP5_12_10, BS_N), 1080 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0), 1081 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1), 1082 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0), 1083 PINMUX_IPSR_DATA(IP5_12_10, DRACK0), 1084 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2), 1085 PINMUX_IPSR_DATA(IP5_14_13, RD_N), 1086 PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0), 1087 PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1), 1088 PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N), 1089 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0), 1090 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1), 1091 PINMUX_IPSR_DATA(IP5_17_15, VI2_R5), 1092 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1), 1093 PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N), 1094 PINMUX_IPSR_DATA(IP5_20_18, WE0_N), 1095 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0), 1096 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0), 1097 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0), 1098 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1), 1099 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1), 1100 PINMUX_IPSR_DATA(IP5_23_21, WE1_N), 1101 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0), 1102 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0), 1103 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0), 1104 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1), 1105 PINMUX_IPSR_DATA(IP5_23_21, VI2_R6), 1106 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1), 1107 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2), 1108 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, EX_WAIT0, SEL_LBS_0), 1109 PINMUX_IPSR_DATA(IP5_26_24, IRQ3), 1110 PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N), 1111 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0), 1112 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1), 1113 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1), 1114 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1), 1115 PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N), 1116 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0), 1117 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1), 1118 PINMUX_IPSR_DATA(IP5_29_27, VI2_R7), 1119 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2), 1120 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1), 1121 1122 PINMUX_IPSR_DATA(IP6_2_0, DACK0), 1123 PINMUX_IPSR_DATA(IP6_2_0, IRQ0), 1124 PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N), 1125 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), 1126 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), 1127 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), 1128 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2), 1129 PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N), 1130 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0), 1131 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1), 1132 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2), 1133 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), 1134 PINMUX_IPSR_DATA(IP6_8_6, DACK1), 1135 PINMUX_IPSR_DATA(IP6_8_6, IRQ1), 1136 PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N), 1137 PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), 1138 PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), 1139 PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N), 1140 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1), 1141 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1), 1142 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), 1143 PINMUX_IPSR_DATA(IP6_13_11, DACK2), 1144 PINMUX_IPSR_DATA(IP6_13_11, IRQ2), 1145 PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N), 1146 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), 1147 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), 1148 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), 1149 PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV), 1150 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), 1151 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), 1152 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2), 1153 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4), 1154 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4), 1155 PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER), 1156 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), 1157 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), 1158 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2), 1159 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4), 1160 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4), 1161 PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0), 1162 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), 1163 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), 1164 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2), 1165 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), 1166 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4), 1167 PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1), 1168 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4), 1169 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), 1170 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), 1171 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2), 1172 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), 1173 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4), 1174 PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK), 1175 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4), 1176 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), 1177 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), 1178 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4), 1179 PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK), 1180 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), 1181 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), 1182 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5), 1183 1184 PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO), 1185 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), 1186 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2), 1187 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), 1188 PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1), 1189 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_5), 1190 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_FM_6), 1191 PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN), 1192 PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), 1193 PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), 1194 PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC), 1195 PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2), 1196 PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0), 1197 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), 1198 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), 1199 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), 1200 PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC), 1201 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), 1202 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), 1203 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), 1204 PINMUX_IPSR_DATA(IP7_18_16, PWM0), 1205 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2), 1206 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1), 1207 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2), 1208 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2), 1209 PINMUX_IPSR_DATA(IP7_21_19, PWM1), 1210 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2), 1211 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1), 1212 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2), 1213 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2), 1214 PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N), 1215 PINMUX_IPSR_DATA(IP7_24_22, PWM2), 1216 PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0), 1217 PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2), 1218 PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N), 1219 PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2), 1220 PINMUX_IPSR_DATA(IP7_26_25, DU_DOTCLKIN1), 1221 PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC), 1222 PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C), 1223 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0), 1224 PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N), 1225 PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1), 1226 PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), 1227 PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N), 1228 PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2), 1229 1230 PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0), 1231 PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N), 1232 PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3), 1233 PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0), 1234 PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N), 1235 PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4), 1236 PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0), 1237 PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N), 1238 PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5), 1239 PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0), 1240 PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N), 1241 PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6), 1242 PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0), 1243 PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1), 1244 PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7), 1245 PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0), 1246 PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER), 1247 PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0), 1248 PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK), 1249 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0), 1250 PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV), 1251 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0), 1252 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3), 1253 PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS), 1254 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0), 1255 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3), 1256 PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC), 1257 PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0), 1258 PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3), 1259 PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO), 1260 PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0), 1261 PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3), 1262 PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK), 1263 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0), 1264 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), 1265 PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC), 1266 PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), 1267 PINMUX_IPSR_DATA(IP8_26, AVB_PHY_INT), 1268 PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), 1269 PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK), 1270 PINMUX_IPSR_DATA(IP8_28, SD0_CLK), 1271 PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1), 1272 PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD), 1273 PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1), 1274 PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1), 1275 1276 PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0), 1277 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1), 1278 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1), 1279 PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1), 1280 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1), 1281 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1), 1282 PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2), 1283 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1), 1284 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1), 1285 PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3), 1286 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1), 1287 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1), 1288 PINMUX_IPSR_DATA(IP9_11_8, SD0_CD), 1289 PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6), 1290 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1), 1291 PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP), 1292 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0), 1293 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1), 1294 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1), 1295 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1), 1296 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1), 1297 PINMUX_IPSR_DATA(IP9_15_12, SD0_WP), 1298 PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7), 1299 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1), 1300 PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN), 1301 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0), 1302 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1), 1303 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1), 1304 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1), 1305 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), 1306 PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK), 1307 PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN), 1308 PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD), 1309 PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER), 1310 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1), 1311 PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0), 1312 PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK), 1313 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1), 1314 PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1), 1315 PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK), 1316 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1), 1317 PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2), 1318 PINMUX_IPSR_DATA(IP9_25_24, AVB_COL), 1319 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1), 1320 PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3), 1321 PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0), 1322 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1), 1323 PINMUX_IPSR_DATA(IP9_31_28, SD1_CD), 1324 PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6), 1325 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0), 1326 PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP), 1327 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0), 1328 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1), 1329 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3), 1330 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3), 1331 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1), 1332 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1), 1333 1334 PINMUX_IPSR_DATA(IP10_3_0, SD1_WP), 1335 PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7), 1336 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0), 1337 PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN), 1338 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0), 1339 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1), 1340 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3), 1341 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3), 1342 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1), 1343 PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK), 1344 PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK), 1345 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0), 1346 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1), 1347 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2), 1348 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1), 1349 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1), 1350 PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD), 1351 PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD), 1352 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0), 1353 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1), 1354 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4), 1355 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3), 1356 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2), 1357 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1), 1358 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1), 1359 PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0), 1360 PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0), 1361 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1), 1362 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1), 1363 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4), 1364 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3), 1365 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2), 1366 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1), 1367 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1), 1368 PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1), 1369 PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1), 1370 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1), 1371 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1), 1372 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4), 1373 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3), 1374 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2), 1375 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1), 1376 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1), 1377 PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2), 1378 PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2), 1379 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1), 1380 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1), 1381 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3), 1382 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1), 1383 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1), 1384 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1), 1385 PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3), 1386 PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3), 1387 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0), 1388 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1), 1389 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3), 1390 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1), 1391 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1), 1392 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1), 1393 PINMUX_IPSR_DATA(IP10_29_26, SD2_CD), 1394 PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4), 1395 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1), 1396 PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP), 1397 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0), 1398 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1), 1399 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3), 1400 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1), 1401 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1), 1402 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1), 1403 1404 PINMUX_IPSR_DATA(IP11_3_0, SD2_WP), 1405 PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5), 1406 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1), 1407 PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN), 1408 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0), 1409 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1), 1410 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3), 1411 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1), 1412 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1), 1413 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1), 1414 PINMUX_IPSR_DATA(IP11_4, SD3_CLK), 1415 PINMUX_IPSR_DATA(IP11_4, MMC1_CLK), 1416 PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD), 1417 PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD), 1418 PINMUX_IPSR_DATA(IP11_6_5, MTS_N), 1419 PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0), 1420 PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0), 1421 PINMUX_IPSR_DATA(IP11_8_7, STM_N), 1422 PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1), 1423 PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1), 1424 PINMUX_IPSR_DATA(IP11_10_9, MDATA), 1425 PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2), 1426 PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2), 1427 PINMUX_IPSR_DATA(IP11_12_11, SDATA), 1428 PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3), 1429 PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3), 1430 PINMUX_IPSR_DATA(IP11_14_13, SCKZ), 1431 PINMUX_IPSR_DATA(IP11_17_15, SD3_CD), 1432 PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4), 1433 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0), 1434 PINMUX_IPSR_DATA(IP11_17_15, VSP), 1435 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0), 1436 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1), 1437 PINMUX_IPSR_DATA(IP11_21_18, SD3_WP), 1438 PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5), 1439 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0), 1440 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0), 1441 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2), 1442 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4), 1443 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5), 1444 PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK), 1445 PINMUX_IPSR_MODSEL_DATA(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1), 1446 PINMUX_IPSR_MODSEL_DATA(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1), 1447 PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG), 1448 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3), 1449 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2), 1450 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1), 1451 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1), 1452 PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT), 1453 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), 1454 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2), 1455 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2), 1456 PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129), 1457 PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1), 1458 PINMUX_IPSR_DATA(IP11_31_30, MOUT0), 1459 1460 PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129), 1461 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1), 1462 PINMUX_IPSR_DATA(IP12_1_0, MOUT1), 1463 PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0), 1464 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1), 1465 PINMUX_IPSR_DATA(IP12_3_2, MOUT2), 1466 PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1), 1467 PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1), 1468 PINMUX_IPSR_DATA(IP12_5_4, MOUT5), 1469 PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2), 1470 PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1), 1471 PINMUX_IPSR_DATA(IP12_7_6, SSI_SCK1), 1472 PINMUX_IPSR_DATA(IP12_7_6, MOUT6), 1473 PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34), 1474 PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0), 1475 PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0), 1476 PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0), 1477 PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER), 1478 PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34), 1479 PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0), 1480 PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0), 1481 PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC), 1482 PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0), 1483 PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3), 1484 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0), 1485 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0), 1486 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0), 1487 PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK), 1488 PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4), 1489 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0), 1490 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0), 1491 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0), 1492 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2), 1493 PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0), 1494 PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4), 1495 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0), 1496 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0), 1497 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0), 1498 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2), 1499 PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1), 1500 PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4), 1501 PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0), 1502 PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0), 1503 PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2), 1504 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0), 1505 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0), 1506 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1), 1507 PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC), 1508 PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS), 1509 PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3), 1510 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0), 1511 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0), 1512 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1), 1513 PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC), 1514 PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE), 1515 PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4), 1516 1517 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0), 1518 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0), 1519 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1), 1520 PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2), 1521 PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2), 1522 PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5), 1523 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0), 1524 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0), 1525 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3), 1526 PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3), 1527 PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3), 1528 PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6), 1529 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5), 1530 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0), 1531 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0), 1532 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3), 1533 PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4), 1534 PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4), 1535 PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7), 1536 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0), 1537 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3), 1538 PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5), 1539 PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5), 1540 PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8), 1541 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0), 1542 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0), 1543 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0), 1544 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0), 1545 PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6), 1546 PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6), 1547 PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9), 1548 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0), 1549 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0), 1550 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0), 1551 PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N), 1552 PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7), 1553 PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7), 1554 PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10), 1555 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0), 1556 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0), 1557 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0), 1558 PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N), 1559 PINMUX_IPSR_DATA(IP13_22_19, TCLK2), 1560 PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS), 1561 PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11), 1562 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4), 1563 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1), 1564 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6), 1565 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0), 1566 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0), 1567 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0), 1568 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2), 1569 PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12), 1570 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1), 1571 PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9), 1572 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0), 1573 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0), 1574 PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1), 1575 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2), 1576 PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13), 1577 PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA), 1578 PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0), 1579 PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14), 1580 1581 PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB), 1582 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0), 1583 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3), 1584 PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE), 1585 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2), 1586 PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15), 1587 PINMUX_IPSR_DATA(IP14_2_0, REMOCON), 1588 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0), 1589 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0), 1590 PINMUX_IPSR_DATA(IP14_5_3, SCK0), 1591 PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2), 1592 PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2), 1593 PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10), 1594 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2), 1595 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2), 1596 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0), 1597 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0), 1598 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0), 1599 PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0), 1600 PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0), 1601 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0), 1602 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0), 1603 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0), 1604 PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1), 1605 PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1), 1606 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0), 1607 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0), 1608 PINMUX_IPSR_DATA(IP14_15_12, CTS0_N), 1609 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0), 1610 PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3), 1611 PINMUX_IPSR_DATA(IP14_15_12, LCDOUT11), 1612 PINMUX_IPSR_DATA(IP14_15_12, PWM0_B), 1613 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2), 1614 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2), 1615 PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), 1616 PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0), 1617 PINMUX_IPSR_DATA(IP14_18_16, RTS0_N), 1618 PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1), 1619 PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0), 1620 PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8), 1621 PINMUX_IPSR_DATA(IP14_18_16, PWM1_B), 1622 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0), 1623 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0), 1624 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0), 1625 PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE), 1626 PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE), 1627 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0), 1628 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0), 1629 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0), 1630 PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1), 1631 PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9), 1632 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0), 1633 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0), 1634 PINMUX_IPSR_DATA(IP14_27_25, CTS1_N), 1635 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0), 1636 PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT), 1637 PINMUX_IPSR_DATA(IP14_27_25, QCLK), 1638 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0), 1639 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0), 1640 PINMUX_IPSR_DATA(IP14_30_28, RTS1_N), 1641 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0), 1642 PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT), 1643 PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE), 1644 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2), 1645 1646 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0), 1647 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0), 1648 PINMUX_IPSR_DATA(IP15_2_0, SCK2), 1649 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0), 1650 PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7), 1651 PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15), 1652 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1), 1653 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0), 1654 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0), 1655 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, TX2, SEL_SCIF2_0), 1656 PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0), 1657 PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16), 1658 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, IIC2_SCL, SEL_IIC2_0), 1659 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, I2C2_SCL, SEL_I2C2_0), 1660 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0), 1661 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0), 1662 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, RX2, SEL_SCIF2_0), 1663 PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1), 1664 PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17), 1665 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, IIC2_SDA, SEL_IIC2_0), 1666 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, I2C2_SDA, SEL_I2C2_0), 1667 PINMUX_IPSR_DATA(IP15_11_9, HSCK0), 1668 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0), 1669 PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4), 1670 PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12), 1671 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2), 1672 PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0), 1673 PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2), 1674 PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18), 1675 PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0), 1676 PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3), 1677 PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19), 1678 PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0), 1679 PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9), 1680 PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4), 1681 PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20), 1682 PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0), 1683 PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9), 1684 PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5), 1685 PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21), 1686 PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0), 1687 PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0), 1688 PINMUX_IPSR_DATA(IP15_22_20, ADICLK), 1689 PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6), 1690 PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22), 1691 PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC), 1692 PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0), 1693 PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2), 1694 PINMUX_IPSR_DATA(IP15_25_23, ADIDATA), 1695 PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7), 1696 PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23), 1697 PINMUX_IPSR_MODSEL_DATA(IP15_25_23, HRX0_C, SEL_SCIFA2_1), 1698 PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0), 1699 PINMUX_IPSR_DATA(IP15_27_26, ADICHS0), 1700 PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5), 1701 PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13), 1702 PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0), 1703 PINMUX_IPSR_DATA(IP15_29_28, ADICHS1), 1704 PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6), 1705 PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14), 1706 1707 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0), 1708 PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT), 1709 PINMUX_IPSR_DATA(IP16_2_0, ADICHS2), 1710 PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP), 1711 PINMUX_IPSR_DATA(IP16_2_0, QPOLA), 1712 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2), 1713 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1), 1714 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0), 1715 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0), 1716 PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2), 1717 PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP), 1718 PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE), 1719 PINMUX_IPSR_DATA(IP16_5_3, QPOLB), 1720 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2), 1721 PINMUX_IPSR_DATA(IP16_6, USB1_PWEN), 1722 PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D), 1723 PINMUX_IPSR_DATA(IP16_7, USB1_OVC), 1724 PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1), 1725 1726 PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0), 1727 PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0), 1728 PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1), 1729 PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1), 1730 1731 PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0), 1732 PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0), 1733 PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1), 1734 PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1), 1735 }; 1736 1737 /* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */ 1738 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) 1739 #define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200) 1740 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) 1741 1742 static const struct sh_pfc_pin pinmux_pins[] = { 1743 PINMUX_GPIO_GP_ALL(), 1744 1745 /* Pins not associated with a GPIO port */ 1746 SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15), 1747 SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15), 1748 SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15), 1749 SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15), 1750 }; 1751 1752 /* - AUDIO CLOCK ------------------------------------------------------------ */ 1753 static const unsigned int audio_clk_a_pins[] = { 1754 /* CLK A */ 1755 RCAR_GP_PIN(4, 25), 1756 }; 1757 static const unsigned int audio_clk_a_mux[] = { 1758 AUDIO_CLKA_MARK, 1759 }; 1760 static const unsigned int audio_clk_b_pins[] = { 1761 /* CLK B */ 1762 RCAR_GP_PIN(4, 26), 1763 }; 1764 static const unsigned int audio_clk_b_mux[] = { 1765 AUDIO_CLKB_MARK, 1766 }; 1767 static const unsigned int audio_clk_c_pins[] = { 1768 /* CLK C */ 1769 RCAR_GP_PIN(5, 27), 1770 }; 1771 static const unsigned int audio_clk_c_mux[] = { 1772 AUDIO_CLKC_MARK, 1773 }; 1774 static const unsigned int audio_clkout_pins[] = { 1775 /* CLK OUT */ 1776 RCAR_GP_PIN(5, 16), 1777 }; 1778 static const unsigned int audio_clkout_mux[] = { 1779 AUDIO_CLKOUT_MARK, 1780 }; 1781 static const unsigned int audio_clkout_b_pins[] = { 1782 /* CLK OUT B */ 1783 RCAR_GP_PIN(0, 23), 1784 }; 1785 static const unsigned int audio_clkout_b_mux[] = { 1786 AUDIO_CLKOUT_B_MARK, 1787 }; 1788 static const unsigned int audio_clkout_c_pins[] = { 1789 /* CLK OUT C */ 1790 RCAR_GP_PIN(5, 27), 1791 }; 1792 static const unsigned int audio_clkout_c_mux[] = { 1793 AUDIO_CLKOUT_C_MARK, 1794 }; 1795 static const unsigned int audio_clkout_d_pins[] = { 1796 /* CLK OUT D */ 1797 RCAR_GP_PIN(5, 20), 1798 }; 1799 static const unsigned int audio_clkout_d_mux[] = { 1800 AUDIO_CLKOUT_D_MARK, 1801 }; 1802 /* - AVB -------------------------------------------------------------------- */ 1803 static const unsigned int avb_link_pins[] = { 1804 RCAR_GP_PIN(3, 11), 1805 }; 1806 static const unsigned int avb_link_mux[] = { 1807 AVB_LINK_MARK, 1808 }; 1809 static const unsigned int avb_magic_pins[] = { 1810 RCAR_GP_PIN(2, 14), 1811 }; 1812 static const unsigned int avb_magic_mux[] = { 1813 AVB_MAGIC_MARK, 1814 }; 1815 static const unsigned int avb_phy_int_pins[] = { 1816 RCAR_GP_PIN(2, 15), 1817 }; 1818 static const unsigned int avb_phy_int_mux[] = { 1819 AVB_PHY_INT_MARK, 1820 }; 1821 static const unsigned int avb_mdio_pins[] = { 1822 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 1823 }; 1824 static const unsigned int avb_mdio_mux[] = { 1825 AVB_MDC_MARK, AVB_MDIO_MARK, 1826 }; 1827 static const unsigned int avb_mii_pins[] = { 1828 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 1829 RCAR_GP_PIN(0, 11), 1830 1831 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1832 RCAR_GP_PIN(2, 2), 1833 1834 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1835 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 10), 1836 RCAR_GP_PIN(3, 12), 1837 }; 1838 static const unsigned int avb_mii_mux[] = { 1839 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, 1840 AVB_TXD3_MARK, 1841 1842 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, 1843 AVB_RXD3_MARK, 1844 1845 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, 1846 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK, 1847 AVB_COL_MARK, 1848 }; 1849 static const unsigned int avb_gmii_pins[] = { 1850 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 1851 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 1852 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 1853 1854 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1855 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 1856 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), 1857 1858 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1859 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16), 1860 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), 1861 RCAR_GP_PIN(3, 12), 1862 }; 1863 static const unsigned int avb_gmii_mux[] = { 1864 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, 1865 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK, 1866 AVB_TXD6_MARK, AVB_TXD7_MARK, 1867 1868 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, 1869 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, 1870 AVB_RXD6_MARK, AVB_RXD7_MARK, 1871 1872 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, 1873 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, 1874 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, 1875 AVB_COL_MARK, 1876 }; 1877 /* - DU RGB ----------------------------------------------------------------- */ 1878 static const unsigned int du_rgb666_pins[] = { 1879 /* R[7:2], G[7:2], B[7:2] */ 1880 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), 1881 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), 1882 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), 1883 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), 1884 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11), 1885 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8), 1886 }; 1887 static const unsigned int du_rgb666_mux[] = { 1888 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK, 1889 DU2_DR3_MARK, DU2_DR2_MARK, 1890 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK, 1891 DU2_DG3_MARK, DU2_DG2_MARK, 1892 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK, 1893 DU2_DB3_MARK, DU2_DB2_MARK, 1894 }; 1895 static const unsigned int du_rgb888_pins[] = { 1896 /* R[7:0], G[7:0], B[7:0] */ 1897 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), 1898 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), 1899 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4), 1900 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7), 1901 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1), 1902 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), 1903 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), 1904 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5), 1905 }; 1906 static const unsigned int du_rgb888_mux[] = { 1907 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK, 1908 DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK, 1909 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK, 1910 DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK, 1911 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK, 1912 DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK, 1913 }; 1914 static const unsigned int du_clk_out_0_pins[] = { 1915 /* CLKOUT */ 1916 RCAR_GP_PIN(5, 2), 1917 }; 1918 static const unsigned int du_clk_out_0_mux[] = { 1919 DU0_DOTCLKOUT_MARK 1920 }; 1921 static const unsigned int du_clk_out_1_pins[] = { 1922 /* CLKOUT */ 1923 RCAR_GP_PIN(5, 3), 1924 }; 1925 static const unsigned int du_clk_out_1_mux[] = { 1926 DU1_DOTCLKOUT_MARK 1927 }; 1928 static const unsigned int du_sync_0_pins[] = { 1929 /* VSYNC, HSYNC, DISP */ 1930 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0), 1931 }; 1932 static const unsigned int du_sync_0_mux[] = { 1933 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, 1934 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK 1935 }; 1936 static const unsigned int du_sync_1_pins[] = { 1937 /* VSYNC, HSYNC, DISP */ 1938 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16), 1939 }; 1940 static const unsigned int du_sync_1_mux[] = { 1941 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, 1942 DU2_DISP_MARK 1943 }; 1944 static const unsigned int du_cde_pins[] = { 1945 /* CDE */ 1946 RCAR_GP_PIN(5, 17), 1947 }; 1948 static const unsigned int du_cde_mux[] = { 1949 DU2_CDE_MARK, 1950 }; 1951 /* - DU0 -------------------------------------------------------------------- */ 1952 static const unsigned int du0_clk_in_pins[] = { 1953 /* CLKIN */ 1954 RCAR_GP_PIN(5, 26), 1955 }; 1956 static const unsigned int du0_clk_in_mux[] = { 1957 DU_DOTCLKIN0_MARK 1958 }; 1959 /* - DU1 -------------------------------------------------------------------- */ 1960 static const unsigned int du1_clk_in_pins[] = { 1961 /* CLKIN */ 1962 RCAR_GP_PIN(5, 27), 1963 }; 1964 static const unsigned int du1_clk_in_mux[] = { 1965 DU_DOTCLKIN1_MARK, 1966 }; 1967 /* - DU2 -------------------------------------------------------------------- */ 1968 static const unsigned int du2_clk_in_pins[] = { 1969 /* CLKIN */ 1970 RCAR_GP_PIN(5, 28), 1971 }; 1972 static const unsigned int du2_clk_in_mux[] = { 1973 DU_DOTCLKIN2_MARK, 1974 }; 1975 /* - ETH -------------------------------------------------------------------- */ 1976 static const unsigned int eth_link_pins[] = { 1977 /* LINK */ 1978 RCAR_GP_PIN(2, 22), 1979 }; 1980 static const unsigned int eth_link_mux[] = { 1981 ETH_LINK_MARK, 1982 }; 1983 static const unsigned int eth_magic_pins[] = { 1984 /* MAGIC */ 1985 RCAR_GP_PIN(2, 27), 1986 }; 1987 static const unsigned int eth_magic_mux[] = { 1988 ETH_MAGIC_MARK, 1989 }; 1990 static const unsigned int eth_mdio_pins[] = { 1991 /* MDC, MDIO */ 1992 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24), 1993 }; 1994 static const unsigned int eth_mdio_mux[] = { 1995 ETH_MDC_MARK, ETH_MDIO_MARK, 1996 }; 1997 static const unsigned int eth_rmii_pins[] = { 1998 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ 1999 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19), 2000 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25), 2001 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23), 2002 }; 2003 static const unsigned int eth_rmii_mux[] = { 2004 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, 2005 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, 2006 }; 2007 /* - HSCIF0 ----------------------------------------------------------------- */ 2008 static const unsigned int hscif0_data_pins[] = { 2009 /* RX, TX */ 2010 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), 2011 }; 2012 static const unsigned int hscif0_data_mux[] = { 2013 HRX0_MARK, HTX0_MARK, 2014 }; 2015 static const unsigned int hscif0_clk_pins[] = { 2016 /* SCK */ 2017 RCAR_GP_PIN(5, 7), 2018 }; 2019 static const unsigned int hscif0_clk_mux[] = { 2020 HSCK0_MARK, 2021 }; 2022 static const unsigned int hscif0_ctrl_pins[] = { 2023 /* RTS, CTS */ 2024 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 2025 }; 2026 static const unsigned int hscif0_ctrl_mux[] = { 2027 HRTS0_N_MARK, HCTS0_N_MARK, 2028 }; 2029 static const unsigned int hscif0_data_b_pins[] = { 2030 /* RX, TX */ 2031 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12), 2032 }; 2033 static const unsigned int hscif0_data_b_mux[] = { 2034 HRX0_B_MARK, HTX0_B_MARK, 2035 }; 2036 static const unsigned int hscif0_ctrl_b_pins[] = { 2037 /* RTS, CTS */ 2038 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), 2039 }; 2040 static const unsigned int hscif0_ctrl_b_mux[] = { 2041 HRTS0_N_B_MARK, HCTS0_N_B_MARK, 2042 }; 2043 static const unsigned int hscif0_data_c_pins[] = { 2044 /* RX, TX */ 2045 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), 2046 }; 2047 static const unsigned int hscif0_data_c_mux[] = { 2048 HRX0_C_MARK, HTX0_C_MARK, 2049 }; 2050 static const unsigned int hscif0_ctrl_c_pins[] = { 2051 /* RTS, CTS */ 2052 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7), 2053 }; 2054 static const unsigned int hscif0_ctrl_c_mux[] = { 2055 HRTS0_N_C_MARK, HCTS0_N_C_MARK, 2056 }; 2057 static const unsigned int hscif0_data_d_pins[] = { 2058 /* RX, TX */ 2059 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 2060 }; 2061 static const unsigned int hscif0_data_d_mux[] = { 2062 HRX0_D_MARK, HTX0_D_MARK, 2063 }; 2064 static const unsigned int hscif0_ctrl_d_pins[] = { 2065 /* RTS, CTS */ 2066 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), 2067 }; 2068 static const unsigned int hscif0_ctrl_d_mux[] = { 2069 HRTS0_N_D_MARK, HCTS0_N_D_MARK, 2070 }; 2071 static const unsigned int hscif0_data_e_pins[] = { 2072 /* RX, TX */ 2073 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 2074 }; 2075 static const unsigned int hscif0_data_e_mux[] = { 2076 HRX0_E_MARK, HTX0_E_MARK, 2077 }; 2078 static const unsigned int hscif0_ctrl_e_pins[] = { 2079 /* RTS, CTS */ 2080 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23), 2081 }; 2082 static const unsigned int hscif0_ctrl_e_mux[] = { 2083 HRTS0_N_E_MARK, HCTS0_N_E_MARK, 2084 }; 2085 static const unsigned int hscif0_data_f_pins[] = { 2086 /* RX, TX */ 2087 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25), 2088 }; 2089 static const unsigned int hscif0_data_f_mux[] = { 2090 HRX0_F_MARK, HTX0_F_MARK, 2091 }; 2092 static const unsigned int hscif0_ctrl_f_pins[] = { 2093 /* RTS, CTS */ 2094 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24), 2095 }; 2096 static const unsigned int hscif0_ctrl_f_mux[] = { 2097 HRTS0_N_F_MARK, HCTS0_N_F_MARK, 2098 }; 2099 /* - HSCIF1 ----------------------------------------------------------------- */ 2100 static const unsigned int hscif1_data_pins[] = { 2101 /* RX, TX */ 2102 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), 2103 }; 2104 static const unsigned int hscif1_data_mux[] = { 2105 HRX1_MARK, HTX1_MARK, 2106 }; 2107 static const unsigned int hscif1_clk_pins[] = { 2108 /* SCK */ 2109 RCAR_GP_PIN(4, 27), 2110 }; 2111 static const unsigned int hscif1_clk_mux[] = { 2112 HSCK1_MARK, 2113 }; 2114 static const unsigned int hscif1_ctrl_pins[] = { 2115 /* RTS, CTS */ 2116 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), 2117 }; 2118 static const unsigned int hscif1_ctrl_mux[] = { 2119 HRTS1_N_MARK, HCTS1_N_MARK, 2120 }; 2121 static const unsigned int hscif1_data_b_pins[] = { 2122 /* RX, TX */ 2123 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18), 2124 }; 2125 static const unsigned int hscif1_data_b_mux[] = { 2126 HRX1_B_MARK, HTX1_B_MARK, 2127 }; 2128 static const unsigned int hscif1_clk_b_pins[] = { 2129 /* SCK */ 2130 RCAR_GP_PIN(1, 28), 2131 }; 2132 static const unsigned int hscif1_clk_b_mux[] = { 2133 HSCK1_B_MARK, 2134 }; 2135 static const unsigned int hscif1_ctrl_b_pins[] = { 2136 /* RTS, CTS */ 2137 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2138 }; 2139 static const unsigned int hscif1_ctrl_b_mux[] = { 2140 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 2141 }; 2142 /* - I2C0 ------------------------------------------------------------------- */ 2143 static const unsigned int i2c0_pins[] = { 2144 /* SCL, SDA */ 2145 PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15), 2146 }; 2147 static const unsigned int i2c0_mux[] = { 2148 I2C0_SCL_MARK, I2C0_SDA_MARK, 2149 }; 2150 /* - I2C1 ------------------------------------------------------------------- */ 2151 static const unsigned int i2c1_pins[] = { 2152 /* SCL, SDA */ 2153 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), 2154 }; 2155 static const unsigned int i2c1_mux[] = { 2156 I2C1_SCL_MARK, I2C1_SDA_MARK, 2157 }; 2158 static const unsigned int i2c1_b_pins[] = { 2159 /* SCL, SDA */ 2160 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 2161 }; 2162 static const unsigned int i2c1_b_mux[] = { 2163 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK, 2164 }; 2165 static const unsigned int i2c1_c_pins[] = { 2166 /* SCL, SDA */ 2167 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), 2168 }; 2169 static const unsigned int i2c1_c_mux[] = { 2170 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK, 2171 }; 2172 /* - I2C2 ------------------------------------------------------------------- */ 2173 static const unsigned int i2c2_pins[] = { 2174 /* SCL, SDA */ 2175 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2176 }; 2177 static const unsigned int i2c2_mux[] = { 2178 I2C2_SCL_MARK, I2C2_SDA_MARK, 2179 }; 2180 static const unsigned int i2c2_b_pins[] = { 2181 /* SCL, SDA */ 2182 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 2183 }; 2184 static const unsigned int i2c2_b_mux[] = { 2185 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK, 2186 }; 2187 static const unsigned int i2c2_c_pins[] = { 2188 /* SCL, SDA */ 2189 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 2190 }; 2191 static const unsigned int i2c2_c_mux[] = { 2192 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK, 2193 }; 2194 static const unsigned int i2c2_d_pins[] = { 2195 /* SCL, SDA */ 2196 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2197 }; 2198 static const unsigned int i2c2_d_mux[] = { 2199 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK, 2200 }; 2201 static const unsigned int i2c2_e_pins[] = { 2202 /* SCL, SDA */ 2203 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), 2204 }; 2205 static const unsigned int i2c2_e_mux[] = { 2206 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK, 2207 }; 2208 /* - I2C3 ------------------------------------------------------------------- */ 2209 static const unsigned int i2c3_pins[] = { 2210 /* SCL, SDA */ 2211 PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15), 2212 }; 2213 static const unsigned int i2c3_mux[] = { 2214 I2C3_SCL_MARK, I2C3_SDA_MARK, 2215 }; 2216 /* - IIC0 (I2C4) ------------------------------------------------------------ */ 2217 static const unsigned int iic0_pins[] = { 2218 /* SCL, SDA */ 2219 PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15), 2220 }; 2221 static const unsigned int iic0_mux[] = { 2222 IIC0_SCL_MARK, IIC0_SDA_MARK, 2223 }; 2224 /* - IIC1 (I2C5) ------------------------------------------------------------ */ 2225 static const unsigned int iic1_pins[] = { 2226 /* SCL, SDA */ 2227 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), 2228 }; 2229 static const unsigned int iic1_mux[] = { 2230 IIC1_SCL_MARK, IIC1_SDA_MARK, 2231 }; 2232 static const unsigned int iic1_b_pins[] = { 2233 /* SCL, SDA */ 2234 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 2235 }; 2236 static const unsigned int iic1_b_mux[] = { 2237 IIC1_SCL_B_MARK, IIC1_SDA_B_MARK, 2238 }; 2239 static const unsigned int iic1_c_pins[] = { 2240 /* SCL, SDA */ 2241 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), 2242 }; 2243 static const unsigned int iic1_c_mux[] = { 2244 IIC1_SCL_C_MARK, IIC1_SDA_C_MARK, 2245 }; 2246 /* - IIC2 (I2C6) ------------------------------------------------------------ */ 2247 static const unsigned int iic2_pins[] = { 2248 /* SCL, SDA */ 2249 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2250 }; 2251 static const unsigned int iic2_mux[] = { 2252 IIC2_SCL_MARK, IIC2_SDA_MARK, 2253 }; 2254 static const unsigned int iic2_b_pins[] = { 2255 /* SCL, SDA */ 2256 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 2257 }; 2258 static const unsigned int iic2_b_mux[] = { 2259 IIC2_SCL_B_MARK, IIC2_SDA_B_MARK, 2260 }; 2261 static const unsigned int iic2_c_pins[] = { 2262 /* SCL, SDA */ 2263 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 2264 }; 2265 static const unsigned int iic2_c_mux[] = { 2266 IIC2_SCL_C_MARK, IIC2_SDA_C_MARK, 2267 }; 2268 static const unsigned int iic2_d_pins[] = { 2269 /* SCL, SDA */ 2270 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2271 }; 2272 static const unsigned int iic2_d_mux[] = { 2273 IIC2_SCL_D_MARK, IIC2_SDA_D_MARK, 2274 }; 2275 static const unsigned int iic2_e_pins[] = { 2276 /* SCL, SDA */ 2277 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), 2278 }; 2279 static const unsigned int iic2_e_mux[] = { 2280 IIC2_SCL_E_MARK, IIC2_SDA_E_MARK, 2281 }; 2282 /* - IIC3 (I2C7) ------------------------------------------------------------ */ 2283 static const unsigned int iic3_pins[] = { 2284 /* SCL, SDA */ 2285 PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15), 2286 }; 2287 static const unsigned int iic3_mux[] = { 2288 IIC3_SCL_MARK, IIC3_SDA_MARK, 2289 }; 2290 /* - INTC ------------------------------------------------------------------- */ 2291 static const unsigned int intc_irq0_pins[] = { 2292 /* IRQ */ 2293 RCAR_GP_PIN(1, 25), 2294 }; 2295 static const unsigned int intc_irq0_mux[] = { 2296 IRQ0_MARK, 2297 }; 2298 static const unsigned int intc_irq1_pins[] = { 2299 /* IRQ */ 2300 RCAR_GP_PIN(1, 27), 2301 }; 2302 static const unsigned int intc_irq1_mux[] = { 2303 IRQ1_MARK, 2304 }; 2305 static const unsigned int intc_irq2_pins[] = { 2306 /* IRQ */ 2307 RCAR_GP_PIN(1, 29), 2308 }; 2309 static const unsigned int intc_irq2_mux[] = { 2310 IRQ2_MARK, 2311 }; 2312 static const unsigned int intc_irq3_pins[] = { 2313 /* IRQ */ 2314 RCAR_GP_PIN(1, 23), 2315 }; 2316 static const unsigned int intc_irq3_mux[] = { 2317 IRQ3_MARK, 2318 }; 2319 /* - MLB+ ------------------------------------------------------------------- */ 2320 static const unsigned int mlb_3pin_pins[] = { 2321 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), 2322 }; 2323 static const unsigned int mlb_3pin_mux[] = { 2324 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, 2325 }; 2326 /* - MMCIF0 ----------------------------------------------------------------- */ 2327 static const unsigned int mmc0_data1_pins[] = { 2328 /* D[0] */ 2329 RCAR_GP_PIN(3, 18), 2330 }; 2331 static const unsigned int mmc0_data1_mux[] = { 2332 MMC0_D0_MARK, 2333 }; 2334 static const unsigned int mmc0_data4_pins[] = { 2335 /* D[0:3] */ 2336 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 2337 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 2338 }; 2339 static const unsigned int mmc0_data4_mux[] = { 2340 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, 2341 }; 2342 static const unsigned int mmc0_data8_pins[] = { 2343 /* D[0:7] */ 2344 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 2345 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 2346 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), 2347 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 2348 }; 2349 static const unsigned int mmc0_data8_mux[] = { 2350 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, 2351 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, 2352 }; 2353 static const unsigned int mmc0_ctrl_pins[] = { 2354 /* CLK, CMD */ 2355 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), 2356 }; 2357 static const unsigned int mmc0_ctrl_mux[] = { 2358 MMC0_CLK_MARK, MMC0_CMD_MARK, 2359 }; 2360 /* - MMCIF1 ----------------------------------------------------------------- */ 2361 static const unsigned int mmc1_data1_pins[] = { 2362 /* D[0] */ 2363 RCAR_GP_PIN(3, 26), 2364 }; 2365 static const unsigned int mmc1_data1_mux[] = { 2366 MMC1_D0_MARK, 2367 }; 2368 static const unsigned int mmc1_data4_pins[] = { 2369 /* D[0:3] */ 2370 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), 2371 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), 2372 }; 2373 static const unsigned int mmc1_data4_mux[] = { 2374 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, 2375 }; 2376 static const unsigned int mmc1_data8_pins[] = { 2377 /* D[0:7] */ 2378 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), 2379 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), 2380 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), 2381 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2382 }; 2383 static const unsigned int mmc1_data8_mux[] = { 2384 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, 2385 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, 2386 }; 2387 static const unsigned int mmc1_ctrl_pins[] = { 2388 /* CLK, CMD */ 2389 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), 2390 }; 2391 static const unsigned int mmc1_ctrl_mux[] = { 2392 MMC1_CLK_MARK, MMC1_CMD_MARK, 2393 }; 2394 /* - MSIOF0 ----------------------------------------------------------------- */ 2395 static const unsigned int msiof0_clk_pins[] = { 2396 /* SCK */ 2397 RCAR_GP_PIN(5, 12), 2398 }; 2399 static const unsigned int msiof0_clk_mux[] = { 2400 MSIOF0_SCK_MARK, 2401 }; 2402 static const unsigned int msiof0_sync_pins[] = { 2403 /* SYNC */ 2404 RCAR_GP_PIN(5, 13), 2405 }; 2406 static const unsigned int msiof0_sync_mux[] = { 2407 MSIOF0_SYNC_MARK, 2408 }; 2409 static const unsigned int msiof0_ss1_pins[] = { 2410 /* SS1 */ 2411 RCAR_GP_PIN(5, 14), 2412 }; 2413 static const unsigned int msiof0_ss1_mux[] = { 2414 MSIOF0_SS1_MARK, 2415 }; 2416 static const unsigned int msiof0_ss2_pins[] = { 2417 /* SS2 */ 2418 RCAR_GP_PIN(5, 16), 2419 }; 2420 static const unsigned int msiof0_ss2_mux[] = { 2421 MSIOF0_SS2_MARK, 2422 }; 2423 static const unsigned int msiof0_rx_pins[] = { 2424 /* RXD */ 2425 RCAR_GP_PIN(5, 17), 2426 }; 2427 static const unsigned int msiof0_rx_mux[] = { 2428 MSIOF0_RXD_MARK, 2429 }; 2430 static const unsigned int msiof0_tx_pins[] = { 2431 /* TXD */ 2432 RCAR_GP_PIN(5, 15), 2433 }; 2434 static const unsigned int msiof0_tx_mux[] = { 2435 MSIOF0_TXD_MARK, 2436 }; 2437 2438 static const unsigned int msiof0_clk_b_pins[] = { 2439 /* SCK */ 2440 RCAR_GP_PIN(1, 23), 2441 }; 2442 static const unsigned int msiof0_clk_b_mux[] = { 2443 MSIOF0_SCK_B_MARK, 2444 }; 2445 static const unsigned int msiof0_ss1_b_pins[] = { 2446 /* SS1 */ 2447 RCAR_GP_PIN(1, 12), 2448 }; 2449 static const unsigned int msiof0_ss1_b_mux[] = { 2450 MSIOF0_SS1_B_MARK, 2451 }; 2452 static const unsigned int msiof0_ss2_b_pins[] = { 2453 /* SS2 */ 2454 RCAR_GP_PIN(1, 10), 2455 }; 2456 static const unsigned int msiof0_ss2_b_mux[] = { 2457 MSIOF0_SS2_B_MARK, 2458 }; 2459 static const unsigned int msiof0_rx_b_pins[] = { 2460 /* RXD */ 2461 RCAR_GP_PIN(1, 29), 2462 }; 2463 static const unsigned int msiof0_rx_b_mux[] = { 2464 MSIOF0_RXD_B_MARK, 2465 }; 2466 static const unsigned int msiof0_tx_b_pins[] = { 2467 /* TXD */ 2468 RCAR_GP_PIN(1, 28), 2469 }; 2470 static const unsigned int msiof0_tx_b_mux[] = { 2471 MSIOF0_TXD_B_MARK, 2472 }; 2473 /* - MSIOF1 ----------------------------------------------------------------- */ 2474 static const unsigned int msiof1_clk_pins[] = { 2475 /* SCK */ 2476 RCAR_GP_PIN(4, 8), 2477 }; 2478 static const unsigned int msiof1_clk_mux[] = { 2479 MSIOF1_SCK_MARK, 2480 }; 2481 static const unsigned int msiof1_sync_pins[] = { 2482 /* SYNC */ 2483 RCAR_GP_PIN(4, 9), 2484 }; 2485 static const unsigned int msiof1_sync_mux[] = { 2486 MSIOF1_SYNC_MARK, 2487 }; 2488 static const unsigned int msiof1_ss1_pins[] = { 2489 /* SS1 */ 2490 RCAR_GP_PIN(4, 10), 2491 }; 2492 static const unsigned int msiof1_ss1_mux[] = { 2493 MSIOF1_SS1_MARK, 2494 }; 2495 static const unsigned int msiof1_ss2_pins[] = { 2496 /* SS2 */ 2497 RCAR_GP_PIN(4, 11), 2498 }; 2499 static const unsigned int msiof1_ss2_mux[] = { 2500 MSIOF1_SS2_MARK, 2501 }; 2502 static const unsigned int msiof1_rx_pins[] = { 2503 /* RXD */ 2504 RCAR_GP_PIN(4, 13), 2505 }; 2506 static const unsigned int msiof1_rx_mux[] = { 2507 MSIOF1_RXD_MARK, 2508 }; 2509 static const unsigned int msiof1_tx_pins[] = { 2510 /* TXD */ 2511 RCAR_GP_PIN(4, 12), 2512 }; 2513 static const unsigned int msiof1_tx_mux[] = { 2514 MSIOF1_TXD_MARK, 2515 }; 2516 2517 static const unsigned int msiof1_clk_b_pins[] = { 2518 /* SCK */ 2519 RCAR_GP_PIN(1, 16), 2520 }; 2521 static const unsigned int msiof1_clk_b_mux[] = { 2522 MSIOF1_SCK_B_MARK, 2523 }; 2524 static const unsigned int msiof1_ss1_b_pins[] = { 2525 /* SS1 */ 2526 RCAR_GP_PIN(0, 18), 2527 }; 2528 static const unsigned int msiof1_ss1_b_mux[] = { 2529 MSIOF1_SS1_B_MARK, 2530 }; 2531 static const unsigned int msiof1_ss2_b_pins[] = { 2532 /* SS2 */ 2533 RCAR_GP_PIN(0, 19), 2534 }; 2535 static const unsigned int msiof1_ss2_b_mux[] = { 2536 MSIOF1_SS2_B_MARK, 2537 }; 2538 static const unsigned int msiof1_rx_b_pins[] = { 2539 /* RXD */ 2540 RCAR_GP_PIN(1, 17), 2541 }; 2542 static const unsigned int msiof1_rx_b_mux[] = { 2543 MSIOF1_RXD_B_MARK, 2544 }; 2545 static const unsigned int msiof1_tx_b_pins[] = { 2546 /* TXD */ 2547 RCAR_GP_PIN(0, 20), 2548 }; 2549 static const unsigned int msiof1_tx_b_mux[] = { 2550 MSIOF1_TXD_B_MARK, 2551 }; 2552 /* - MSIOF2 ----------------------------------------------------------------- */ 2553 static const unsigned int msiof2_clk_pins[] = { 2554 /* SCK */ 2555 RCAR_GP_PIN(0, 27), 2556 }; 2557 static const unsigned int msiof2_clk_mux[] = { 2558 MSIOF2_SCK_MARK, 2559 }; 2560 static const unsigned int msiof2_sync_pins[] = { 2561 /* SYNC */ 2562 RCAR_GP_PIN(0, 26), 2563 }; 2564 static const unsigned int msiof2_sync_mux[] = { 2565 MSIOF2_SYNC_MARK, 2566 }; 2567 static const unsigned int msiof2_ss1_pins[] = { 2568 /* SS1 */ 2569 RCAR_GP_PIN(0, 30), 2570 }; 2571 static const unsigned int msiof2_ss1_mux[] = { 2572 MSIOF2_SS1_MARK, 2573 }; 2574 static const unsigned int msiof2_ss2_pins[] = { 2575 /* SS2 */ 2576 RCAR_GP_PIN(0, 31), 2577 }; 2578 static const unsigned int msiof2_ss2_mux[] = { 2579 MSIOF2_SS2_MARK, 2580 }; 2581 static const unsigned int msiof2_rx_pins[] = { 2582 /* RXD */ 2583 RCAR_GP_PIN(0, 29), 2584 }; 2585 static const unsigned int msiof2_rx_mux[] = { 2586 MSIOF2_RXD_MARK, 2587 }; 2588 static const unsigned int msiof2_tx_pins[] = { 2589 /* TXD */ 2590 RCAR_GP_PIN(0, 28), 2591 }; 2592 static const unsigned int msiof2_tx_mux[] = { 2593 MSIOF2_TXD_MARK, 2594 }; 2595 /* - MSIOF3 ----------------------------------------------------------------- */ 2596 static const unsigned int msiof3_clk_pins[] = { 2597 /* SCK */ 2598 RCAR_GP_PIN(5, 4), 2599 }; 2600 static const unsigned int msiof3_clk_mux[] = { 2601 MSIOF3_SCK_MARK, 2602 }; 2603 static const unsigned int msiof3_sync_pins[] = { 2604 /* SYNC */ 2605 RCAR_GP_PIN(4, 30), 2606 }; 2607 static const unsigned int msiof3_sync_mux[] = { 2608 MSIOF3_SYNC_MARK, 2609 }; 2610 static const unsigned int msiof3_ss1_pins[] = { 2611 /* SS1 */ 2612 RCAR_GP_PIN(4, 31), 2613 }; 2614 static const unsigned int msiof3_ss1_mux[] = { 2615 MSIOF3_SS1_MARK, 2616 }; 2617 static const unsigned int msiof3_ss2_pins[] = { 2618 /* SS2 */ 2619 RCAR_GP_PIN(4, 27), 2620 }; 2621 static const unsigned int msiof3_ss2_mux[] = { 2622 MSIOF3_SS2_MARK, 2623 }; 2624 static const unsigned int msiof3_rx_pins[] = { 2625 /* RXD */ 2626 RCAR_GP_PIN(5, 2), 2627 }; 2628 static const unsigned int msiof3_rx_mux[] = { 2629 MSIOF3_RXD_MARK, 2630 }; 2631 static const unsigned int msiof3_tx_pins[] = { 2632 /* TXD */ 2633 RCAR_GP_PIN(5, 3), 2634 }; 2635 static const unsigned int msiof3_tx_mux[] = { 2636 MSIOF3_TXD_MARK, 2637 }; 2638 2639 static const unsigned int msiof3_clk_b_pins[] = { 2640 /* SCK */ 2641 RCAR_GP_PIN(0, 0), 2642 }; 2643 static const unsigned int msiof3_clk_b_mux[] = { 2644 MSIOF3_SCK_B_MARK, 2645 }; 2646 static const unsigned int msiof3_sync_b_pins[] = { 2647 /* SYNC */ 2648 RCAR_GP_PIN(0, 1), 2649 }; 2650 static const unsigned int msiof3_sync_b_mux[] = { 2651 MSIOF3_SYNC_B_MARK, 2652 }; 2653 static const unsigned int msiof3_rx_b_pins[] = { 2654 /* RXD */ 2655 RCAR_GP_PIN(0, 2), 2656 }; 2657 static const unsigned int msiof3_rx_b_mux[] = { 2658 MSIOF3_RXD_B_MARK, 2659 }; 2660 static const unsigned int msiof3_tx_b_pins[] = { 2661 /* TXD */ 2662 RCAR_GP_PIN(0, 3), 2663 }; 2664 static const unsigned int msiof3_tx_b_mux[] = { 2665 MSIOF3_TXD_B_MARK, 2666 }; 2667 /* - QSPI ------------------------------------------------------------------- */ 2668 static const unsigned int qspi_ctrl_pins[] = { 2669 /* SPCLK, SSL */ 2670 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), 2671 }; 2672 static const unsigned int qspi_ctrl_mux[] = { 2673 SPCLK_MARK, SSL_MARK, 2674 }; 2675 static const unsigned int qspi_data2_pins[] = { 2676 /* MOSI_IO0, MISO_IO1 */ 2677 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 2678 }; 2679 static const unsigned int qspi_data2_mux[] = { 2680 MOSI_IO0_MARK, MISO_IO1_MARK, 2681 }; 2682 static const unsigned int qspi_data4_pins[] = { 2683 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 2684 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 2685 RCAR_GP_PIN(1, 8), 2686 }; 2687 static const unsigned int qspi_data4_mux[] = { 2688 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, 2689 }; 2690 /* - SCIF0 ------------------------------------------------------------------ */ 2691 static const unsigned int scif0_data_pins[] = { 2692 /* RX, TX */ 2693 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), 2694 }; 2695 static const unsigned int scif0_data_mux[] = { 2696 RX0_MARK, TX0_MARK, 2697 }; 2698 static const unsigned int scif0_clk_pins[] = { 2699 /* SCK */ 2700 RCAR_GP_PIN(4, 27), 2701 }; 2702 static const unsigned int scif0_clk_mux[] = { 2703 SCK0_MARK, 2704 }; 2705 static const unsigned int scif0_ctrl_pins[] = { 2706 /* RTS, CTS */ 2707 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), 2708 }; 2709 static const unsigned int scif0_ctrl_mux[] = { 2710 RTS0_N_MARK, CTS0_N_MARK, 2711 }; 2712 static const unsigned int scif0_data_b_pins[] = { 2713 /* RX, TX */ 2714 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 2715 }; 2716 static const unsigned int scif0_data_b_mux[] = { 2717 RX0_B_MARK, TX0_B_MARK, 2718 }; 2719 /* - SCIF1 ------------------------------------------------------------------ */ 2720 static const unsigned int scif1_data_pins[] = { 2721 /* RX, TX */ 2722 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), 2723 }; 2724 static const unsigned int scif1_data_mux[] = { 2725 RX1_MARK, TX1_MARK, 2726 }; 2727 static const unsigned int scif1_clk_pins[] = { 2728 /* SCK */ 2729 RCAR_GP_PIN(4, 20), 2730 }; 2731 static const unsigned int scif1_clk_mux[] = { 2732 SCK1_MARK, 2733 }; 2734 static const unsigned int scif1_ctrl_pins[] = { 2735 /* RTS, CTS */ 2736 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), 2737 }; 2738 static const unsigned int scif1_ctrl_mux[] = { 2739 RTS1_N_MARK, CTS1_N_MARK, 2740 }; 2741 static const unsigned int scif1_data_b_pins[] = { 2742 /* RX, TX */ 2743 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2744 }; 2745 static const unsigned int scif1_data_b_mux[] = { 2746 RX1_B_MARK, TX1_B_MARK, 2747 }; 2748 static const unsigned int scif1_data_c_pins[] = { 2749 /* RX, TX */ 2750 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), 2751 }; 2752 static const unsigned int scif1_data_c_mux[] = { 2753 RX1_C_MARK, TX1_C_MARK, 2754 }; 2755 static const unsigned int scif1_data_d_pins[] = { 2756 /* RX, TX */ 2757 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 2758 }; 2759 static const unsigned int scif1_data_d_mux[] = { 2760 RX1_D_MARK, TX1_D_MARK, 2761 }; 2762 static const unsigned int scif1_clk_d_pins[] = { 2763 /* SCK */ 2764 RCAR_GP_PIN(3, 17), 2765 }; 2766 static const unsigned int scif1_clk_d_mux[] = { 2767 SCK1_D_MARK, 2768 }; 2769 static const unsigned int scif1_data_e_pins[] = { 2770 /* RX, TX */ 2771 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 2772 }; 2773 static const unsigned int scif1_data_e_mux[] = { 2774 RX1_E_MARK, TX1_E_MARK, 2775 }; 2776 static const unsigned int scif1_clk_e_pins[] = { 2777 /* SCK */ 2778 RCAR_GP_PIN(2, 20), 2779 }; 2780 static const unsigned int scif1_clk_e_mux[] = { 2781 SCK1_E_MARK, 2782 }; 2783 /* - SCIF2 ------------------------------------------------------------------ */ 2784 static const unsigned int scif2_data_pins[] = { 2785 /* RX, TX */ 2786 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5), 2787 }; 2788 static const unsigned int scif2_data_mux[] = { 2789 RX2_MARK, TX2_MARK, 2790 }; 2791 static const unsigned int scif2_clk_pins[] = { 2792 /* SCK */ 2793 RCAR_GP_PIN(5, 4), 2794 }; 2795 static const unsigned int scif2_clk_mux[] = { 2796 SCK2_MARK, 2797 }; 2798 static const unsigned int scif2_data_b_pins[] = { 2799 /* RX, TX */ 2800 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 2801 }; 2802 static const unsigned int scif2_data_b_mux[] = { 2803 RX2_B_MARK, TX2_B_MARK, 2804 }; 2805 /* - SCIFA0 ----------------------------------------------------------------- */ 2806 static const unsigned int scifa0_data_pins[] = { 2807 /* RXD, TXD */ 2808 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), 2809 }; 2810 static const unsigned int scifa0_data_mux[] = { 2811 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, 2812 }; 2813 static const unsigned int scifa0_clk_pins[] = { 2814 /* SCK */ 2815 RCAR_GP_PIN(4, 27), 2816 }; 2817 static const unsigned int scifa0_clk_mux[] = { 2818 SCIFA0_SCK_MARK, 2819 }; 2820 static const unsigned int scifa0_ctrl_pins[] = { 2821 /* RTS, CTS */ 2822 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), 2823 }; 2824 static const unsigned int scifa0_ctrl_mux[] = { 2825 SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK, 2826 }; 2827 static const unsigned int scifa0_data_b_pins[] = { 2828 /* RXD, TXD */ 2829 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21), 2830 }; 2831 static const unsigned int scifa0_data_b_mux[] = { 2832 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK 2833 }; 2834 static const unsigned int scifa0_clk_b_pins[] = { 2835 /* SCK */ 2836 RCAR_GP_PIN(1, 19), 2837 }; 2838 static const unsigned int scifa0_clk_b_mux[] = { 2839 SCIFA0_SCK_B_MARK, 2840 }; 2841 static const unsigned int scifa0_ctrl_b_pins[] = { 2842 /* RTS, CTS */ 2843 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), 2844 }; 2845 static const unsigned int scifa0_ctrl_b_mux[] = { 2846 SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK, 2847 }; 2848 /* - SCIFA1 ----------------------------------------------------------------- */ 2849 static const unsigned int scifa1_data_pins[] = { 2850 /* RXD, TXD */ 2851 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), 2852 }; 2853 static const unsigned int scifa1_data_mux[] = { 2854 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, 2855 }; 2856 static const unsigned int scifa1_clk_pins[] = { 2857 /* SCK */ 2858 RCAR_GP_PIN(4, 20), 2859 }; 2860 static const unsigned int scifa1_clk_mux[] = { 2861 SCIFA1_SCK_MARK, 2862 }; 2863 static const unsigned int scifa1_ctrl_pins[] = { 2864 /* RTS, CTS */ 2865 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), 2866 }; 2867 static const unsigned int scifa1_ctrl_mux[] = { 2868 SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK, 2869 }; 2870 static const unsigned int scifa1_data_b_pins[] = { 2871 /* RXD, TXD */ 2872 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21), 2873 }; 2874 static const unsigned int scifa1_data_b_mux[] = { 2875 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, 2876 }; 2877 static const unsigned int scifa1_clk_b_pins[] = { 2878 /* SCK */ 2879 RCAR_GP_PIN(0, 23), 2880 }; 2881 static const unsigned int scifa1_clk_b_mux[] = { 2882 SCIFA1_SCK_B_MARK, 2883 }; 2884 static const unsigned int scifa1_ctrl_b_pins[] = { 2885 /* RTS, CTS */ 2886 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25), 2887 }; 2888 static const unsigned int scifa1_ctrl_b_mux[] = { 2889 SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK, 2890 }; 2891 static const unsigned int scifa1_data_c_pins[] = { 2892 /* RXD, TXD */ 2893 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 2894 }; 2895 static const unsigned int scifa1_data_c_mux[] = { 2896 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, 2897 }; 2898 static const unsigned int scifa1_clk_c_pins[] = { 2899 /* SCK */ 2900 RCAR_GP_PIN(0, 8), 2901 }; 2902 static const unsigned int scifa1_clk_c_mux[] = { 2903 SCIFA1_SCK_C_MARK, 2904 }; 2905 static const unsigned int scifa1_ctrl_c_pins[] = { 2906 /* RTS, CTS */ 2907 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), 2908 }; 2909 static const unsigned int scifa1_ctrl_c_mux[] = { 2910 SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK, 2911 }; 2912 static const unsigned int scifa1_data_d_pins[] = { 2913 /* RXD, TXD */ 2914 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 2915 }; 2916 static const unsigned int scifa1_data_d_mux[] = { 2917 SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK, 2918 }; 2919 static const unsigned int scifa1_clk_d_pins[] = { 2920 /* SCK */ 2921 RCAR_GP_PIN(2, 10), 2922 }; 2923 static const unsigned int scifa1_clk_d_mux[] = { 2924 SCIFA1_SCK_D_MARK, 2925 }; 2926 static const unsigned int scifa1_ctrl_d_pins[] = { 2927 /* RTS, CTS */ 2928 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 2929 }; 2930 static const unsigned int scifa1_ctrl_d_mux[] = { 2931 SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK, 2932 }; 2933 /* - SCIFA2 ----------------------------------------------------------------- */ 2934 static const unsigned int scifa2_data_pins[] = { 2935 /* RXD, TXD */ 2936 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2937 }; 2938 static const unsigned int scifa2_data_mux[] = { 2939 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, 2940 }; 2941 static const unsigned int scifa2_clk_pins[] = { 2942 /* SCK */ 2943 RCAR_GP_PIN(5, 4), 2944 }; 2945 static const unsigned int scifa2_clk_mux[] = { 2946 SCIFA2_SCK_MARK, 2947 }; 2948 static const unsigned int scifa2_ctrl_pins[] = { 2949 /* RTS, CTS */ 2950 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), 2951 }; 2952 static const unsigned int scifa2_ctrl_mux[] = { 2953 SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK, 2954 }; 2955 static const unsigned int scifa2_data_b_pins[] = { 2956 /* RXD, TXD */ 2957 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), 2958 }; 2959 static const unsigned int scifa2_data_b_mux[] = { 2960 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, 2961 }; 2962 static const unsigned int scifa2_data_c_pins[] = { 2963 /* RXD, TXD */ 2964 RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), 2965 }; 2966 static const unsigned int scifa2_data_c_mux[] = { 2967 SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK, 2968 }; 2969 static const unsigned int scifa2_clk_c_pins[] = { 2970 /* SCK */ 2971 RCAR_GP_PIN(5, 29), 2972 }; 2973 static const unsigned int scifa2_clk_c_mux[] = { 2974 SCIFA2_SCK_C_MARK, 2975 }; 2976 /* - SCIFB0 ----------------------------------------------------------------- */ 2977 static const unsigned int scifb0_data_pins[] = { 2978 /* RXD, TXD */ 2979 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 2980 }; 2981 static const unsigned int scifb0_data_mux[] = { 2982 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, 2983 }; 2984 static const unsigned int scifb0_clk_pins[] = { 2985 /* SCK */ 2986 RCAR_GP_PIN(4, 8), 2987 }; 2988 static const unsigned int scifb0_clk_mux[] = { 2989 SCIFB0_SCK_MARK, 2990 }; 2991 static const unsigned int scifb0_ctrl_pins[] = { 2992 /* RTS, CTS */ 2993 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), 2994 }; 2995 static const unsigned int scifb0_ctrl_mux[] = { 2996 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, 2997 }; 2998 static const unsigned int scifb0_data_b_pins[] = { 2999 /* RXD, TXD */ 3000 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3001 }; 3002 static const unsigned int scifb0_data_b_mux[] = { 3003 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK, 3004 }; 3005 static const unsigned int scifb0_clk_b_pins[] = { 3006 /* SCK */ 3007 RCAR_GP_PIN(3, 9), 3008 }; 3009 static const unsigned int scifb0_clk_b_mux[] = { 3010 SCIFB0_SCK_B_MARK, 3011 }; 3012 static const unsigned int scifb0_ctrl_b_pins[] = { 3013 /* RTS, CTS */ 3014 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 3015 }; 3016 static const unsigned int scifb0_ctrl_b_mux[] = { 3017 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK, 3018 }; 3019 static const unsigned int scifb0_data_c_pins[] = { 3020 /* RXD, TXD */ 3021 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3022 }; 3023 static const unsigned int scifb0_data_c_mux[] = { 3024 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK, 3025 }; 3026 /* - SCIFB1 ----------------------------------------------------------------- */ 3027 static const unsigned int scifb1_data_pins[] = { 3028 /* RXD, TXD */ 3029 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 3030 }; 3031 static const unsigned int scifb1_data_mux[] = { 3032 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, 3033 }; 3034 static const unsigned int scifb1_clk_pins[] = { 3035 /* SCK */ 3036 RCAR_GP_PIN(4, 14), 3037 }; 3038 static const unsigned int scifb1_clk_mux[] = { 3039 SCIFB1_SCK_MARK, 3040 }; 3041 static const unsigned int scifb1_ctrl_pins[] = { 3042 /* RTS, CTS */ 3043 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), 3044 }; 3045 static const unsigned int scifb1_ctrl_mux[] = { 3046 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK, 3047 }; 3048 static const unsigned int scifb1_data_b_pins[] = { 3049 /* RXD, TXD */ 3050 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3051 }; 3052 static const unsigned int scifb1_data_b_mux[] = { 3053 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK, 3054 }; 3055 static const unsigned int scifb1_clk_b_pins[] = { 3056 /* SCK */ 3057 RCAR_GP_PIN(3, 1), 3058 }; 3059 static const unsigned int scifb1_clk_b_mux[] = { 3060 SCIFB1_SCK_B_MARK, 3061 }; 3062 static const unsigned int scifb1_ctrl_b_pins[] = { 3063 /* RTS, CTS */ 3064 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4), 3065 }; 3066 static const unsigned int scifb1_ctrl_b_mux[] = { 3067 SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK, 3068 }; 3069 static const unsigned int scifb1_data_c_pins[] = { 3070 /* RXD, TXD */ 3071 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3072 }; 3073 static const unsigned int scifb1_data_c_mux[] = { 3074 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK, 3075 }; 3076 static const unsigned int scifb1_data_d_pins[] = { 3077 /* RXD, TXD */ 3078 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), 3079 }; 3080 static const unsigned int scifb1_data_d_mux[] = { 3081 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK, 3082 }; 3083 static const unsigned int scifb1_data_e_pins[] = { 3084 /* RXD, TXD */ 3085 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), 3086 }; 3087 static const unsigned int scifb1_data_e_mux[] = { 3088 SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK, 3089 }; 3090 static const unsigned int scifb1_clk_e_pins[] = { 3091 /* SCK */ 3092 RCAR_GP_PIN(3, 17), 3093 }; 3094 static const unsigned int scifb1_clk_e_mux[] = { 3095 SCIFB1_SCK_E_MARK, 3096 }; 3097 static const unsigned int scifb1_data_f_pins[] = { 3098 /* RXD, TXD */ 3099 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3100 }; 3101 static const unsigned int scifb1_data_f_mux[] = { 3102 SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK, 3103 }; 3104 static const unsigned int scifb1_data_g_pins[] = { 3105 /* RXD, TXD */ 3106 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 3107 }; 3108 static const unsigned int scifb1_data_g_mux[] = { 3109 SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK, 3110 }; 3111 static const unsigned int scifb1_clk_g_pins[] = { 3112 /* SCK */ 3113 RCAR_GP_PIN(2, 20), 3114 }; 3115 static const unsigned int scifb1_clk_g_mux[] = { 3116 SCIFB1_SCK_G_MARK, 3117 }; 3118 /* - SCIFB2 ----------------------------------------------------------------- */ 3119 static const unsigned int scifb2_data_pins[] = { 3120 /* RXD, TXD */ 3121 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), 3122 }; 3123 static const unsigned int scifb2_data_mux[] = { 3124 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, 3125 }; 3126 static const unsigned int scifb2_clk_pins[] = { 3127 /* SCK */ 3128 RCAR_GP_PIN(4, 21), 3129 }; 3130 static const unsigned int scifb2_clk_mux[] = { 3131 SCIFB2_SCK_MARK, 3132 }; 3133 static const unsigned int scifb2_ctrl_pins[] = { 3134 /* RTS, CTS */ 3135 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), 3136 }; 3137 static const unsigned int scifb2_ctrl_mux[] = { 3138 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, 3139 }; 3140 static const unsigned int scifb2_data_b_pins[] = { 3141 /* RXD, TXD */ 3142 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30), 3143 }; 3144 static const unsigned int scifb2_data_b_mux[] = { 3145 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK, 3146 }; 3147 static const unsigned int scifb2_clk_b_pins[] = { 3148 /* SCK */ 3149 RCAR_GP_PIN(0, 31), 3150 }; 3151 static const unsigned int scifb2_clk_b_mux[] = { 3152 SCIFB2_SCK_B_MARK, 3153 }; 3154 static const unsigned int scifb2_ctrl_b_pins[] = { 3155 /* RTS, CTS */ 3156 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27), 3157 }; 3158 static const unsigned int scifb2_ctrl_b_mux[] = { 3159 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK, 3160 }; 3161 static const unsigned int scifb2_data_c_pins[] = { 3162 /* RXD, TXD */ 3163 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3164 }; 3165 static const unsigned int scifb2_data_c_mux[] = { 3166 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, 3167 }; 3168 /* - SDHI0 ------------------------------------------------------------------ */ 3169 static const unsigned int sdhi0_data1_pins[] = { 3170 /* D0 */ 3171 RCAR_GP_PIN(3, 2), 3172 }; 3173 static const unsigned int sdhi0_data1_mux[] = { 3174 SD0_DAT0_MARK, 3175 }; 3176 static const unsigned int sdhi0_data4_pins[] = { 3177 /* D[0:3] */ 3178 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3179 }; 3180 static const unsigned int sdhi0_data4_mux[] = { 3181 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, 3182 }; 3183 static const unsigned int sdhi0_ctrl_pins[] = { 3184 /* CLK, CMD */ 3185 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3186 }; 3187 static const unsigned int sdhi0_ctrl_mux[] = { 3188 SD0_CLK_MARK, SD0_CMD_MARK, 3189 }; 3190 static const unsigned int sdhi0_cd_pins[] = { 3191 /* CD */ 3192 RCAR_GP_PIN(3, 6), 3193 }; 3194 static const unsigned int sdhi0_cd_mux[] = { 3195 SD0_CD_MARK, 3196 }; 3197 static const unsigned int sdhi0_wp_pins[] = { 3198 /* WP */ 3199 RCAR_GP_PIN(3, 7), 3200 }; 3201 static const unsigned int sdhi0_wp_mux[] = { 3202 SD0_WP_MARK, 3203 }; 3204 /* - SDHI1 ------------------------------------------------------------------ */ 3205 static const unsigned int sdhi1_data1_pins[] = { 3206 /* D0 */ 3207 RCAR_GP_PIN(3, 10), 3208 }; 3209 static const unsigned int sdhi1_data1_mux[] = { 3210 SD1_DAT0_MARK, 3211 }; 3212 static const unsigned int sdhi1_data4_pins[] = { 3213 /* D[0:3] */ 3214 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 3215 }; 3216 static const unsigned int sdhi1_data4_mux[] = { 3217 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, 3218 }; 3219 static const unsigned int sdhi1_ctrl_pins[] = { 3220 /* CLK, CMD */ 3221 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3222 }; 3223 static const unsigned int sdhi1_ctrl_mux[] = { 3224 SD1_CLK_MARK, SD1_CMD_MARK, 3225 }; 3226 static const unsigned int sdhi1_cd_pins[] = { 3227 /* CD */ 3228 RCAR_GP_PIN(3, 14), 3229 }; 3230 static const unsigned int sdhi1_cd_mux[] = { 3231 SD1_CD_MARK, 3232 }; 3233 static const unsigned int sdhi1_wp_pins[] = { 3234 /* WP */ 3235 RCAR_GP_PIN(3, 15), 3236 }; 3237 static const unsigned int sdhi1_wp_mux[] = { 3238 SD1_WP_MARK, 3239 }; 3240 /* - SDHI2 ------------------------------------------------------------------ */ 3241 static const unsigned int sdhi2_data1_pins[] = { 3242 /* D0 */ 3243 RCAR_GP_PIN(3, 18), 3244 }; 3245 static const unsigned int sdhi2_data1_mux[] = { 3246 SD2_DAT0_MARK, 3247 }; 3248 static const unsigned int sdhi2_data4_pins[] = { 3249 /* D[0:3] */ 3250 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), 3251 }; 3252 static const unsigned int sdhi2_data4_mux[] = { 3253 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, 3254 }; 3255 static const unsigned int sdhi2_ctrl_pins[] = { 3256 /* CLK, CMD */ 3257 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), 3258 }; 3259 static const unsigned int sdhi2_ctrl_mux[] = { 3260 SD2_CLK_MARK, SD2_CMD_MARK, 3261 }; 3262 static const unsigned int sdhi2_cd_pins[] = { 3263 /* CD */ 3264 RCAR_GP_PIN(3, 22), 3265 }; 3266 static const unsigned int sdhi2_cd_mux[] = { 3267 SD2_CD_MARK, 3268 }; 3269 static const unsigned int sdhi2_wp_pins[] = { 3270 /* WP */ 3271 RCAR_GP_PIN(3, 23), 3272 }; 3273 static const unsigned int sdhi2_wp_mux[] = { 3274 SD2_WP_MARK, 3275 }; 3276 /* - SDHI3 ------------------------------------------------------------------ */ 3277 static const unsigned int sdhi3_data1_pins[] = { 3278 /* D0 */ 3279 RCAR_GP_PIN(3, 26), 3280 }; 3281 static const unsigned int sdhi3_data1_mux[] = { 3282 SD3_DAT0_MARK, 3283 }; 3284 static const unsigned int sdhi3_data4_pins[] = { 3285 /* D[0:3] */ 3286 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), 3287 }; 3288 static const unsigned int sdhi3_data4_mux[] = { 3289 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, 3290 }; 3291 static const unsigned int sdhi3_ctrl_pins[] = { 3292 /* CLK, CMD */ 3293 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), 3294 }; 3295 static const unsigned int sdhi3_ctrl_mux[] = { 3296 SD3_CLK_MARK, SD3_CMD_MARK, 3297 }; 3298 static const unsigned int sdhi3_cd_pins[] = { 3299 /* CD */ 3300 RCAR_GP_PIN(3, 30), 3301 }; 3302 static const unsigned int sdhi3_cd_mux[] = { 3303 SD3_CD_MARK, 3304 }; 3305 static const unsigned int sdhi3_wp_pins[] = { 3306 /* WP */ 3307 RCAR_GP_PIN(3, 31), 3308 }; 3309 static const unsigned int sdhi3_wp_mux[] = { 3310 SD3_WP_MARK, 3311 }; 3312 /* - SSI -------------------------------------------------------------------- */ 3313 static const unsigned int ssi0_data_pins[] = { 3314 /* SDATA0 */ 3315 RCAR_GP_PIN(4, 5), 3316 }; 3317 static const unsigned int ssi0_data_mux[] = { 3318 SSI_SDATA0_MARK, 3319 }; 3320 static const unsigned int ssi0129_ctrl_pins[] = { 3321 /* SCK, WS */ 3322 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), 3323 }; 3324 static const unsigned int ssi0129_ctrl_mux[] = { 3325 SSI_SCK0129_MARK, SSI_WS0129_MARK, 3326 }; 3327 static const unsigned int ssi1_data_pins[] = { 3328 /* SDATA1 */ 3329 RCAR_GP_PIN(4, 6), 3330 }; 3331 static const unsigned int ssi1_data_mux[] = { 3332 SSI_SDATA1_MARK, 3333 }; 3334 static const unsigned int ssi1_ctrl_pins[] = { 3335 /* SCK, WS */ 3336 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24), 3337 }; 3338 static const unsigned int ssi1_ctrl_mux[] = { 3339 SSI_SCK1_MARK, SSI_WS1_MARK, 3340 }; 3341 static const unsigned int ssi2_data_pins[] = { 3342 /* SDATA2 */ 3343 RCAR_GP_PIN(4, 7), 3344 }; 3345 static const unsigned int ssi2_data_mux[] = { 3346 SSI_SDATA2_MARK, 3347 }; 3348 static const unsigned int ssi2_ctrl_pins[] = { 3349 /* SCK, WS */ 3350 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17), 3351 }; 3352 static const unsigned int ssi2_ctrl_mux[] = { 3353 SSI_SCK2_MARK, SSI_WS2_MARK, 3354 }; 3355 static const unsigned int ssi3_data_pins[] = { 3356 /* SDATA3 */ 3357 RCAR_GP_PIN(4, 10), 3358 }; 3359 static const unsigned int ssi3_data_mux[] = { 3360 SSI_SDATA3_MARK 3361 }; 3362 static const unsigned int ssi34_ctrl_pins[] = { 3363 /* SCK, WS */ 3364 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), 3365 }; 3366 static const unsigned int ssi34_ctrl_mux[] = { 3367 SSI_SCK34_MARK, SSI_WS34_MARK, 3368 }; 3369 static const unsigned int ssi4_data_pins[] = { 3370 /* SDATA4 */ 3371 RCAR_GP_PIN(4, 13), 3372 }; 3373 static const unsigned int ssi4_data_mux[] = { 3374 SSI_SDATA4_MARK, 3375 }; 3376 static const unsigned int ssi4_ctrl_pins[] = { 3377 /* SCK, WS */ 3378 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3379 }; 3380 static const unsigned int ssi4_ctrl_mux[] = { 3381 SSI_SCK4_MARK, SSI_WS4_MARK, 3382 }; 3383 static const unsigned int ssi5_pins[] = { 3384 /* SDATA5, SCK, WS */ 3385 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), 3386 }; 3387 static const unsigned int ssi5_mux[] = { 3388 SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK, 3389 }; 3390 static const unsigned int ssi5_b_pins[] = { 3391 /* SDATA5, SCK, WS */ 3392 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3393 }; 3394 static const unsigned int ssi5_b_mux[] = { 3395 SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK 3396 }; 3397 static const unsigned int ssi5_c_pins[] = { 3398 /* SDATA5, SCK, WS */ 3399 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3400 }; 3401 static const unsigned int ssi5_c_mux[] = { 3402 SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK, 3403 }; 3404 static const unsigned int ssi6_pins[] = { 3405 /* SDATA6, SCK, WS */ 3406 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), 3407 }; 3408 static const unsigned int ssi6_mux[] = { 3409 SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK, 3410 }; 3411 static const unsigned int ssi6_b_pins[] = { 3412 /* SDATA6, SCK, WS */ 3413 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27), 3414 }; 3415 static const unsigned int ssi6_b_mux[] = { 3416 SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK, 3417 }; 3418 static const unsigned int ssi7_data_pins[] = { 3419 /* SDATA7 */ 3420 RCAR_GP_PIN(4, 22), 3421 }; 3422 static const unsigned int ssi7_data_mux[] = { 3423 SSI_SDATA7_MARK, 3424 }; 3425 static const unsigned int ssi7_b_data_pins[] = { 3426 /* SDATA7 */ 3427 RCAR_GP_PIN(4, 22), 3428 }; 3429 static const unsigned int ssi7_b_data_mux[] = { 3430 SSI_SDATA7_B_MARK, 3431 }; 3432 static const unsigned int ssi7_c_data_pins[] = { 3433 /* SDATA7 */ 3434 RCAR_GP_PIN(1, 26), 3435 }; 3436 static const unsigned int ssi7_c_data_mux[] = { 3437 SSI_SDATA7_C_MARK, 3438 }; 3439 static const unsigned int ssi78_ctrl_pins[] = { 3440 /* SCK, WS */ 3441 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), 3442 }; 3443 static const unsigned int ssi78_ctrl_mux[] = { 3444 SSI_SCK78_MARK, SSI_WS78_MARK, 3445 }; 3446 static const unsigned int ssi78_b_ctrl_pins[] = { 3447 /* SCK, WS */ 3448 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24), 3449 }; 3450 static const unsigned int ssi78_b_ctrl_mux[] = { 3451 SSI_SCK78_B_MARK, SSI_WS78_B_MARK, 3452 }; 3453 static const unsigned int ssi78_c_ctrl_pins[] = { 3454 /* SCK, WS */ 3455 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25), 3456 }; 3457 static const unsigned int ssi78_c_ctrl_mux[] = { 3458 SSI_SCK78_C_MARK, SSI_WS78_C_MARK, 3459 }; 3460 static const unsigned int ssi8_data_pins[] = { 3461 /* SDATA8 */ 3462 RCAR_GP_PIN(4, 23), 3463 }; 3464 static const unsigned int ssi8_data_mux[] = { 3465 SSI_SDATA8_MARK, 3466 }; 3467 static const unsigned int ssi8_b_data_pins[] = { 3468 /* SDATA8 */ 3469 RCAR_GP_PIN(4, 23), 3470 }; 3471 static const unsigned int ssi8_b_data_mux[] = { 3472 SSI_SDATA8_B_MARK, 3473 }; 3474 static const unsigned int ssi8_c_data_pins[] = { 3475 /* SDATA8 */ 3476 RCAR_GP_PIN(1, 27), 3477 }; 3478 static const unsigned int ssi8_c_data_mux[] = { 3479 SSI_SDATA8_C_MARK, 3480 }; 3481 static const unsigned int ssi9_data_pins[] = { 3482 /* SDATA9 */ 3483 RCAR_GP_PIN(4, 24), 3484 }; 3485 static const unsigned int ssi9_data_mux[] = { 3486 SSI_SDATA9_MARK, 3487 }; 3488 static const unsigned int ssi9_ctrl_pins[] = { 3489 /* SCK, WS */ 3490 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), 3491 }; 3492 static const unsigned int ssi9_ctrl_mux[] = { 3493 SSI_SCK9_MARK, SSI_WS9_MARK, 3494 }; 3495 /* - TPU0 ------------------------------------------------------------------- */ 3496 static const unsigned int tpu0_to0_pins[] = { 3497 /* TO */ 3498 RCAR_GP_PIN(0, 20), 3499 }; 3500 static const unsigned int tpu0_to0_mux[] = { 3501 TPU0TO0_MARK, 3502 }; 3503 static const unsigned int tpu0_to1_pins[] = { 3504 /* TO */ 3505 RCAR_GP_PIN(0, 21), 3506 }; 3507 static const unsigned int tpu0_to1_mux[] = { 3508 TPU0TO1_MARK, 3509 }; 3510 static const unsigned int tpu0_to2_pins[] = { 3511 /* TO */ 3512 RCAR_GP_PIN(0, 22), 3513 }; 3514 static const unsigned int tpu0_to2_mux[] = { 3515 TPU0TO2_MARK, 3516 }; 3517 static const unsigned int tpu0_to3_pins[] = { 3518 /* TO */ 3519 RCAR_GP_PIN(0, 23), 3520 }; 3521 static const unsigned int tpu0_to3_mux[] = { 3522 TPU0TO3_MARK, 3523 }; 3524 /* - USB0 ------------------------------------------------------------------- */ 3525 static const unsigned int usb0_pins[] = { 3526 /* PWEN, OVC/VBUS */ 3527 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), 3528 }; 3529 static const unsigned int usb0_mux[] = { 3530 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, 3531 }; 3532 static const unsigned int usb0_ovc_vbus_pins[] = { 3533 /* OVC/VBUS */ 3534 RCAR_GP_PIN(5, 19), 3535 }; 3536 static const unsigned int usb0_ovc_vbus_mux[] = { 3537 USB0_OVC_VBUS_MARK, 3538 }; 3539 /* - USB1 ------------------------------------------------------------------- */ 3540 static const unsigned int usb1_pins[] = { 3541 /* PWEN, OVC */ 3542 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), 3543 }; 3544 static const unsigned int usb1_mux[] = { 3545 USB1_PWEN_MARK, USB1_OVC_MARK, 3546 }; 3547 /* - USB2 ------------------------------------------------------------------- */ 3548 static const unsigned int usb2_pins[] = { 3549 /* PWEN, OVC */ 3550 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), 3551 }; 3552 static const unsigned int usb2_mux[] = { 3553 USB2_PWEN_MARK, USB2_OVC_MARK, 3554 }; 3555 3556 union vin_data { 3557 unsigned int data24[24]; 3558 unsigned int data20[20]; 3559 unsigned int data16[16]; 3560 unsigned int data12[12]; 3561 unsigned int data10[10]; 3562 unsigned int data8[8]; 3563 unsigned int data4[4]; 3564 }; 3565 3566 #define VIN_DATA_PIN_GROUP(n, s) \ 3567 { \ 3568 .name = #n#s, \ 3569 .pins = n##_pins.data##s, \ 3570 .mux = n##_mux.data##s, \ 3571 .nr_pins = ARRAY_SIZE(n##_pins.data##s), \ 3572 } 3573 3574 /* - VIN0 ------------------------------------------------------------------- */ 3575 static const union vin_data vin0_data_pins = { 3576 .data24 = { 3577 /* B */ 3578 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), 3579 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 3580 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), 3581 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 3582 /* G */ 3583 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 3584 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3585 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 3586 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3587 /* R */ 3588 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3589 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3590 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3591 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), 3592 }, 3593 }; 3594 static const union vin_data vin0_data_mux = { 3595 .data24 = { 3596 /* B */ 3597 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, 3598 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 3599 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 3600 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 3601 /* G */ 3602 VI0_G0_MARK, VI0_G1_MARK, 3603 VI0_G2_MARK, VI0_G3_MARK, 3604 VI0_G4_MARK, VI0_G5_MARK, 3605 VI0_G6_MARK, VI0_G7_MARK, 3606 /* R */ 3607 VI0_R0_MARK, VI0_R1_MARK, 3608 VI0_R2_MARK, VI0_R3_MARK, 3609 VI0_R4_MARK, VI0_R5_MARK, 3610 VI0_R6_MARK, VI0_R7_MARK, 3611 }, 3612 }; 3613 static const unsigned int vin0_data18_pins[] = { 3614 /* B */ 3615 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 3616 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), 3617 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 3618 /* G */ 3619 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3620 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 3621 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3622 /* R */ 3623 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3624 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3625 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), 3626 }; 3627 static const unsigned int vin0_data18_mux[] = { 3628 /* B */ 3629 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, 3630 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 3631 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 3632 /* G */ 3633 VI0_G2_MARK, VI0_G3_MARK, 3634 VI0_G4_MARK, VI0_G5_MARK, 3635 VI0_G6_MARK, VI0_G7_MARK, 3636 /* R */ 3637 VI0_R2_MARK, VI0_R3_MARK, 3638 VI0_R4_MARK, VI0_R5_MARK, 3639 VI0_R6_MARK, VI0_R7_MARK, 3640 }; 3641 static const unsigned int vin0_sync_pins[] = { 3642 RCAR_GP_PIN(0, 12), /* HSYNC */ 3643 RCAR_GP_PIN(0, 13), /* VSYNC */ 3644 }; 3645 static const unsigned int vin0_sync_mux[] = { 3646 VI0_HSYNC_N_MARK, 3647 VI0_VSYNC_N_MARK, 3648 }; 3649 static const unsigned int vin0_field_pins[] = { 3650 RCAR_GP_PIN(0, 15), 3651 }; 3652 static const unsigned int vin0_field_mux[] = { 3653 VI0_FIELD_MARK, 3654 }; 3655 static const unsigned int vin0_clkenb_pins[] = { 3656 RCAR_GP_PIN(0, 14), 3657 }; 3658 static const unsigned int vin0_clkenb_mux[] = { 3659 VI0_CLKENB_MARK, 3660 }; 3661 static const unsigned int vin0_clk_pins[] = { 3662 RCAR_GP_PIN(2, 0), 3663 }; 3664 static const unsigned int vin0_clk_mux[] = { 3665 VI0_CLK_MARK, 3666 }; 3667 /* - VIN1 ------------------------------------------------------------------- */ 3668 static const union vin_data vin1_data_pins = { 3669 .data24 = { 3670 /* B */ 3671 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 3672 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 3673 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 3674 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), 3675 /* G */ 3676 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 3677 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 3678 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), 3679 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), 3680 /* R */ 3681 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), 3682 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), 3683 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 3684 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), 3685 }, 3686 }; 3687 static const union vin_data vin1_data_mux = { 3688 .data24 = { 3689 /* B */ 3690 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, 3691 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, 3692 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, 3693 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, 3694 /* G */ 3695 VI1_G0_MARK, VI1_G1_MARK, 3696 VI1_G2_MARK, VI1_G3_MARK, 3697 VI1_G4_MARK, VI1_G5_MARK, 3698 VI1_G6_MARK, VI1_G7_MARK, 3699 /* R */ 3700 VI1_R0_MARK, VI1_R1_MARK, 3701 VI1_R2_MARK, VI1_R3_MARK, 3702 VI1_R4_MARK, VI1_R5_MARK, 3703 VI1_R6_MARK, VI1_R7_MARK, 3704 }, 3705 }; 3706 static const unsigned int vin1_data18_pins[] = { 3707 /* B */ 3708 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 3709 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 3710 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), 3711 /* G */ 3712 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 3713 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), 3714 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), 3715 /* R */ 3716 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), 3717 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), 3718 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), 3719 }; 3720 static const unsigned int vin1_data18_mux[] = { 3721 /* B */ 3722 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, 3723 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, 3724 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, 3725 /* G */ 3726 VI1_G2_MARK, VI1_G3_MARK, 3727 VI1_G4_MARK, VI1_G5_MARK, 3728 VI1_G6_MARK, VI1_G7_MARK, 3729 /* R */ 3730 VI1_R2_MARK, VI1_R3_MARK, 3731 VI1_R4_MARK, VI1_R5_MARK, 3732 VI1_R6_MARK, VI1_R7_MARK, 3733 }; 3734 static const unsigned int vin1_sync_pins[] = { 3735 RCAR_GP_PIN(1, 24), /* HSYNC */ 3736 RCAR_GP_PIN(1, 25), /* VSYNC */ 3737 }; 3738 static const unsigned int vin1_sync_mux[] = { 3739 VI1_HSYNC_N_MARK, 3740 VI1_VSYNC_N_MARK, 3741 }; 3742 static const unsigned int vin1_field_pins[] = { 3743 RCAR_GP_PIN(1, 13), 3744 }; 3745 static const unsigned int vin1_field_mux[] = { 3746 VI1_FIELD_MARK, 3747 }; 3748 static const unsigned int vin1_clkenb_pins[] = { 3749 RCAR_GP_PIN(1, 26), 3750 }; 3751 static const unsigned int vin1_clkenb_mux[] = { 3752 VI1_CLKENB_MARK, 3753 }; 3754 static const unsigned int vin1_clk_pins[] = { 3755 RCAR_GP_PIN(2, 9), 3756 }; 3757 static const unsigned int vin1_clk_mux[] = { 3758 VI1_CLK_MARK, 3759 }; 3760 /* - VIN2 ----------------------------------------------------------------- */ 3761 static const union vin_data vin2_data_pins = { 3762 .data24 = { 3763 /* B */ 3764 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 3765 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3766 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3767 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3768 /* G */ 3769 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), 3770 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), 3771 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3772 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3773 /* R */ 3774 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 3775 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 3776 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 3777 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), 3778 }, 3779 }; 3780 static const union vin_data vin2_data_mux = { 3781 .data24 = { 3782 /* B */ 3783 VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, 3784 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, 3785 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, 3786 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, 3787 /* G */ 3788 VI2_G0_MARK, VI2_G1_MARK, 3789 VI2_G2_MARK, VI2_G3_MARK, 3790 VI2_G4_MARK, VI2_G5_MARK, 3791 VI2_G6_MARK, VI2_G7_MARK, 3792 /* R */ 3793 VI2_R0_MARK, VI2_R1_MARK, 3794 VI2_R2_MARK, VI2_R3_MARK, 3795 VI2_R4_MARK, VI2_R5_MARK, 3796 VI2_R6_MARK, VI2_R7_MARK, 3797 }, 3798 }; 3799 static const unsigned int vin2_data18_pins[] = { 3800 /* B */ 3801 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 3802 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3803 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 3804 /* G */ 3805 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), 3806 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3807 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3808 /* R */ 3809 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 3810 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), 3811 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), 3812 }; 3813 static const unsigned int vin2_data18_mux[] = { 3814 /* B */ 3815 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, 3816 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, 3817 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, 3818 /* G */ 3819 VI2_G2_MARK, VI2_G3_MARK, 3820 VI2_G4_MARK, VI2_G5_MARK, 3821 VI2_G6_MARK, VI2_G7_MARK, 3822 /* R */ 3823 VI2_R2_MARK, VI2_R3_MARK, 3824 VI2_R4_MARK, VI2_R5_MARK, 3825 VI2_R6_MARK, VI2_R7_MARK, 3826 }; 3827 static const unsigned int vin2_sync_pins[] = { 3828 RCAR_GP_PIN(1, 16), /* HSYNC */ 3829 RCAR_GP_PIN(1, 21), /* VSYNC */ 3830 }; 3831 static const unsigned int vin2_sync_mux[] = { 3832 VI2_HSYNC_N_MARK, 3833 VI2_VSYNC_N_MARK, 3834 }; 3835 static const unsigned int vin2_field_pins[] = { 3836 RCAR_GP_PIN(1, 9), 3837 }; 3838 static const unsigned int vin2_field_mux[] = { 3839 VI2_FIELD_MARK, 3840 }; 3841 static const unsigned int vin2_clkenb_pins[] = { 3842 RCAR_GP_PIN(1, 8), 3843 }; 3844 static const unsigned int vin2_clkenb_mux[] = { 3845 VI2_CLKENB_MARK, 3846 }; 3847 static const unsigned int vin2_clk_pins[] = { 3848 RCAR_GP_PIN(1, 11), 3849 }; 3850 static const unsigned int vin2_clk_mux[] = { 3851 VI2_CLK_MARK, 3852 }; 3853 /* - VIN3 ----------------------------------------------------------------- */ 3854 static const unsigned int vin3_data8_pins[] = { 3855 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 3856 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3857 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 3858 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 3859 }; 3860 static const unsigned int vin3_data8_mux[] = { 3861 VI3_DATA0_MARK, VI3_DATA1_MARK, 3862 VI3_DATA2_MARK, VI3_DATA3_MARK, 3863 VI3_DATA4_MARK, VI3_DATA5_MARK, 3864 VI3_DATA6_MARK, VI3_DATA7_MARK, 3865 }; 3866 static const unsigned int vin3_sync_pins[] = { 3867 RCAR_GP_PIN(1, 16), /* HSYNC */ 3868 RCAR_GP_PIN(1, 17), /* VSYNC */ 3869 }; 3870 static const unsigned int vin3_sync_mux[] = { 3871 VI3_HSYNC_N_MARK, 3872 VI3_VSYNC_N_MARK, 3873 }; 3874 static const unsigned int vin3_field_pins[] = { 3875 RCAR_GP_PIN(1, 15), 3876 }; 3877 static const unsigned int vin3_field_mux[] = { 3878 VI3_FIELD_MARK, 3879 }; 3880 static const unsigned int vin3_clkenb_pins[] = { 3881 RCAR_GP_PIN(1, 14), 3882 }; 3883 static const unsigned int vin3_clkenb_mux[] = { 3884 VI3_CLKENB_MARK, 3885 }; 3886 static const unsigned int vin3_clk_pins[] = { 3887 RCAR_GP_PIN(1, 23), 3888 }; 3889 static const unsigned int vin3_clk_mux[] = { 3890 VI3_CLK_MARK, 3891 }; 3892 3893 static const struct sh_pfc_pin_group pinmux_groups[] = { 3894 SH_PFC_PIN_GROUP(audio_clk_a), 3895 SH_PFC_PIN_GROUP(audio_clk_b), 3896 SH_PFC_PIN_GROUP(audio_clk_c), 3897 SH_PFC_PIN_GROUP(audio_clkout), 3898 SH_PFC_PIN_GROUP(audio_clkout_b), 3899 SH_PFC_PIN_GROUP(audio_clkout_c), 3900 SH_PFC_PIN_GROUP(audio_clkout_d), 3901 SH_PFC_PIN_GROUP(avb_link), 3902 SH_PFC_PIN_GROUP(avb_magic), 3903 SH_PFC_PIN_GROUP(avb_phy_int), 3904 SH_PFC_PIN_GROUP(avb_mdio), 3905 SH_PFC_PIN_GROUP(avb_mii), 3906 SH_PFC_PIN_GROUP(avb_gmii), 3907 SH_PFC_PIN_GROUP(du_rgb666), 3908 SH_PFC_PIN_GROUP(du_rgb888), 3909 SH_PFC_PIN_GROUP(du_clk_out_0), 3910 SH_PFC_PIN_GROUP(du_clk_out_1), 3911 SH_PFC_PIN_GROUP(du_sync_0), 3912 SH_PFC_PIN_GROUP(du_sync_1), 3913 SH_PFC_PIN_GROUP(du_cde), 3914 SH_PFC_PIN_GROUP(du0_clk_in), 3915 SH_PFC_PIN_GROUP(du1_clk_in), 3916 SH_PFC_PIN_GROUP(du2_clk_in), 3917 SH_PFC_PIN_GROUP(eth_link), 3918 SH_PFC_PIN_GROUP(eth_magic), 3919 SH_PFC_PIN_GROUP(eth_mdio), 3920 SH_PFC_PIN_GROUP(eth_rmii), 3921 SH_PFC_PIN_GROUP(hscif0_data), 3922 SH_PFC_PIN_GROUP(hscif0_clk), 3923 SH_PFC_PIN_GROUP(hscif0_ctrl), 3924 SH_PFC_PIN_GROUP(hscif0_data_b), 3925 SH_PFC_PIN_GROUP(hscif0_ctrl_b), 3926 SH_PFC_PIN_GROUP(hscif0_data_c), 3927 SH_PFC_PIN_GROUP(hscif0_ctrl_c), 3928 SH_PFC_PIN_GROUP(hscif0_data_d), 3929 SH_PFC_PIN_GROUP(hscif0_ctrl_d), 3930 SH_PFC_PIN_GROUP(hscif0_data_e), 3931 SH_PFC_PIN_GROUP(hscif0_ctrl_e), 3932 SH_PFC_PIN_GROUP(hscif0_data_f), 3933 SH_PFC_PIN_GROUP(hscif0_ctrl_f), 3934 SH_PFC_PIN_GROUP(hscif1_data), 3935 SH_PFC_PIN_GROUP(hscif1_clk), 3936 SH_PFC_PIN_GROUP(hscif1_ctrl), 3937 SH_PFC_PIN_GROUP(hscif1_data_b), 3938 SH_PFC_PIN_GROUP(hscif1_clk_b), 3939 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 3940 SH_PFC_PIN_GROUP(i2c0), 3941 SH_PFC_PIN_GROUP(i2c1), 3942 SH_PFC_PIN_GROUP(i2c1_b), 3943 SH_PFC_PIN_GROUP(i2c1_c), 3944 SH_PFC_PIN_GROUP(i2c2), 3945 SH_PFC_PIN_GROUP(i2c2_b), 3946 SH_PFC_PIN_GROUP(i2c2_c), 3947 SH_PFC_PIN_GROUP(i2c2_d), 3948 SH_PFC_PIN_GROUP(i2c2_e), 3949 SH_PFC_PIN_GROUP(i2c3), 3950 SH_PFC_PIN_GROUP(iic0), 3951 SH_PFC_PIN_GROUP(iic1), 3952 SH_PFC_PIN_GROUP(iic1_b), 3953 SH_PFC_PIN_GROUP(iic1_c), 3954 SH_PFC_PIN_GROUP(iic2), 3955 SH_PFC_PIN_GROUP(iic2_b), 3956 SH_PFC_PIN_GROUP(iic2_c), 3957 SH_PFC_PIN_GROUP(iic2_d), 3958 SH_PFC_PIN_GROUP(iic2_e), 3959 SH_PFC_PIN_GROUP(iic3), 3960 SH_PFC_PIN_GROUP(intc_irq0), 3961 SH_PFC_PIN_GROUP(intc_irq1), 3962 SH_PFC_PIN_GROUP(intc_irq2), 3963 SH_PFC_PIN_GROUP(intc_irq3), 3964 SH_PFC_PIN_GROUP(mlb_3pin), 3965 SH_PFC_PIN_GROUP(mmc0_data1), 3966 SH_PFC_PIN_GROUP(mmc0_data4), 3967 SH_PFC_PIN_GROUP(mmc0_data8), 3968 SH_PFC_PIN_GROUP(mmc0_ctrl), 3969 SH_PFC_PIN_GROUP(mmc1_data1), 3970 SH_PFC_PIN_GROUP(mmc1_data4), 3971 SH_PFC_PIN_GROUP(mmc1_data8), 3972 SH_PFC_PIN_GROUP(mmc1_ctrl), 3973 SH_PFC_PIN_GROUP(msiof0_clk), 3974 SH_PFC_PIN_GROUP(msiof0_sync), 3975 SH_PFC_PIN_GROUP(msiof0_ss1), 3976 SH_PFC_PIN_GROUP(msiof0_ss2), 3977 SH_PFC_PIN_GROUP(msiof0_rx), 3978 SH_PFC_PIN_GROUP(msiof0_tx), 3979 SH_PFC_PIN_GROUP(msiof0_clk_b), 3980 SH_PFC_PIN_GROUP(msiof0_ss1_b), 3981 SH_PFC_PIN_GROUP(msiof0_ss2_b), 3982 SH_PFC_PIN_GROUP(msiof0_rx_b), 3983 SH_PFC_PIN_GROUP(msiof0_tx_b), 3984 SH_PFC_PIN_GROUP(msiof1_clk), 3985 SH_PFC_PIN_GROUP(msiof1_sync), 3986 SH_PFC_PIN_GROUP(msiof1_ss1), 3987 SH_PFC_PIN_GROUP(msiof1_ss2), 3988 SH_PFC_PIN_GROUP(msiof1_rx), 3989 SH_PFC_PIN_GROUP(msiof1_tx), 3990 SH_PFC_PIN_GROUP(msiof1_clk_b), 3991 SH_PFC_PIN_GROUP(msiof1_ss1_b), 3992 SH_PFC_PIN_GROUP(msiof1_ss2_b), 3993 SH_PFC_PIN_GROUP(msiof1_rx_b), 3994 SH_PFC_PIN_GROUP(msiof1_tx_b), 3995 SH_PFC_PIN_GROUP(msiof2_clk), 3996 SH_PFC_PIN_GROUP(msiof2_sync), 3997 SH_PFC_PIN_GROUP(msiof2_ss1), 3998 SH_PFC_PIN_GROUP(msiof2_ss2), 3999 SH_PFC_PIN_GROUP(msiof2_rx), 4000 SH_PFC_PIN_GROUP(msiof2_tx), 4001 SH_PFC_PIN_GROUP(msiof3_clk), 4002 SH_PFC_PIN_GROUP(msiof3_sync), 4003 SH_PFC_PIN_GROUP(msiof3_ss1), 4004 SH_PFC_PIN_GROUP(msiof3_ss2), 4005 SH_PFC_PIN_GROUP(msiof3_rx), 4006 SH_PFC_PIN_GROUP(msiof3_tx), 4007 SH_PFC_PIN_GROUP(msiof3_clk_b), 4008 SH_PFC_PIN_GROUP(msiof3_sync_b), 4009 SH_PFC_PIN_GROUP(msiof3_rx_b), 4010 SH_PFC_PIN_GROUP(msiof3_tx_b), 4011 SH_PFC_PIN_GROUP(qspi_ctrl), 4012 SH_PFC_PIN_GROUP(qspi_data2), 4013 SH_PFC_PIN_GROUP(qspi_data4), 4014 SH_PFC_PIN_GROUP(scif0_data), 4015 SH_PFC_PIN_GROUP(scif0_clk), 4016 SH_PFC_PIN_GROUP(scif0_ctrl), 4017 SH_PFC_PIN_GROUP(scif0_data_b), 4018 SH_PFC_PIN_GROUP(scif1_data), 4019 SH_PFC_PIN_GROUP(scif1_clk), 4020 SH_PFC_PIN_GROUP(scif1_ctrl), 4021 SH_PFC_PIN_GROUP(scif1_data_b), 4022 SH_PFC_PIN_GROUP(scif1_data_c), 4023 SH_PFC_PIN_GROUP(scif1_data_d), 4024 SH_PFC_PIN_GROUP(scif1_clk_d), 4025 SH_PFC_PIN_GROUP(scif1_data_e), 4026 SH_PFC_PIN_GROUP(scif1_clk_e), 4027 SH_PFC_PIN_GROUP(scif2_data), 4028 SH_PFC_PIN_GROUP(scif2_clk), 4029 SH_PFC_PIN_GROUP(scif2_data_b), 4030 SH_PFC_PIN_GROUP(scifa0_data), 4031 SH_PFC_PIN_GROUP(scifa0_clk), 4032 SH_PFC_PIN_GROUP(scifa0_ctrl), 4033 SH_PFC_PIN_GROUP(scifa0_data_b), 4034 SH_PFC_PIN_GROUP(scifa0_clk_b), 4035 SH_PFC_PIN_GROUP(scifa0_ctrl_b), 4036 SH_PFC_PIN_GROUP(scifa1_data), 4037 SH_PFC_PIN_GROUP(scifa1_clk), 4038 SH_PFC_PIN_GROUP(scifa1_ctrl), 4039 SH_PFC_PIN_GROUP(scifa1_data_b), 4040 SH_PFC_PIN_GROUP(scifa1_clk_b), 4041 SH_PFC_PIN_GROUP(scifa1_ctrl_b), 4042 SH_PFC_PIN_GROUP(scifa1_data_c), 4043 SH_PFC_PIN_GROUP(scifa1_clk_c), 4044 SH_PFC_PIN_GROUP(scifa1_ctrl_c), 4045 SH_PFC_PIN_GROUP(scifa1_data_d), 4046 SH_PFC_PIN_GROUP(scifa1_clk_d), 4047 SH_PFC_PIN_GROUP(scifa1_ctrl_d), 4048 SH_PFC_PIN_GROUP(scifa2_data), 4049 SH_PFC_PIN_GROUP(scifa2_clk), 4050 SH_PFC_PIN_GROUP(scifa2_ctrl), 4051 SH_PFC_PIN_GROUP(scifa2_data_b), 4052 SH_PFC_PIN_GROUP(scifa2_data_c), 4053 SH_PFC_PIN_GROUP(scifa2_clk_c), 4054 SH_PFC_PIN_GROUP(scifb0_data), 4055 SH_PFC_PIN_GROUP(scifb0_clk), 4056 SH_PFC_PIN_GROUP(scifb0_ctrl), 4057 SH_PFC_PIN_GROUP(scifb0_data_b), 4058 SH_PFC_PIN_GROUP(scifb0_clk_b), 4059 SH_PFC_PIN_GROUP(scifb0_ctrl_b), 4060 SH_PFC_PIN_GROUP(scifb0_data_c), 4061 SH_PFC_PIN_GROUP(scifb1_data), 4062 SH_PFC_PIN_GROUP(scifb1_clk), 4063 SH_PFC_PIN_GROUP(scifb1_ctrl), 4064 SH_PFC_PIN_GROUP(scifb1_data_b), 4065 SH_PFC_PIN_GROUP(scifb1_clk_b), 4066 SH_PFC_PIN_GROUP(scifb1_ctrl_b), 4067 SH_PFC_PIN_GROUP(scifb1_data_c), 4068 SH_PFC_PIN_GROUP(scifb1_data_d), 4069 SH_PFC_PIN_GROUP(scifb1_data_e), 4070 SH_PFC_PIN_GROUP(scifb1_clk_e), 4071 SH_PFC_PIN_GROUP(scifb1_data_f), 4072 SH_PFC_PIN_GROUP(scifb1_data_g), 4073 SH_PFC_PIN_GROUP(scifb1_clk_g), 4074 SH_PFC_PIN_GROUP(scifb2_data), 4075 SH_PFC_PIN_GROUP(scifb2_clk), 4076 SH_PFC_PIN_GROUP(scifb2_ctrl), 4077 SH_PFC_PIN_GROUP(scifb2_data_b), 4078 SH_PFC_PIN_GROUP(scifb2_clk_b), 4079 SH_PFC_PIN_GROUP(scifb2_ctrl_b), 4080 SH_PFC_PIN_GROUP(scifb2_data_c), 4081 SH_PFC_PIN_GROUP(sdhi0_data1), 4082 SH_PFC_PIN_GROUP(sdhi0_data4), 4083 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4084 SH_PFC_PIN_GROUP(sdhi0_cd), 4085 SH_PFC_PIN_GROUP(sdhi0_wp), 4086 SH_PFC_PIN_GROUP(sdhi1_data1), 4087 SH_PFC_PIN_GROUP(sdhi1_data4), 4088 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4089 SH_PFC_PIN_GROUP(sdhi1_cd), 4090 SH_PFC_PIN_GROUP(sdhi1_wp), 4091 SH_PFC_PIN_GROUP(sdhi2_data1), 4092 SH_PFC_PIN_GROUP(sdhi2_data4), 4093 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4094 SH_PFC_PIN_GROUP(sdhi2_cd), 4095 SH_PFC_PIN_GROUP(sdhi2_wp), 4096 SH_PFC_PIN_GROUP(sdhi3_data1), 4097 SH_PFC_PIN_GROUP(sdhi3_data4), 4098 SH_PFC_PIN_GROUP(sdhi3_ctrl), 4099 SH_PFC_PIN_GROUP(sdhi3_cd), 4100 SH_PFC_PIN_GROUP(sdhi3_wp), 4101 SH_PFC_PIN_GROUP(ssi0_data), 4102 SH_PFC_PIN_GROUP(ssi0129_ctrl), 4103 SH_PFC_PIN_GROUP(ssi1_data), 4104 SH_PFC_PIN_GROUP(ssi1_ctrl), 4105 SH_PFC_PIN_GROUP(ssi2_data), 4106 SH_PFC_PIN_GROUP(ssi2_ctrl), 4107 SH_PFC_PIN_GROUP(ssi3_data), 4108 SH_PFC_PIN_GROUP(ssi34_ctrl), 4109 SH_PFC_PIN_GROUP(ssi4_data), 4110 SH_PFC_PIN_GROUP(ssi4_ctrl), 4111 SH_PFC_PIN_GROUP(ssi5), 4112 SH_PFC_PIN_GROUP(ssi5_b), 4113 SH_PFC_PIN_GROUP(ssi5_c), 4114 SH_PFC_PIN_GROUP(ssi6), 4115 SH_PFC_PIN_GROUP(ssi6_b), 4116 SH_PFC_PIN_GROUP(ssi7_data), 4117 SH_PFC_PIN_GROUP(ssi7_b_data), 4118 SH_PFC_PIN_GROUP(ssi7_c_data), 4119 SH_PFC_PIN_GROUP(ssi78_ctrl), 4120 SH_PFC_PIN_GROUP(ssi78_b_ctrl), 4121 SH_PFC_PIN_GROUP(ssi78_c_ctrl), 4122 SH_PFC_PIN_GROUP(ssi8_data), 4123 SH_PFC_PIN_GROUP(ssi8_b_data), 4124 SH_PFC_PIN_GROUP(ssi8_c_data), 4125 SH_PFC_PIN_GROUP(ssi9_data), 4126 SH_PFC_PIN_GROUP(ssi9_ctrl), 4127 SH_PFC_PIN_GROUP(tpu0_to0), 4128 SH_PFC_PIN_GROUP(tpu0_to1), 4129 SH_PFC_PIN_GROUP(tpu0_to2), 4130 SH_PFC_PIN_GROUP(tpu0_to3), 4131 SH_PFC_PIN_GROUP(usb0), 4132 SH_PFC_PIN_GROUP(usb0_ovc_vbus), 4133 SH_PFC_PIN_GROUP(usb1), 4134 SH_PFC_PIN_GROUP(usb2), 4135 VIN_DATA_PIN_GROUP(vin0_data, 24), 4136 VIN_DATA_PIN_GROUP(vin0_data, 20), 4137 SH_PFC_PIN_GROUP(vin0_data18), 4138 VIN_DATA_PIN_GROUP(vin0_data, 16), 4139 VIN_DATA_PIN_GROUP(vin0_data, 12), 4140 VIN_DATA_PIN_GROUP(vin0_data, 10), 4141 VIN_DATA_PIN_GROUP(vin0_data, 8), 4142 VIN_DATA_PIN_GROUP(vin0_data, 4), 4143 SH_PFC_PIN_GROUP(vin0_sync), 4144 SH_PFC_PIN_GROUP(vin0_field), 4145 SH_PFC_PIN_GROUP(vin0_clkenb), 4146 SH_PFC_PIN_GROUP(vin0_clk), 4147 VIN_DATA_PIN_GROUP(vin1_data, 24), 4148 VIN_DATA_PIN_GROUP(vin1_data, 20), 4149 SH_PFC_PIN_GROUP(vin1_data18), 4150 VIN_DATA_PIN_GROUP(vin1_data, 16), 4151 VIN_DATA_PIN_GROUP(vin1_data, 12), 4152 VIN_DATA_PIN_GROUP(vin1_data, 10), 4153 VIN_DATA_PIN_GROUP(vin1_data, 8), 4154 VIN_DATA_PIN_GROUP(vin1_data, 4), 4155 SH_PFC_PIN_GROUP(vin1_sync), 4156 SH_PFC_PIN_GROUP(vin1_field), 4157 SH_PFC_PIN_GROUP(vin1_clkenb), 4158 SH_PFC_PIN_GROUP(vin1_clk), 4159 VIN_DATA_PIN_GROUP(vin2_data, 24), 4160 SH_PFC_PIN_GROUP(vin2_data18), 4161 VIN_DATA_PIN_GROUP(vin2_data, 16), 4162 VIN_DATA_PIN_GROUP(vin2_data, 8), 4163 VIN_DATA_PIN_GROUP(vin2_data, 4), 4164 SH_PFC_PIN_GROUP(vin2_sync), 4165 SH_PFC_PIN_GROUP(vin2_field), 4166 SH_PFC_PIN_GROUP(vin2_clkenb), 4167 SH_PFC_PIN_GROUP(vin2_clk), 4168 SH_PFC_PIN_GROUP(vin3_data8), 4169 SH_PFC_PIN_GROUP(vin3_sync), 4170 SH_PFC_PIN_GROUP(vin3_field), 4171 SH_PFC_PIN_GROUP(vin3_clkenb), 4172 SH_PFC_PIN_GROUP(vin3_clk), 4173 }; 4174 4175 static const char * const audio_clk_groups[] = { 4176 "audio_clk_a", 4177 "audio_clk_b", 4178 "audio_clk_c", 4179 "audio_clkout", 4180 "audio_clkout_b", 4181 "audio_clkout_c", 4182 "audio_clkout_d", 4183 }; 4184 4185 static const char * const avb_groups[] = { 4186 "avb_link", 4187 "avb_magic", 4188 "avb_phy_int", 4189 "avb_mdio", 4190 "avb_mii", 4191 "avb_gmii", 4192 }; 4193 4194 static const char * const du_groups[] = { 4195 "du_rgb666", 4196 "du_rgb888", 4197 "du_clk_out_0", 4198 "du_clk_out_1", 4199 "du_sync_0", 4200 "du_sync_1", 4201 "du_cde", 4202 }; 4203 4204 static const char * const du0_groups[] = { 4205 "du0_clk_in", 4206 }; 4207 4208 static const char * const du1_groups[] = { 4209 "du1_clk_in", 4210 }; 4211 4212 static const char * const du2_groups[] = { 4213 "du2_clk_in", 4214 }; 4215 4216 static const char * const eth_groups[] = { 4217 "eth_link", 4218 "eth_magic", 4219 "eth_mdio", 4220 "eth_rmii", 4221 }; 4222 4223 static const char * const hscif0_groups[] = { 4224 "hscif0_data", 4225 "hscif0_clk", 4226 "hscif0_ctrl", 4227 "hscif0_data_b", 4228 "hscif0_ctrl_b", 4229 "hscif0_data_c", 4230 "hscif0_ctrl_c", 4231 "hscif0_data_d", 4232 "hscif0_ctrl_d", 4233 "hscif0_data_e", 4234 "hscif0_ctrl_e", 4235 "hscif0_data_f", 4236 "hscif0_ctrl_f", 4237 }; 4238 4239 static const char * const hscif1_groups[] = { 4240 "hscif1_data", 4241 "hscif1_clk", 4242 "hscif1_ctrl", 4243 "hscif1_data_b", 4244 "hscif1_clk_b", 4245 "hscif1_ctrl_b", 4246 }; 4247 4248 static const char * const i2c0_groups[] = { 4249 "i2c0", 4250 }; 4251 4252 static const char * const i2c1_groups[] = { 4253 "i2c1", 4254 "i2c1_b", 4255 "i2c1_c", 4256 }; 4257 4258 static const char * const i2c2_groups[] = { 4259 "i2c2", 4260 "i2c2_b", 4261 "i2c2_c", 4262 "i2c2_d", 4263 "i2c2_e", 4264 }; 4265 4266 static const char * const i2c3_groups[] = { 4267 "i2c3", 4268 }; 4269 4270 static const char * const iic0_groups[] = { 4271 "iic0", 4272 }; 4273 4274 static const char * const iic1_groups[] = { 4275 "iic1", 4276 "iic1_b", 4277 "iic1_c", 4278 }; 4279 4280 static const char * const iic2_groups[] = { 4281 "iic2", 4282 "iic2_b", 4283 "iic2_c", 4284 "iic2_d", 4285 "iic2_e", 4286 }; 4287 4288 static const char * const iic3_groups[] = { 4289 "iic3", 4290 }; 4291 4292 static const char * const intc_groups[] = { 4293 "intc_irq0", 4294 "intc_irq1", 4295 "intc_irq2", 4296 "intc_irq3", 4297 }; 4298 4299 static const char * const mlb_groups[] = { 4300 "mlb_3pin", 4301 }; 4302 4303 static const char * const mmc0_groups[] = { 4304 "mmc0_data1", 4305 "mmc0_data4", 4306 "mmc0_data8", 4307 "mmc0_ctrl", 4308 }; 4309 4310 static const char * const mmc1_groups[] = { 4311 "mmc1_data1", 4312 "mmc1_data4", 4313 "mmc1_data8", 4314 "mmc1_ctrl", 4315 }; 4316 4317 static const char * const msiof0_groups[] = { 4318 "msiof0_clk", 4319 "msiof0_sync", 4320 "msiof0_ss1", 4321 "msiof0_ss2", 4322 "msiof0_rx", 4323 "msiof0_tx", 4324 "msiof0_clk_b", 4325 "msiof0_ss1_b", 4326 "msiof0_ss2_b", 4327 "msiof0_rx_b", 4328 "msiof0_tx_b", 4329 }; 4330 4331 static const char * const msiof1_groups[] = { 4332 "msiof1_clk", 4333 "msiof1_sync", 4334 "msiof1_ss1", 4335 "msiof1_ss2", 4336 "msiof1_rx", 4337 "msiof1_tx", 4338 "msiof1_clk_b", 4339 "msiof1_ss1_b", 4340 "msiof1_ss2_b", 4341 "msiof1_rx_b", 4342 "msiof1_tx_b", 4343 }; 4344 4345 static const char * const msiof2_groups[] = { 4346 "msiof2_clk", 4347 "msiof2_sync", 4348 "msiof2_ss1", 4349 "msiof2_ss2", 4350 "msiof2_rx", 4351 "msiof2_tx", 4352 }; 4353 4354 static const char * const msiof3_groups[] = { 4355 "msiof3_clk", 4356 "msiof3_sync", 4357 "msiof3_ss1", 4358 "msiof3_ss2", 4359 "msiof3_rx", 4360 "msiof3_tx", 4361 "msiof3_clk_b", 4362 "msiof3_sync_b", 4363 "msiof3_rx_b", 4364 "msiof3_tx_b", 4365 }; 4366 4367 static const char * const qspi_groups[] = { 4368 "qspi_ctrl", 4369 "qspi_data2", 4370 "qspi_data4", 4371 }; 4372 4373 static const char * const scif0_groups[] = { 4374 "scif0_data", 4375 "scif0_clk", 4376 "scif0_ctrl", 4377 "scif0_data_b", 4378 }; 4379 4380 static const char * const scif1_groups[] = { 4381 "scif1_data", 4382 "scif1_clk", 4383 "scif1_ctrl", 4384 "scif1_data_b", 4385 "scif1_data_c", 4386 "scif1_data_d", 4387 "scif1_clk_d", 4388 "scif1_data_e", 4389 "scif1_clk_e", 4390 }; 4391 4392 static const char * const scif2_groups[] = { 4393 "scif2_data", 4394 "scif2_clk", 4395 "scif2_data_b", 4396 }; 4397 4398 static const char * const scifa0_groups[] = { 4399 "scifa0_data", 4400 "scifa0_clk", 4401 "scifa0_ctrl", 4402 "scifa0_data_b", 4403 "scifa0_clk_b", 4404 "scifa0_ctrl_b", 4405 }; 4406 4407 static const char * const scifa1_groups[] = { 4408 "scifa1_data", 4409 "scifa1_clk", 4410 "scifa1_ctrl", 4411 "scifa1_data_b", 4412 "scifa1_clk_b", 4413 "scifa1_ctrl_b", 4414 "scifa1_data_c", 4415 "scifa1_clk_c", 4416 "scifa1_ctrl_c", 4417 "scifa1_data_d", 4418 "scifa1_clk_d", 4419 "scifa1_ctrl_d", 4420 }; 4421 4422 static const char * const scifa2_groups[] = { 4423 "scifa2_data", 4424 "scifa2_clk", 4425 "scifa2_ctrl", 4426 "scifa2_data_b", 4427 "scifa2_data_c", 4428 "scifa2_clk_c", 4429 }; 4430 4431 static const char * const scifb0_groups[] = { 4432 "scifb0_data", 4433 "scifb0_clk", 4434 "scifb0_ctrl", 4435 "scifb0_data_b", 4436 "scifb0_clk_b", 4437 "scifb0_ctrl_b", 4438 "scifb0_data_c", 4439 }; 4440 4441 static const char * const scifb1_groups[] = { 4442 "scifb1_data", 4443 "scifb1_clk", 4444 "scifb1_ctrl", 4445 "scifb1_data_b", 4446 "scifb1_clk_b", 4447 "scifb1_ctrl_b", 4448 "scifb1_data_c", 4449 "scifb1_data_d", 4450 "scifb1_data_e", 4451 "scifb1_clk_e", 4452 "scifb1_data_f", 4453 "scifb1_data_g", 4454 "scifb1_clk_g", 4455 }; 4456 4457 static const char * const scifb2_groups[] = { 4458 "scifb2_data", 4459 "scifb2_clk", 4460 "scifb2_ctrl", 4461 "scifb2_data_b", 4462 "scifb2_clk_b", 4463 "scifb2_ctrl_b", 4464 "scifb2_data_c", 4465 }; 4466 4467 static const char * const sdhi0_groups[] = { 4468 "sdhi0_data1", 4469 "sdhi0_data4", 4470 "sdhi0_ctrl", 4471 "sdhi0_cd", 4472 "sdhi0_wp", 4473 }; 4474 4475 static const char * const sdhi1_groups[] = { 4476 "sdhi1_data1", 4477 "sdhi1_data4", 4478 "sdhi1_ctrl", 4479 "sdhi1_cd", 4480 "sdhi1_wp", 4481 }; 4482 4483 static const char * const sdhi2_groups[] = { 4484 "sdhi2_data1", 4485 "sdhi2_data4", 4486 "sdhi2_ctrl", 4487 "sdhi2_cd", 4488 "sdhi2_wp", 4489 }; 4490 4491 static const char * const sdhi3_groups[] = { 4492 "sdhi3_data1", 4493 "sdhi3_data4", 4494 "sdhi3_ctrl", 4495 "sdhi3_cd", 4496 "sdhi3_wp", 4497 }; 4498 4499 static const char * const ssi_groups[] = { 4500 "ssi0_data", 4501 "ssi0129_ctrl", 4502 "ssi1_data", 4503 "ssi1_ctrl", 4504 "ssi2_data", 4505 "ssi2_ctrl", 4506 "ssi3_data", 4507 "ssi34_ctrl", 4508 "ssi4_data", 4509 "ssi4_ctrl", 4510 "ssi5", 4511 "ssi5_b", 4512 "ssi5_c", 4513 "ssi6", 4514 "ssi6_b", 4515 "ssi7_data", 4516 "ssi7_b_data", 4517 "ssi7_c_data", 4518 "ssi78_ctrl", 4519 "ssi78_b_ctrl", 4520 "ssi78_c_ctrl", 4521 "ssi8_data", 4522 "ssi8_b_data", 4523 "ssi8_c_data", 4524 "ssi9_data", 4525 "ssi9_ctrl", 4526 }; 4527 4528 static const char * const tpu0_groups[] = { 4529 "tpu0_to0", 4530 "tpu0_to1", 4531 "tpu0_to2", 4532 "tpu0_to3", 4533 }; 4534 4535 static const char * const usb0_groups[] = { 4536 "usb0", 4537 "usb0_ovc_vbus", 4538 }; 4539 4540 static const char * const usb1_groups[] = { 4541 "usb1", 4542 }; 4543 4544 static const char * const usb2_groups[] = { 4545 "usb2", 4546 }; 4547 4548 static const char * const vin0_groups[] = { 4549 "vin0_data24", 4550 "vin0_data20", 4551 "vin0_data18", 4552 "vin0_data16", 4553 "vin0_data12", 4554 "vin0_data10", 4555 "vin0_data8", 4556 "vin0_data4", 4557 "vin0_sync", 4558 "vin0_field", 4559 "vin0_clkenb", 4560 "vin0_clk", 4561 }; 4562 4563 static const char * const vin1_groups[] = { 4564 "vin1_data24", 4565 "vin1_data20", 4566 "vin1_data18", 4567 "vin1_data16", 4568 "vin1_data12", 4569 "vin1_data10", 4570 "vin1_data8", 4571 "vin1_data4", 4572 "vin1_sync", 4573 "vin1_field", 4574 "vin1_clkenb", 4575 "vin1_clk", 4576 }; 4577 4578 static const char * const vin2_groups[] = { 4579 "vin2_data24", 4580 "vin2_data18", 4581 "vin2_data16", 4582 "vin2_data8", 4583 "vin2_data4", 4584 "vin2_sync", 4585 "vin2_field", 4586 "vin2_clkenb", 4587 "vin2_clk", 4588 }; 4589 4590 static const char * const vin3_groups[] = { 4591 "vin3_data8", 4592 "vin3_sync", 4593 "vin3_field", 4594 "vin3_clkenb", 4595 "vin3_clk", 4596 }; 4597 4598 static const struct sh_pfc_function pinmux_functions[] = { 4599 SH_PFC_FUNCTION(audio_clk), 4600 SH_PFC_FUNCTION(avb), 4601 SH_PFC_FUNCTION(du), 4602 SH_PFC_FUNCTION(du0), 4603 SH_PFC_FUNCTION(du1), 4604 SH_PFC_FUNCTION(du2), 4605 SH_PFC_FUNCTION(eth), 4606 SH_PFC_FUNCTION(hscif0), 4607 SH_PFC_FUNCTION(hscif1), 4608 SH_PFC_FUNCTION(i2c0), 4609 SH_PFC_FUNCTION(i2c1), 4610 SH_PFC_FUNCTION(i2c2), 4611 SH_PFC_FUNCTION(i2c3), 4612 SH_PFC_FUNCTION(iic0), 4613 SH_PFC_FUNCTION(iic1), 4614 SH_PFC_FUNCTION(iic2), 4615 SH_PFC_FUNCTION(iic3), 4616 SH_PFC_FUNCTION(intc), 4617 SH_PFC_FUNCTION(mlb), 4618 SH_PFC_FUNCTION(mmc0), 4619 SH_PFC_FUNCTION(mmc1), 4620 SH_PFC_FUNCTION(msiof0), 4621 SH_PFC_FUNCTION(msiof1), 4622 SH_PFC_FUNCTION(msiof2), 4623 SH_PFC_FUNCTION(msiof3), 4624 SH_PFC_FUNCTION(qspi), 4625 SH_PFC_FUNCTION(scif0), 4626 SH_PFC_FUNCTION(scif1), 4627 SH_PFC_FUNCTION(scif2), 4628 SH_PFC_FUNCTION(scifa0), 4629 SH_PFC_FUNCTION(scifa1), 4630 SH_PFC_FUNCTION(scifa2), 4631 SH_PFC_FUNCTION(scifb0), 4632 SH_PFC_FUNCTION(scifb1), 4633 SH_PFC_FUNCTION(scifb2), 4634 SH_PFC_FUNCTION(sdhi0), 4635 SH_PFC_FUNCTION(sdhi1), 4636 SH_PFC_FUNCTION(sdhi2), 4637 SH_PFC_FUNCTION(sdhi3), 4638 SH_PFC_FUNCTION(ssi), 4639 SH_PFC_FUNCTION(tpu0), 4640 SH_PFC_FUNCTION(usb0), 4641 SH_PFC_FUNCTION(usb1), 4642 SH_PFC_FUNCTION(usb2), 4643 SH_PFC_FUNCTION(vin0), 4644 SH_PFC_FUNCTION(vin1), 4645 SH_PFC_FUNCTION(vin2), 4646 SH_PFC_FUNCTION(vin3), 4647 }; 4648 4649 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 4650 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { 4651 GP_0_31_FN, FN_IP3_17_15, 4652 GP_0_30_FN, FN_IP3_14_12, 4653 GP_0_29_FN, FN_IP3_11_8, 4654 GP_0_28_FN, FN_IP3_7_4, 4655 GP_0_27_FN, FN_IP3_3_0, 4656 GP_0_26_FN, FN_IP2_28_26, 4657 GP_0_25_FN, FN_IP2_25_22, 4658 GP_0_24_FN, FN_IP2_21_18, 4659 GP_0_23_FN, FN_IP2_17_15, 4660 GP_0_22_FN, FN_IP2_14_12, 4661 GP_0_21_FN, FN_IP2_11_9, 4662 GP_0_20_FN, FN_IP2_8_6, 4663 GP_0_19_FN, FN_IP2_5_3, 4664 GP_0_18_FN, FN_IP2_2_0, 4665 GP_0_17_FN, FN_IP1_29_28, 4666 GP_0_16_FN, FN_IP1_27_26, 4667 GP_0_15_FN, FN_IP1_25_22, 4668 GP_0_14_FN, FN_IP1_21_18, 4669 GP_0_13_FN, FN_IP1_17_15, 4670 GP_0_12_FN, FN_IP1_14_12, 4671 GP_0_11_FN, FN_IP1_11_8, 4672 GP_0_10_FN, FN_IP1_7_4, 4673 GP_0_9_FN, FN_IP1_3_0, 4674 GP_0_8_FN, FN_IP0_30_27, 4675 GP_0_7_FN, FN_IP0_26_23, 4676 GP_0_6_FN, FN_IP0_22_20, 4677 GP_0_5_FN, FN_IP0_19_16, 4678 GP_0_4_FN, FN_IP0_15_12, 4679 GP_0_3_FN, FN_IP0_11_9, 4680 GP_0_2_FN, FN_IP0_8_6, 4681 GP_0_1_FN, FN_IP0_5_3, 4682 GP_0_0_FN, FN_IP0_2_0 } 4683 }, 4684 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { 4685 0, 0, 4686 0, 0, 4687 GP_1_29_FN, FN_IP6_13_11, 4688 GP_1_28_FN, FN_IP6_10_9, 4689 GP_1_27_FN, FN_IP6_8_6, 4690 GP_1_26_FN, FN_IP6_5_3, 4691 GP_1_25_FN, FN_IP6_2_0, 4692 GP_1_24_FN, FN_IP5_29_27, 4693 GP_1_23_FN, FN_IP5_26_24, 4694 GP_1_22_FN, FN_IP5_23_21, 4695 GP_1_21_FN, FN_IP5_20_18, 4696 GP_1_20_FN, FN_IP5_17_15, 4697 GP_1_19_FN, FN_IP5_14_13, 4698 GP_1_18_FN, FN_IP5_12_10, 4699 GP_1_17_FN, FN_IP5_9_6, 4700 GP_1_16_FN, FN_IP5_5_3, 4701 GP_1_15_FN, FN_IP5_2_0, 4702 GP_1_14_FN, FN_IP4_29_27, 4703 GP_1_13_FN, FN_IP4_26_24, 4704 GP_1_12_FN, FN_IP4_23_21, 4705 GP_1_11_FN, FN_IP4_20_18, 4706 GP_1_10_FN, FN_IP4_17_15, 4707 GP_1_9_FN, FN_IP4_14_12, 4708 GP_1_8_FN, FN_IP4_11_9, 4709 GP_1_7_FN, FN_IP4_8_6, 4710 GP_1_6_FN, FN_IP4_5_3, 4711 GP_1_5_FN, FN_IP4_2_0, 4712 GP_1_4_FN, FN_IP3_31_29, 4713 GP_1_3_FN, FN_IP3_28_26, 4714 GP_1_2_FN, FN_IP3_25_23, 4715 GP_1_1_FN, FN_IP3_22_20, 4716 GP_1_0_FN, FN_IP3_19_18, } 4717 }, 4718 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { 4719 0, 0, 4720 0, 0, 4721 GP_2_29_FN, FN_IP7_15_13, 4722 GP_2_28_FN, FN_IP7_12_10, 4723 GP_2_27_FN, FN_IP7_9_8, 4724 GP_2_26_FN, FN_IP7_7_6, 4725 GP_2_25_FN, FN_IP7_5_3, 4726 GP_2_24_FN, FN_IP7_2_0, 4727 GP_2_23_FN, FN_IP6_31_29, 4728 GP_2_22_FN, FN_IP6_28_26, 4729 GP_2_21_FN, FN_IP6_25_23, 4730 GP_2_20_FN, FN_IP6_22_20, 4731 GP_2_19_FN, FN_IP6_19_17, 4732 GP_2_18_FN, FN_IP6_16_14, 4733 GP_2_17_FN, FN_VI1_DATA7_VI1_B7, 4734 GP_2_16_FN, FN_IP8_27, 4735 GP_2_15_FN, FN_IP8_26, 4736 GP_2_14_FN, FN_IP8_25_24, 4737 GP_2_13_FN, FN_IP8_23_22, 4738 GP_2_12_FN, FN_IP8_21_20, 4739 GP_2_11_FN, FN_IP8_19_18, 4740 GP_2_10_FN, FN_IP8_17_16, 4741 GP_2_9_FN, FN_IP8_15_14, 4742 GP_2_8_FN, FN_IP8_13_12, 4743 GP_2_7_FN, FN_IP8_11_10, 4744 GP_2_6_FN, FN_IP8_9_8, 4745 GP_2_5_FN, FN_IP8_7_6, 4746 GP_2_4_FN, FN_IP8_5_4, 4747 GP_2_3_FN, FN_IP8_3_2, 4748 GP_2_2_FN, FN_IP8_1_0, 4749 GP_2_1_FN, FN_IP7_30_29, 4750 GP_2_0_FN, FN_IP7_28_27 } 4751 }, 4752 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { 4753 GP_3_31_FN, FN_IP11_21_18, 4754 GP_3_30_FN, FN_IP11_17_15, 4755 GP_3_29_FN, FN_IP11_14_13, 4756 GP_3_28_FN, FN_IP11_12_11, 4757 GP_3_27_FN, FN_IP11_10_9, 4758 GP_3_26_FN, FN_IP11_8_7, 4759 GP_3_25_FN, FN_IP11_6_5, 4760 GP_3_24_FN, FN_IP11_4, 4761 GP_3_23_FN, FN_IP11_3_0, 4762 GP_3_22_FN, FN_IP10_29_26, 4763 GP_3_21_FN, FN_IP10_25_23, 4764 GP_3_20_FN, FN_IP10_22_19, 4765 GP_3_19_FN, FN_IP10_18_15, 4766 GP_3_18_FN, FN_IP10_14_11, 4767 GP_3_17_FN, FN_IP10_10_7, 4768 GP_3_16_FN, FN_IP10_6_4, 4769 GP_3_15_FN, FN_IP10_3_0, 4770 GP_3_14_FN, FN_IP9_31_28, 4771 GP_3_13_FN, FN_IP9_27_26, 4772 GP_3_12_FN, FN_IP9_25_24, 4773 GP_3_11_FN, FN_IP9_23_22, 4774 GP_3_10_FN, FN_IP9_21_20, 4775 GP_3_9_FN, FN_IP9_19_18, 4776 GP_3_8_FN, FN_IP9_17_16, 4777 GP_3_7_FN, FN_IP9_15_12, 4778 GP_3_6_FN, FN_IP9_11_8, 4779 GP_3_5_FN, FN_IP9_7_6, 4780 GP_3_4_FN, FN_IP9_5_4, 4781 GP_3_3_FN, FN_IP9_3_2, 4782 GP_3_2_FN, FN_IP9_1_0, 4783 GP_3_1_FN, FN_IP8_30_29, 4784 GP_3_0_FN, FN_IP8_28 } 4785 }, 4786 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { 4787 GP_4_31_FN, FN_IP14_18_16, 4788 GP_4_30_FN, FN_IP14_15_12, 4789 GP_4_29_FN, FN_IP14_11_9, 4790 GP_4_28_FN, FN_IP14_8_6, 4791 GP_4_27_FN, FN_IP14_5_3, 4792 GP_4_26_FN, FN_IP14_2_0, 4793 GP_4_25_FN, FN_IP13_30_29, 4794 GP_4_24_FN, FN_IP13_28_26, 4795 GP_4_23_FN, FN_IP13_25_23, 4796 GP_4_22_FN, FN_IP13_22_19, 4797 GP_4_21_FN, FN_IP13_18_16, 4798 GP_4_20_FN, FN_IP13_15_13, 4799 GP_4_19_FN, FN_IP13_12_10, 4800 GP_4_18_FN, FN_IP13_9_7, 4801 GP_4_17_FN, FN_IP13_6_3, 4802 GP_4_16_FN, FN_IP13_2_0, 4803 GP_4_15_FN, FN_IP12_30_28, 4804 GP_4_14_FN, FN_IP12_27_25, 4805 GP_4_13_FN, FN_IP12_24_23, 4806 GP_4_12_FN, FN_IP12_22_20, 4807 GP_4_11_FN, FN_IP12_19_17, 4808 GP_4_10_FN, FN_IP12_16_14, 4809 GP_4_9_FN, FN_IP12_13_11, 4810 GP_4_8_FN, FN_IP12_10_8, 4811 GP_4_7_FN, FN_IP12_7_6, 4812 GP_4_6_FN, FN_IP12_5_4, 4813 GP_4_5_FN, FN_IP12_3_2, 4814 GP_4_4_FN, FN_IP12_1_0, 4815 GP_4_3_FN, FN_IP11_31_30, 4816 GP_4_2_FN, FN_IP11_29_27, 4817 GP_4_1_FN, FN_IP11_26_24, 4818 GP_4_0_FN, FN_IP11_23_22 } 4819 }, 4820 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { 4821 GP_5_31_FN, FN_IP7_24_22, 4822 GP_5_30_FN, FN_IP7_21_19, 4823 GP_5_29_FN, FN_IP7_18_16, 4824 GP_5_28_FN, FN_DU_DOTCLKIN2, 4825 GP_5_27_FN, FN_IP7_26_25, 4826 GP_5_26_FN, FN_DU_DOTCLKIN0, 4827 GP_5_25_FN, FN_AVS2, 4828 GP_5_24_FN, FN_AVS1, 4829 GP_5_23_FN, FN_USB2_OVC, 4830 GP_5_22_FN, FN_USB2_PWEN, 4831 GP_5_21_FN, FN_IP16_7, 4832 GP_5_20_FN, FN_IP16_6, 4833 GP_5_19_FN, FN_USB0_OVC_VBUS, 4834 GP_5_18_FN, FN_USB0_PWEN, 4835 GP_5_17_FN, FN_IP16_5_3, 4836 GP_5_16_FN, FN_IP16_2_0, 4837 GP_5_15_FN, FN_IP15_29_28, 4838 GP_5_14_FN, FN_IP15_27_26, 4839 GP_5_13_FN, FN_IP15_25_23, 4840 GP_5_12_FN, FN_IP15_22_20, 4841 GP_5_11_FN, FN_IP15_19_18, 4842 GP_5_10_FN, FN_IP15_17_16, 4843 GP_5_9_FN, FN_IP15_15_14, 4844 GP_5_8_FN, FN_IP15_13_12, 4845 GP_5_7_FN, FN_IP15_11_9, 4846 GP_5_6_FN, FN_IP15_8_6, 4847 GP_5_5_FN, FN_IP15_5_3, 4848 GP_5_4_FN, FN_IP15_2_0, 4849 GP_5_3_FN, FN_IP14_30_28, 4850 GP_5_2_FN, FN_IP14_27_25, 4851 GP_5_1_FN, FN_IP14_24_22, 4852 GP_5_0_FN, FN_IP14_21_19 } 4853 }, 4854 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, 4855 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) { 4856 /* IP0_31 [1] */ 4857 0, 0, 4858 /* IP0_30_27 [4] */ 4859 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0, 4860 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, 4861 0, 0, 0, 0, 0, 0, 0, 0, 0, 4862 /* IP0_26_23 [4] */ 4863 FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, 4864 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, 4865 FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0, 4866 /* IP0_22_20 [3] */ 4867 FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, 4868 FN_I2C2_SCL_C, 0, 0, 4869 /* IP0_19_16 [4] */ 4870 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, 4871 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, 4872 0, 0, 0, 0, 0, 0, 0, 0, 0, 4873 /* IP0_15_12 [4] */ 4874 FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, 4875 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, 4876 0, 0, 0, 0, 0, 0, 0, 0, 0, 4877 /* IP0_11_9 [3] */ 4878 FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, 4879 0, 0, 0, 4880 /* IP0_8_6 [3] */ 4881 FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B, 4882 0, 0, 0, 4883 /* IP0_5_3 [3] */ 4884 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B, 4885 0, 0, 0, 4886 /* IP0_2_0 [3] */ 4887 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, 4888 0, 0, 0, } 4889 }, 4890 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, 4891 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) { 4892 /* IP1_31_30 [2] */ 4893 0, 0, 0, 0, 4894 /* IP1_29_28 [2] */ 4895 FN_A1, FN_PWM4, 0, 0, 4896 /* IP1_27_26 [2] */ 4897 FN_A0, FN_PWM3, 0, 0, 4898 /* IP1_25_22 [4] */ 4899 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, 4900 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, 4901 0, 0, 0, 0, 0, 0, 0, 0, 0, 4902 /* IP1_21_18 [4] */ 4903 FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, 4904 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, 4905 0, 0, 0, 0, 0, 0, 0, 0, 0, 4906 /* IP1_17_15 [3] */ 4907 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, 4908 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, 4909 0, 0, 0, 4910 /* IP1_14_12 [3] */ 4911 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, 4912 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, 4913 0, 0, 4914 /* IP1_11_8 [4] */ 4915 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0, 4916 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, 4917 0, 0, 0, 0, 0, 0, 0, 0, 0, 4918 /* IP1_7_4 [4] */ 4919 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0, 4920 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, 4921 0, 0, 0, 0, 0, 0, 0, 0, 0, 4922 /* IP1_3_0 [4] */ 4923 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0, 4924 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, 4925 0, 0, 0, 0, 0, 0, 0, 0, 0, } 4926 }, 4927 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, 4928 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) { 4929 /* IP2_31_29 [3] */ 4930 0, 0, 0, 0, 0, 0, 0, 0, 4931 /* IP2_28_26 [3] */ 4932 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, 4933 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0, 4934 /* IP2_25_22 [4] */ 4935 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, 4936 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B, 4937 0, 0, 0, 0, 0, 0, 0, 0, 4938 /* IP2_21_18 [4] */ 4939 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, 4940 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B, 4941 0, 0, 0, 0, 0, 0, 0, 0, 4942 /* IP2_17_15 [3] */ 4943 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, 4944 0, 0, 0, 0, 4945 /* IP2_14_12 [3] */ 4946 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0, 4947 /* IP2_11_9 [3] */ 4948 FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0, 4949 /* IP2_8_6 [3] */ 4950 FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0, 4951 /* IP2_5_3 [3] */ 4952 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0, 4953 /* IP2_2_0 [3] */ 4954 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, } 4955 }, 4956 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, 4957 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) { 4958 /* IP3_31_29 [3] */ 4959 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, 4960 0, 0, 0, 4961 /* IP3_28_26 [3] */ 4962 FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B, 4963 0, 0, 0, 0, 4964 /* IP3_25_23 [3] */ 4965 FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0, 4966 /* IP3_22_20 [3] */ 4967 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0, 4968 /* IP3_19_18 [2] */ 4969 FN_A16, FN_ATAWR1_N, 0, 0, 4970 /* IP3_17_15 [3] */ 4971 FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2, 4972 0, 0, 0, 0, 4973 /* IP3_14_12 [3] */ 4974 FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1, 4975 0, 0, 0, 0, 4976 /* IP3_11_8 [4] */ 4977 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, 4978 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, 4979 FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0, 4980 /* IP3_7_4 [4] */ 4981 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, 4982 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, 4983 0, 0, 0, 0, 0, 0, 0, 0, 0, 4984 /* IP3_3_0 [4] */ 4985 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, 4986 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0, 4987 0, 0, 0, 0, 0, 0, 0, 0, } 4988 }, 4989 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, 4990 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { 4991 /* IP4_31_30 [2] */ 4992 0, 0, 0, 0, 4993 /* IP4_29_27 [3] */ 4994 FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, 4995 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0, 4996 /* IP4_26_24 [3] */ 4997 FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD, 4998 FN_VI1_FIELD_B, FN_VI2_R1, 0, 0, 4999 /* IP4_23_21 [3] */ 5000 FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, 5001 FN_HTX0_B, FN_MSIOF0_SS1_B, 0, 5002 /* IP4_20_18 [3] */ 5003 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, 5004 FN_VI2_CLK, FN_VI2_CLK_B, 0, 0, 5005 /* IP4_17_15 [3] */ 5006 FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, 5007 0, 0, 0, 5008 /* IP4_14_12 [3] */ 5009 FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD, 5010 FN_VI2_FIELD_B, 0, 0, 5011 /* IP4_11_9 [3] */ 5012 FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, 5013 FN_VI2_CLKENB_B, 0, 0, 5014 /* IP4_8_6 [3] */ 5015 FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0, 5016 /* IP4_5_3 [3] */ 5017 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0, 5018 /* IP4_2_0 [3] */ 5019 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0, 5020 } 5021 }, 5022 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, 5023 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) { 5024 /* IP5_31_30 [2] */ 5025 0, 0, 0, 0, 5026 /* IP5_29_27 [3] */ 5027 FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7, 5028 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0, 5029 /* IP5_26_24 [3] */ 5030 FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, 5031 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, 5032 FN_MSIOF0_SCK_B, 0, 5033 /* IP5_23_21 [3] */ 5034 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, 5035 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C, 5036 /* IP5_20_18 [3] */ 5037 FN_WE0_N, FN_IECLK, FN_CAN_CLK, 5038 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0, 5039 /* IP5_17_15 [3] */ 5040 FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, 5041 FN_INTC_IRQ4_N, 0, 0, 5042 /* IP5_14_13 [2] */ 5043 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0, 5044 /* IP5_12_10 [3] */ 5045 FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C, 5046 0, 0, 5047 /* IP5_9_6 [4] */ 5048 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, 5049 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N, 5050 FN_I2C1_SDA, 0, 0, 0, 0, 0, 0, 5051 /* IP5_5_3 [3] */ 5052 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, 5053 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B, 5054 FN_INTC_EN0_N, FN_I2C1_SCL, 5055 /* IP5_2_0 [3] */ 5056 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, 5057 FN_VI2_R3, 0, 0, } 5058 }, 5059 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, 5060 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { 5061 /* IP6_31_29 [3] */ 5062 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E, 5063 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, 5064 /* IP6_28_26 [3] */ 5065 FN_ETH_LINK, 0, FN_HTX0_E, 5066 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0, 5067 /* IP6_25_23 [3] */ 5068 FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B, 5069 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E, 5070 /* IP6_22_20 [3] */ 5071 FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D, 5072 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, 5073 /* IP6_19_17 [3] */ 5074 FN_ETH_RX_ER, 0, FN_STP_ISD_0_B, 5075 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0, 5076 /* IP6_16_14 [3] */ 5077 FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B, 5078 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, 5079 FN_I2C2_SCL_E, 0, 5080 /* IP6_13_11 [3] */ 5081 FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, 5082 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, 5083 /* IP6_10_9 [2] */ 5084 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B, 5085 /* IP6_8_6 [3] */ 5086 FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B, 5087 FN_SSI_SDATA8_C, 0, 0, 0, 5088 /* IP6_5_3 [3] */ 5089 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, 5090 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, 5091 /* IP6_2_0 [3] */ 5092 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, 5093 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, } 5094 }, 5095 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, 5096 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) { 5097 /* IP7_31 [1] */ 5098 0, 0, 5099 /* IP7_30_29 [2] */ 5100 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0, 5101 /* IP7_28_27 [2] */ 5102 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0, 5103 /* IP7_26_25 [2] */ 5104 FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, 5105 /* IP7_24_22 [3] */ 5106 FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C, 5107 0, 0, 0, 5108 /* IP7_21_19 [3] */ 5109 FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, 5110 FN_GLO_RFON_C, FN_PCMOE_N, 0, 0, 5111 /* IP7_18_16 [3] */ 5112 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, 5113 FN_GLO_SS_C, 0, 0, 0, 5114 /* IP7_15_13 [3] */ 5115 FN_ETH_MDC, 0, FN_STP_ISD_1_B, 5116 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0, 5117 /* IP7_12_10 [3] */ 5118 FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, 5119 FN_GLO_SCLK_C, 0, 0, 0, 5120 /* IP7_9_8 [2] */ 5121 FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0, 5122 /* IP7_7_6 [2] */ 5123 FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F, 5124 /* IP7_5_3 [3] */ 5125 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0, 5126 /* IP7_2_0 [3] */ 5127 FN_ETH_MDIO, 0, FN_HRTS0_N_E, 5128 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } 5129 }, 5130 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, 5131 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 5132 2, 2, 2, 2, 2, 2, 2) { 5133 /* IP8_31 [1] */ 5134 0, 0, 5135 /* IP8_30_29 [2] */ 5136 FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0, 5137 /* IP8_28 [1] */ 5138 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, 5139 /* IP8_27 [1] */ 5140 FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, 5141 /* IP8_26 [1] */ 5142 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT, 5143 /* IP8_25_24 [2] */ 5144 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, 5145 FN_AVB_MAGIC, 0, 5146 /* IP8_23_22 [2] */ 5147 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0, 5148 /* IP8_21_20 [2] */ 5149 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0, 5150 /* IP8_19_18 [2] */ 5151 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0, 5152 /* IP8_17_16 [2] */ 5153 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0, 5154 /* IP8_15_14 [2] */ 5155 FN_VI1_CLK, FN_AVB_RX_DV, 0, 0, 5156 /* IP8_13_12 [2] */ 5157 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0, 5158 /* IP8_11_10 [2] */ 5159 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0, 5160 /* IP8_9_8 [2] */ 5161 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0, 5162 /* IP8_7_6 [2] */ 5163 FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0, 5164 /* IP8_5_4 [2] */ 5165 FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0, 5166 /* IP8_3_2 [2] */ 5167 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, 5168 /* IP8_1_0 [2] */ 5169 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, } 5170 }, 5171 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, 5172 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { 5173 /* IP9_31_28 [4] */ 5174 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP, 5175 FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D, 5176 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0, 5177 /* IP9_27_26 [2] */ 5178 FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B, 5179 /* IP9_25_24 [2] */ 5180 FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B, 5181 /* IP9_23_22 [2] */ 5182 FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B, 5183 /* IP9_21_20 [2] */ 5184 FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B, 5185 /* IP9_19_18 [2] */ 5186 FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B, 5187 /* IP9_17_16 [2] */ 5188 FN_SD1_CLK, FN_AVB_TX_EN, 0, 0, 5189 /* IP9_15_12 [4] */ 5190 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, 5191 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, 5192 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0, 5193 /* IP9_11_8 [4] */ 5194 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, 5195 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B, 5196 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0, 5197 /* IP9_7_6 [2] */ 5198 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0, 5199 /* IP9_5_4 [2] */ 5200 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0, 5201 /* IP9_3_2 [2] */ 5202 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0, 5203 /* IP9_1_0 [2] */ 5204 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, } 5205 }, 5206 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, 5207 2, 4, 3, 4, 4, 4, 4, 3, 4) { 5208 /* IP10_31_30 [2] */ 5209 0, 0, 0, 0, 5210 /* IP10_29_26 [4] */ 5211 FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, 5212 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, 5213 FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0, 5214 /* IP10_25_23 [3] */ 5215 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, 5216 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B, 5217 /* IP10_22_19 [4] */ 5218 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0, 5219 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, 5220 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0, 5221 /* IP10_18_15 [4] */ 5222 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0, 5223 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, 5224 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, 5225 0, 0, 0, 0, 0, 0, 5226 /* IP10_14_11 [4] */ 5227 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, 5228 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, 5229 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, 5230 0, 0, 0, 0, 0, 0, 0, 5231 /* IP10_10_7 [4] */ 5232 FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, 5233 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, 5234 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, 5235 0, 0, 0, 0, 0, 0, 0, 5236 /* IP10_6_4 [3] */ 5237 FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, 5238 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, 5239 FN_VI3_DATA0_B, 0, 5240 /* IP10_3_0 [4] */ 5241 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, 5242 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, 5243 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, } 5244 }, 5245 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, 5246 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) { 5247 /* IP11_31_30 [2] */ 5248 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, 5249 /* IP11_29_27 [3] */ 5250 FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, 5251 0, 0, 0, 5252 /* IP11_26_24 [3] */ 5253 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B, 5254 0, 0, 0, 5255 /* IP11_23_22 [2] */ 5256 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0, 5257 /* IP11_21_18 [4] */ 5258 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, 5259 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0, 5260 /* IP11_17_15 [3] */ 5261 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, 5262 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0, 5263 /* IP11_14_13 [2] */ 5264 FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0, 5265 /* IP11_12_11 [2] */ 5266 FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0, 5267 /* IP11_10_9 [2] */ 5268 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0, 5269 /* IP11_8_7 [2] */ 5270 FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0, 5271 /* IP11_6_5 [2] */ 5272 FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0, 5273 /* IP11_4 [1] */ 5274 FN_SD3_CLK, FN_MMC1_CLK, 5275 /* IP11_3_0 [4] */ 5276 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, 5277 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, 5278 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, } 5279 }, 5280 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, 5281 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) { 5282 /* IP12_31 [1] */ 5283 0, 0, 5284 /* IP12_30_28 [3] */ 5285 FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B, 5286 FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, 5287 FN_CAN_DEBUGOUT4, 0, 0, 5288 /* IP12_27_25 [3] */ 5289 FN_SSI_SCK5, FN_SCIFB1_SCK, 5290 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, 5291 FN_CAN_DEBUGOUT3, 0, 0, 5292 /* IP12_24_23 [2] */ 5293 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, 5294 FN_CAN_DEBUGOUT2, 5295 /* IP12_22_20 [3] */ 5296 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, 5297 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0, 5298 /* IP12_19_17 [3] */ 5299 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, 5300 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0, 5301 /* IP12_16_14 [3] */ 5302 FN_SSI_SDATA3, FN_STP_ISCLK_0, 5303 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0, 5304 /* IP12_13_11 [3] */ 5305 FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, 5306 FN_CAN_STEP0, 0, 0, 0, 5307 /* IP12_10_8 [3] */ 5308 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, 5309 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0, 5310 /* IP12_7_6 [2] */ 5311 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, 5312 /* IP12_5_4 [2] */ 5313 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0, 5314 /* IP12_3_2 [2] */ 5315 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0, 5316 /* IP12_1_0 [2] */ 5317 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, } 5318 }, 5319 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, 5320 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) { 5321 /* IP13_31 [1] */ 5322 0, 0, 5323 /* IP13_30_29 [2] */ 5324 FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0, 5325 /* IP13_28_26 [3] */ 5326 FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, 5327 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0, 5328 /* IP13_25_23 [3] */ 5329 FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, 5330 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0, 5331 /* IP13_22_19 [4] */ 5332 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, 5333 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E, 5334 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0, 5335 /* IP13_18_16 [3] */ 5336 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, 5337 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0, 5338 /* IP13_15_13 [3] */ 5339 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK, 5340 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0, 5341 /* IP13_12_10 [3] */ 5342 FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5, 5343 FN_CAN_DEBUGOUT8, 0, 0, 5344 /* IP13_9_7 [3] */ 5345 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, 5346 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0, 5347 /* IP13_6_3 [4] */ 5348 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0, 5349 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, 5350 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0, 5351 /* IP13_2_0 [3] */ 5352 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, 5353 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, } 5354 }, 5355 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, 5356 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) { 5357 /* IP14_30 [1] */ 5358 0, 0, 5359 /* IP14_30_28 [3] */ 5360 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, 5361 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, 5362 FN_HRTS0_N_C, 0, 5363 /* IP14_27_25 [3] */ 5364 FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD, 5365 FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0, 5366 /* IP14_24_22 [3] */ 5367 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, 5368 FN_LCDOUT9, 0, 0, 0, 5369 /* IP14_21_19 [3] */ 5370 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, 5371 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0, 5372 /* IP14_18_16 [3] */ 5373 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N, 5374 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0, 5375 /* IP14_15_12 [4] */ 5376 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, 5377 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, 5378 0, 0, 0, 0, 0, 0, 0, 5379 /* IP14_11_9 [3] */ 5380 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1, 5381 0, 0, 0, 5382 /* IP14_8_6 [3] */ 5383 FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0, 5384 0, 0, 0, 5385 /* IP14_5_3 [3] */ 5386 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2, 5387 FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C, 5388 /* IP14_2_0 [3] */ 5389 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, 5390 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, 5391 FN_REMOCON, 0, } 5392 }, 5393 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, 5394 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) { 5395 /* IP15_31_30 [2] */ 5396 0, 0, 0, 0, 5397 /* IP15_29_28 [2] */ 5398 FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14, 5399 /* IP15_27_26 [2] */ 5400 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13, 5401 /* IP15_25_23 [3] */ 5402 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA, 5403 FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0, 5404 /* IP15_22_20 [3] */ 5405 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, 5406 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0, 5407 /* IP15_19_18 [2] */ 5408 FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21, 5409 /* IP15_17_16 [2] */ 5410 FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20, 5411 /* IP15_15_14 [2] */ 5412 FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0, 5413 /* IP15_13_12 [2] */ 5414 FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0, 5415 /* IP15_11_9 [3] */ 5416 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, 5417 0, 0, 0, 5418 /* IP15_8_6 [3] */ 5419 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17, 5420 FN_IIC2_SDA, FN_I2C2_SDA, 0, 5421 /* IP15_5_3 [3] */ 5422 FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16, 5423 FN_IIC2_SCL, FN_I2C2_SCL, 0, 5424 /* IP15_2_0 [3] */ 5425 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, 5426 FN_LCDOUT15, FN_SCIF_CLK_B, 0, } 5427 }, 5428 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, 5429 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) { 5430 /* IP16_31_28 [4] */ 5431 0, 0, 0, 0, 0, 0, 0, 0, 5432 0, 0, 0, 0, 0, 0, 0, 0, 5433 /* IP16_27_24 [4] */ 5434 0, 0, 0, 0, 0, 0, 0, 0, 5435 0, 0, 0, 0, 0, 0, 0, 0, 5436 /* IP16_23_20 [4] */ 5437 0, 0, 0, 0, 0, 0, 0, 0, 5438 0, 0, 0, 0, 0, 0, 0, 0, 5439 /* IP16_19_16 [4] */ 5440 0, 0, 0, 0, 0, 0, 0, 0, 5441 0, 0, 0, 0, 0, 0, 0, 0, 5442 /* IP16_15_12 [4] */ 5443 0, 0, 0, 0, 0, 0, 0, 0, 5444 0, 0, 0, 0, 0, 0, 0, 0, 5445 /* IP16_11_8 [4] */ 5446 0, 0, 0, 0, 0, 0, 0, 0, 5447 0, 0, 0, 0, 0, 0, 0, 0, 5448 /* IP16_7 [1] */ 5449 FN_USB1_OVC, FN_TCLK1_B, 5450 /* IP16_6 [1] */ 5451 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, 5452 /* IP16_5_3 [3] */ 5453 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, 5454 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0, 5455 /* IP16_2_0 [3] */ 5456 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, 5457 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, } 5458 }, 5459 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, 5460 3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 5461 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) { 5462 /* SEL_SCIF1 [3] */ 5463 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 5464 FN_SEL_SCIF1_4, 0, 0, 0, 5465 /* SEL_SCIFB [2] */ 5466 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0, 5467 /* SEL_SCIFB2 [2] */ 5468 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0, 5469 /* SEL_SCIFB1 [3] */ 5470 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, 5471 FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5, 5472 FN_SEL_SCIFB1_6, 0, 5473 /* SEL_SCIFA1 [2] */ 5474 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 5475 FN_SEL_SCIFA1_3, 5476 /* SEL_SCIF0 [1] */ 5477 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, 5478 /* SEL_SCIFA [1] */ 5479 FN_SEL_SCFA_0, FN_SEL_SCFA_1, 5480 /* SEL_SOF1 [1] */ 5481 FN_SEL_SOF1_0, FN_SEL_SOF1_1, 5482 /* SEL_SSI7 [2] */ 5483 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0, 5484 /* SEL_SSI6 [1] */ 5485 FN_SEL_SSI6_0, FN_SEL_SSI6_1, 5486 /* SEL_SSI5 [2] */ 5487 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0, 5488 /* SEL_VI3 [1] */ 5489 FN_SEL_VI3_0, FN_SEL_VI3_1, 5490 /* SEL_VI2 [1] */ 5491 FN_SEL_VI2_0, FN_SEL_VI2_1, 5492 /* SEL_VI1 [1] */ 5493 FN_SEL_VI1_0, FN_SEL_VI1_1, 5494 /* SEL_VI0 [1] */ 5495 FN_SEL_VI0_0, FN_SEL_VI0_1, 5496 /* SEL_TSIF1 [2] */ 5497 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0, 5498 /* RESERVED [1] */ 5499 0, 0, 5500 /* SEL_LBS [1] */ 5501 FN_SEL_LBS_0, FN_SEL_LBS_1, 5502 /* SEL_TSIF0 [2] */ 5503 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 5504 /* SEL_SOF3 [1] */ 5505 FN_SEL_SOF3_0, FN_SEL_SOF3_1, 5506 /* SEL_SOF0 [1] */ 5507 FN_SEL_SOF0_0, FN_SEL_SOF0_1, } 5508 }, 5509 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, 5510 3, 1, 1, 1, 2, 1, 2, 1, 2, 5511 1, 1, 1, 3, 3, 2, 3, 2, 2) { 5512 /* RESERVED [3] */ 5513 0, 0, 0, 0, 0, 0, 0, 0, 5514 /* SEL_TMU1 [1] */ 5515 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 5516 /* SEL_HSCIF1 [1] */ 5517 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, 5518 /* SEL_SCIFCLK [1] */ 5519 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, 5520 /* SEL_CAN0 [2] */ 5521 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 5522 /* SEL_CANCLK [1] */ 5523 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, 5524 /* SEL_SCIFA2 [2] */ 5525 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0, 5526 /* SEL_CAN1 [1] */ 5527 FN_SEL_CAN1_0, FN_SEL_CAN1_1, 5528 /* RESERVED [2] */ 5529 0, 0, 0, 0, 5530 /* SEL_SCIF2 [1] */ 5531 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, 5532 /* SEL_ADI [1] */ 5533 FN_SEL_ADI_0, FN_SEL_ADI_1, 5534 /* SEL_SSP [1] */ 5535 FN_SEL_SSP_0, FN_SEL_SSP_1, 5536 /* SEL_FM [3] */ 5537 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, 5538 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0, 5539 /* SEL_HSCIF0 [3] */ 5540 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 5541 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0, 5542 /* SEL_GPS [2] */ 5543 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0, 5544 /* RESERVED [3] */ 5545 0, 0, 0, 0, 0, 0, 0, 0, 5546 /* SEL_SIM [2] */ 5547 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0, 5548 /* SEL_SSI8 [2] */ 5549 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, } 5550 }, 5551 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, 5552 1, 1, 2, 4, 4, 2, 2, 5553 4, 2, 3, 2, 3, 2) { 5554 /* SEL_IICDVFS [1] */ 5555 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, 5556 /* SEL_IIC0 [1] */ 5557 FN_SEL_IIC0_0, FN_SEL_IIC0_1, 5558 /* RESERVED [2] */ 5559 0, 0, 0, 0, 5560 /* RESERVED [4] */ 5561 0, 0, 0, 0, 0, 0, 0, 0, 5562 0, 0, 0, 0, 0, 0, 0, 0, 5563 /* RESERVED [4] */ 5564 0, 0, 0, 0, 0, 0, 0, 0, 5565 0, 0, 0, 0, 0, 0, 0, 0, 5566 /* RESERVED [2] */ 5567 0, 0, 0, 0, 5568 /* SEL_IEB [2] */ 5569 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, 5570 /* RESERVED [4] */ 5571 0, 0, 0, 0, 0, 0, 0, 0, 5572 0, 0, 0, 0, 0, 0, 0, 0, 5573 /* RESERVED [2] */ 5574 0, 0, 0, 0, 5575 /* SEL_IIC2 [3] */ 5576 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, 5577 FN_SEL_IIC2_4, 0, 0, 0, 5578 /* SEL_IIC1 [2] */ 5579 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0, 5580 /* SEL_I2C2 [3] */ 5581 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 5582 FN_SEL_I2C2_4, 0, 0, 0, 5583 /* SEL_I2C1 [2] */ 5584 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, } 5585 }, 5586 { }, 5587 }; 5588 5589 const struct sh_pfc_soc_info r8a7790_pinmux_info = { 5590 .name = "r8a77900_pfc", 5591 .unlock_reg = 0xe6060000, /* PMMR */ 5592 5593 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 5594 5595 .pins = pinmux_pins, 5596 .nr_pins = ARRAY_SIZE(pinmux_pins), 5597 .groups = pinmux_groups, 5598 .nr_groups = ARRAY_SIZE(pinmux_groups), 5599 .functions = pinmux_functions, 5600 .nr_functions = ARRAY_SIZE(pinmux_functions), 5601 5602 .cfg_regs = pinmux_config_regs, 5603 5604 .gpio_data = pinmux_data, 5605 .gpio_data_size = ARRAY_SIZE(pinmux_data), 5606 }; 5607