Searched refs:idx_value (Results 1 - 6 of 6) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
H A Dr200.c157 u32 idx_value; r200_packet0_check() local
161 idx_value = radeon_get_ib_value(p, idx); r200_packet0_check()
189 track->zb.offset = idx_value; r200_packet0_check()
191 ib[idx] = idx_value + ((u32)reloc->gpu_offset); r200_packet0_check()
202 track->cb[0].offset = idx_value; r200_packet0_check()
204 ib[idx] = idx_value + ((u32)reloc->gpu_offset); r200_packet0_check()
226 tmp = idx_value & ~(0x7 << 2); r200_packet0_check()
230 ib[idx] = idx_value + ((u32)reloc->gpu_offset); r200_packet0_check()
273 track->textures[i].cube_info[face - 1].offset = idx_value; r200_packet0_check()
274 ib[idx] = idx_value + ((u32)reloc->gpu_offset); r200_packet0_check()
279 track->maxy = ((idx_value >> 16) & 0x7FF); r200_packet0_check()
298 tmp = idx_value & ~(0x7 << 16); r200_packet0_check()
302 ib[idx] = idx_value; r200_packet0_check()
304 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; r200_packet0_check()
308 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; r200_packet0_check()
312 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { r200_packet0_check()
330 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); r200_packet0_check()
333 if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) { r200_packet0_check()
338 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); r200_packet0_check()
343 switch (idx_value & 0xf) { r200_packet0_check()
368 ib[idx] = idx_value + ((u32)reloc->gpu_offset); r200_packet0_check()
372 uint32_t temp = idx_value >> 4; r200_packet0_check()
379 track->vap_vf_cntl = idx_value; r200_packet0_check()
383 track->max_indx = idx_value & 0x00FFFFFFUL; r200_packet0_check()
386 track->vtx_size = r200_get_vtx_size_0(idx_value); r200_packet0_check()
389 track->vtx_size += r200_get_vtx_size_1(idx_value); r200_packet0_check()
398 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; r200_packet0_check()
399 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; r200_packet0_check()
409 track->textures[i].pitch = idx_value + 32; r200_packet0_check()
419 track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK) r200_packet0_check()
421 tmp = (idx_value >> 23) & 0x7; r200_packet0_check()
424 tmp = (idx_value >> 27) & 0x7; r200_packet0_check()
444 track->textures[i].txdepth = idx_value & 0x7; r200_packet0_check()
445 tmp = (idx_value >> 16) & 0x3; r200_packet0_check()
475 if (idx_value & R200_TXFORMAT_NON_POWER2) { r200_packet0_check()
479 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); r200_packet0_check()
480 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); r200_packet0_check()
482 if (idx_value & R200_TXFORMAT_LOOKUP_DISABLE) r200_packet0_check()
484 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { r200_packet0_check()
521 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); r200_packet0_check()
522 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); r200_packet0_check()
531 tmp = idx_value; r200_packet0_check()
H A Dr300.c613 u32 idx_value; r300_packet0_check() local
617 idx_value = radeon_get_ib_value(p, idx); r300_packet0_check()
649 track->cb[i].offset = idx_value; r300_packet0_check()
651 ib[idx] = idx_value + ((u32)reloc->gpu_offset); r300_packet0_check()
662 track->zb.offset = idx_value; r300_packet0_check()
664 ib[idx] = idx_value + ((u32)reloc->gpu_offset); r300_packet0_check()
692 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ r300_packet0_check()
693 ((idx_value & ~31) + (u32)reloc->gpu_offset); r300_packet0_check()
702 tmp = idx_value + ((u32)reloc->gpu_offset); r300_packet0_check()
712 track->vap_vf_cntl = idx_value; r300_packet0_check()
716 track->vtx_size = idx_value & 0x7F; r300_packet0_check()
720 track->max_indx = idx_value & 0x00FFFFFFUL; r300_packet0_check()
726 track->vap_alt_nverts = idx_value & 0xFFFFFF; r300_packet0_check()
730 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; r300_packet0_check()
739 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ r300_packet0_check()
744 track->num_cb = ((idx_value >> 5) & 0x3) + 1; r300_packet0_check()
771 tmp = idx_value & ~(0x7 << 16); r300_packet0_check()
776 track->cb[i].pitch = idx_value & 0x3FFE; r300_packet0_check()
777 switch (((idx_value >> 21) & 0xF)) { r300_packet0_check()
792 ((idx_value >> 21) & 0xF)); r300_packet0_check()
807 ((idx_value >> 21) & 0xF)); r300_packet0_check()
814 if (idx_value & 2) { r300_packet0_check()
823 switch ((idx_value & 0xF)) { r300_packet0_check()
833 (idx_value & 0xF)); r300_packet0_check()
856 tmp = idx_value & ~(0x7 << 16); r300_packet0_check()
860 track->zb.pitch = idx_value & 0x3FFC; r300_packet0_check()
868 enabled = !!(idx_value & (1 << i)); r300_packet0_check()
891 tmp = (idx_value >> 25) & 0x3; r300_packet0_check()
893 switch ((idx_value & 0x1F)) { r300_packet0_check()
942 (idx_value & 0x1F)); r300_packet0_check()
954 (idx_value & 0x1F)); r300_packet0_check()
977 tmp = idx_value & 0x7; r300_packet0_check()
981 tmp = (idx_value >> 3) & 0x7; r300_packet0_check()
1005 tmp = idx_value & 0x3FFF; r300_packet0_check()
1008 tmp = ((idx_value >> 15) & 1) << 11; r300_packet0_check()
1010 tmp = ((idx_value >> 16) & 1) << 11; r300_packet0_check()
1014 if (idx_value & (1 << 14)) { r300_packet0_check()
1019 } else if (idx_value & (1 << 14)) { r300_packet0_check()
1043 tmp = idx_value & 0x7FF; r300_packet0_check()
1045 tmp = (idx_value >> 11) & 0x7FF; r300_packet0_check()
1047 tmp = (idx_value >> 26) & 0xF; r300_packet0_check()
1049 tmp = idx_value & (1 << 31); r300_packet0_check()
1051 tmp = (idx_value >> 22) & 0xF; r300_packet0_check()
1063 ib[idx] = idx_value + ((u32)reloc->gpu_offset); r300_packet0_check()
1067 track->color_channel_mask = idx_value; r300_packet0_check()
1075 if (idx_value & 0x1) r300_packet0_check()
1076 ib[idx] = idx_value & ~1; r300_packet0_check()
1081 track->zb_cb_clear = !!(idx_value & (1 << 5)); r300_packet0_check()
1085 if (idx_value & (R300_HIZ_ENABLE | r300_packet0_check()
1094 track->blend_read_enable = !!(idx_value & (1 << 2)); r300_packet0_check()
1106 track->aa.offset = idx_value; r300_packet0_check()
1108 ib[idx] = idx_value + ((u32)reloc->gpu_offset); r300_packet0_check()
1111 track->aa.pitch = idx_value & 0x3FFE; r300_packet0_check()
1115 track->aaresolve = idx_value & 0x1; r300_packet0_check()
1122 if (idx_value && (p->rdev->hyperz_filp != p->filp)) r300_packet0_check()
1126 if (idx_value && (p->rdev->hyperz_filp != p->filp)) r300_packet0_check()
1144 reg, idx, idx_value); r300_packet0_check()
H A Dr600_cs.c1636 u32 idx_value; r600_packet3_check() local
1641 idx_value = radeon_get_ib_value(p, idx); r600_packet3_check()
1674 (idx_value & 0xfffffff0) + r600_packet3_check()
1715 idx_value + r600_packet3_check()
1757 if (idx_value & 0x10) { r600_packet3_check()
1772 } else if (idx_value & 0x100) { r600_packet3_check()
1909 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET; r600_packet3_check()
1925 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET; r600_packet3_check()
1945 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET; r600_packet3_check()
2025 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET; r600_packet3_check()
2036 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET; r600_packet3_check()
2046 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET; r600_packet3_check()
2056 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET; r600_packet3_check()
2070 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET; r600_packet3_check()
2089 if (idx_value > 3) { r600_packet3_check()
2102 if (reloc->robj != track->vgt_strmout_bo[idx_value]) { r600_packet3_check()
2108 if (offset != track->vgt_strmout_bo_offset[idx_value]) { r600_packet3_check()
2110 offset, track->vgt_strmout_bo_offset[idx_value]); r600_packet3_check()
2138 if (idx_value & 0x1) { r600_packet3_check()
2157 if (((idx_value >> 1) & 0x3) == 2) { r600_packet3_check()
2210 if (idx_value & 0x1) { r600_packet3_check()
2234 if (idx_value & 0x2) { r600_packet3_check()
2479 u32 idx, idx_value; r600_dma_cs_parse() local
2534 idx_value = radeon_get_ib_value(p, idx + 2); r600_dma_cs_parse()
2536 if (idx_value & (1 << 31)) { r600_dma_cs_parse()
H A Dr100.c1310 u32 idx_value; r100_packet3_load_vbpntr() local
1330 idx_value = radeon_get_ib_value(p, idx); r100_packet3_load_vbpntr()
1333 track->arrays[i + 0].esize = idx_value >> 8; r100_packet3_load_vbpntr()
1345 track->arrays[i + 1].esize = idx_value >> 24; r100_packet3_load_vbpntr()
1356 idx_value = radeon_get_ib_value(p, idx); r100_packet3_load_vbpntr()
1359 track->arrays[i + 0].esize = idx_value >> 8; r100_packet3_load_vbpntr()
1562 u32 idx_value; r100_packet0_check() local
1567 idx_value = radeon_get_ib_value(p, idx); r100_packet0_check()
1596 track->zb.offset = idx_value; r100_packet0_check()
1598 ib[idx] = idx_value + ((u32)reloc->gpu_offset); r100_packet0_check()
1609 track->cb[0].offset = idx_value; r100_packet0_check()
1611 ib[idx] = idx_value + ((u32)reloc->gpu_offset); r100_packet0_check()
1630 tmp = idx_value & ~(0x7 << 2); r100_packet0_check()
1634 ib[idx] = idx_value + ((u32)reloc->gpu_offset); r100_packet0_check()
1651 track->textures[0].cube_info[i].offset = idx_value; r100_packet0_check()
1652 ib[idx] = idx_value + ((u32)reloc->gpu_offset); r100_packet0_check()
1669 track->textures[1].cube_info[i].offset = idx_value; r100_packet0_check()
1670 ib[idx] = idx_value + ((u32)reloc->gpu_offset); r100_packet0_check()
1687 track->textures[2].cube_info[i].offset = idx_value; r100_packet0_check()
1688 ib[idx] = idx_value + ((u32)reloc->gpu_offset); r100_packet0_check()
1693 track->maxy = ((idx_value >> 16) & 0x7FF); r100_packet0_check()
1711 tmp = idx_value & ~(0x7 << 16); r100_packet0_check()
1715 ib[idx] = idx_value; r100_packet0_check()
1717 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; r100_packet0_check()
1721 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; r100_packet0_check()
1725 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { r100_packet0_check()
1743 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); r100_packet0_check()
1746 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); r100_packet0_check()
1751 switch (idx_value & 0xf) { r100_packet0_check()
1776 ib[idx] = idx_value + ((u32)reloc->gpu_offset); r100_packet0_check()
1780 uint32_t temp = idx_value >> 4; r100_packet0_check()
1787 track->vap_vf_cntl = idx_value; r100_packet0_check()
1790 track->vtx_size = r100_get_vtx_size(idx_value); r100_packet0_check()
1796 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; r100_packet0_check()
1797 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; r100_packet0_check()
1804 track->textures[i].pitch = idx_value + 32; r100_packet0_check()
1811 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) r100_packet0_check()
1813 tmp = (idx_value >> 23) & 0x7; r100_packet0_check()
1816 tmp = (idx_value >> 27) & 0x7; r100_packet0_check()
1825 if (idx_value & RADEON_TXFORMAT_NON_POWER2) { r100_packet0_check()
1829 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); r100_packet0_check()
1830 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); r100_packet0_check()
1832 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) r100_packet0_check()
1834 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { r100_packet0_check()
1870 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); r100_packet0_check()
1871 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); r100_packet0_check()
1877 tmp = idx_value; r100_packet0_check()
H A Devergreen_cs.c1803 u32 idx_value; evergreen_packet3_check() local
1808 idx_value = radeon_get_ib_value(p, idx); evergreen_packet3_check()
1841 (idx_value & 0xfffffff0) + evergreen_packet3_check()
1887 idx_value + evergreen_packet3_check()
1922 idx_value + evergreen_packet3_check()
2033 if (idx_value != 1) { evergreen_packet3_check()
2066 if (idx_value + size > track->indirect_draw_buffer_size) { evergreen_packet3_check()
2068 idx_value, size, track->indirect_draw_buffer_size); evergreen_packet3_check()
2100 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); evergreen_packet3_check()
2113 if (idx_value & 0x10) { evergreen_packet3_check()
2128 } else if (idx_value & 0x100) { evergreen_packet3_check()
2316 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; evergreen_packet3_check()
2332 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START; evergreen_packet3_check()
2352 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START; evergreen_packet3_check()
2455 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START; evergreen_packet3_check()
2465 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START; evergreen_packet3_check()
2475 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START; evergreen_packet3_check()
2489 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START; evergreen_packet3_check()
2504 if (idx_value & 0x1) { evergreen_packet3_check()
2523 if (((idx_value >> 1) & 0x3) == 2) { evergreen_packet3_check()
2576 if (idx_value & 0x1) { evergreen_packet3_check()
2600 if (idx_value & 0x2) { evergreen_packet3_check()
3310 u32 idx_value = ib[idx]; evergreen_vm_packet3_check() local
3318 if (idx_value != 1) { evergreen_vm_packet3_check()
3365 if (idx_value & 0x100) { evergreen_vm_packet3_check()
3372 if (idx_value & 0x2) { evergreen_vm_packet3_check()
3379 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; evergreen_vm_packet3_check()
3411 start_reg = idx_value << 2; evergreen_vm_packet3_check()
H A Dsi.c4468 u32 idx_value = ib[idx]; si_vm_packet3_cp_dma_check() local
4472 start_reg = idx_value << 2; si_vm_packet3_cp_dma_check()
4519 u32 idx_value = ib[idx]; si_vm_packet3_gfx_check() local
4570 if ((idx_value & 0xf00) == 0) { si_vm_packet3_gfx_check()
4577 if ((idx_value & 0xf00) == 0) { si_vm_packet3_gfx_check()
4579 if (idx_value & 0x10000) { si_vm_packet3_gfx_check()
4592 if (idx_value & 0x100) { si_vm_packet3_gfx_check()
4599 if (idx_value & 0x2) { si_vm_packet3_gfx_check()
4606 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; si_vm_packet3_gfx_check()
4637 u32 idx_value = ib[idx]; si_vm_packet3_compute_check() local
4673 if ((idx_value & 0xf00) == 0) { si_vm_packet3_compute_check()
4680 if ((idx_value & 0xf00) == 0) { si_vm_packet3_compute_check()
4682 if (idx_value & 0x10000) { si_vm_packet3_compute_check()
4695 if (idx_value & 0x100) { si_vm_packet3_compute_check()
4702 if (idx_value & 0x2) { si_vm_packet3_compute_check()

Completed in 258 milliseconds