/linux-4.1.27/drivers/isdn/hisax/ |
H A D | Makefile | 30 hisax-$(CONFIG_HISAX_16_0) += teles0.o isac.o arcofi.o hscx.o 31 hisax-$(CONFIG_HISAX_16_3) += teles3.o isac.o arcofi.o hscx.o 32 hisax-$(CONFIG_HISAX_TELESPCI) += telespci.o isac.o arcofi.o hscx.o 33 hisax-$(CONFIG_HISAX_S0BOX) += s0box.o isac.o arcofi.o hscx.o 34 hisax-$(CONFIG_HISAX_AVM_A1) += avm_a1.o isac.o arcofi.o hscx.o 35 hisax-$(CONFIG_HISAX_AVM_A1_PCMCIA) += avm_a1p.o isac.o arcofi.o hscx.o 37 hisax-$(CONFIG_HISAX_ELSA) += elsa.o isac.o arcofi.o hscx.o 38 hisax-$(CONFIG_HISAX_IX1MICROR2) += ix1_micro.o isac.o arcofi.o hscx.o 39 hisax-$(CONFIG_HISAX_DIEHLDIVA) += diva.o isac.o arcofi.o hscx.o ipacx.o 40 hisax-$(CONFIG_HISAX_ASUSCOM) += asuscom.o isac.o arcofi.o hscx.o 42 hisax-$(CONFIG_HISAX_SEDLBAUER) += sedlbauer.o isac.o arcofi.o hscx.o \ 44 hisax-$(CONFIG_HISAX_SPORTSTER) += sportster.o isac.o arcofi.o hscx.o 45 hisax-$(CONFIG_HISAX_MIC) += mic.o isac.o arcofi.o hscx.o 51 hisax-$(CONFIG_HISAX_NICCY) += niccy.o isac.o arcofi.o hscx.o 53 hisax-$(CONFIG_HISAX_HSTSAPHIR) += saphir.o isac.o arcofi.o hscx.o 55 hisax-$(CONFIG_HISAX_SCT_QUADRO) += bkm_a8.o isac.o arcofi.o hscx.o 56 hisax-$(CONFIG_HISAX_GAZEL) += gazel.o isac.o arcofi.o hscx.o
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H A D | hscx_irq.c | 17 waitforCEC(struct IsdnCardState *cs, int hscx) waitforCEC() argument 21 while ((READHSCX(cs, hscx, HSCX_STAR) & 0x04) && to) { waitforCEC() 31 waitforXFW(struct IsdnCardState *cs, int hscx) waitforXFW() argument 35 while (((READHSCX(cs, hscx, HSCX_STAR) & 0x44) != 0x40) && to) { waitforXFW() 44 WriteHSCXCMDR(struct IsdnCardState *cs, int hscx, u_char data) WriteHSCXCMDR() argument 46 waitforCEC(cs, hscx); WriteHSCXCMDR() 47 WRITEHSCX(cs, hscx, HSCX_CMDR, data); WriteHSCXCMDR() 61 if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) { hscx_empty_fifo() 64 WriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80); hscx_empty_fifo() 65 bcs->hw.hscx.rcvidx = 0; hscx_empty_fifo() 68 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx; hscx_empty_fifo() 69 bcs->hw.hscx.rcvidx += count; hscx_empty_fifo() 70 READHSCXFIFO(cs, bcs->hw.hscx.hscx, ptr, count); hscx_empty_fifo() 71 WriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80); hscx_empty_fifo() 76 bcs->hw.hscx.hscx ? 'B' : 'A', count); hscx_empty_fifo() 105 waitforXFW(cs, bcs->hw.hscx.hscx); hscx_fill_fifo() 109 bcs->hw.hscx.count += count; hscx_fill_fifo() 110 WRITEHSCXFIFO(cs, bcs->hw.hscx.hscx, ptr, count); hscx_fill_fifo() 111 WriteHSCXCMDR(cs, bcs->hw.hscx.hscx, more ? 0x8 : 0xa); hscx_fill_fifo() 116 bcs->hw.hscx.hscx ? 'B' : 'A', count); hscx_fill_fifo() 123 hscx_interrupt(struct IsdnCardState *cs, u_char val, u_char hscx) hscx_interrupt() argument 126 struct BCState *bcs = cs->bcs + hscx; hscx_interrupt() 135 r = READHSCX(cs, hscx, HSCX_RSTA); hscx_interrupt() 159 WriteHSCXCMDR(cs, hscx, 0x80); hscx_interrupt() 161 count = READHSCX(cs, hscx, HSCX_RBCL) & ( hscx_interrupt() 166 if ((count = bcs->hw.hscx.rcvidx - 1) > 0) { hscx_interrupt() 172 memcpy(skb_put(skb, count), bcs->hw.hscx.rcvbuf, count); hscx_interrupt() 177 bcs->hw.hscx.rcvidx = 0; hscx_interrupt() 187 memcpy(skb_put(skb, fifo_size), bcs->hw.hscx.rcvbuf, fifo_size); hscx_interrupt() 190 bcs->hw.hscx.rcvidx = 0; hscx_interrupt() 204 bcs->ackcnt += bcs->hw.hscx.count; hscx_interrupt() 209 bcs->hw.hscx.count = 0; hscx_interrupt() 214 bcs->hw.hscx.count = 0; hscx_interrupt() 245 skb_push(bcs->tx_skb, bcs->hw.hscx.count); hscx_int_main() 246 bcs->tx_cnt += bcs->hw.hscx.count; hscx_int_main() 247 bcs->hw.hscx.count = 0; hscx_int_main() 249 WriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01); hscx_int_main() 275 skb_push(bcs->tx_skb, bcs->hw.hscx.count); hscx_int_main() 276 bcs->tx_cnt += bcs->hw.hscx.count; hscx_int_main() 277 bcs->hw.hscx.count = 0; hscx_int_main() 279 WriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01); hscx_int_main()
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H A D | hscx.c | 1 /* $Id: hscx.c,v 1.24.2.4 2004/01/24 20:47:23 keil Exp $ 15 #include "hscx.h" 44 int hscx = bcs->hw.hscx.hscx; modehscx() local 47 debugl1(cs, "hscx %c mode %d ichan %d", modehscx() 48 'A' + hscx, mode, bc); modehscx() 51 cs->BC_Write_Reg(cs, hscx, HSCX_XAD1, 0xFF); modehscx() 52 cs->BC_Write_Reg(cs, hscx, HSCX_XAD2, 0xFF); modehscx() 53 cs->BC_Write_Reg(cs, hscx, HSCX_RAH2, 0xFF); modehscx() 54 cs->BC_Write_Reg(cs, hscx, HSCX_XBCH, 0x0); modehscx() 55 cs->BC_Write_Reg(cs, hscx, HSCX_RLCR, 0x0); modehscx() 56 cs->BC_Write_Reg(cs, hscx, HSCX_CCR1, modehscx() 58 cs->BC_Write_Reg(cs, hscx, HSCX_CCR2, 0x30); modehscx() 59 cs->BC_Write_Reg(cs, hscx, HSCX_XCCR, 7); modehscx() 60 cs->BC_Write_Reg(cs, hscx, HSCX_RCCR, 7); modehscx() 63 if (test_bit(HW_IOM1, &cs->HW_Flags) && (hscx == 0)) modehscx() 67 cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, modehscx() 68 test_bit(HW_IOM1, &cs->HW_Flags) ? 0x7 : bcs->hw.hscx.tsaxr0); modehscx() 69 cs->BC_Write_Reg(cs, hscx, HSCX_TSAR, modehscx() 70 test_bit(HW_IOM1, &cs->HW_Flags) ? 0x7 : bcs->hw.hscx.tsaxr0); modehscx() 72 cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, bcs->hw.hscx.tsaxr1); modehscx() 73 cs->BC_Write_Reg(cs, hscx, HSCX_TSAR, bcs->hw.hscx.tsaxr1); modehscx() 77 cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, 0x1f); modehscx() 78 cs->BC_Write_Reg(cs, hscx, HSCX_TSAR, 0x1f); modehscx() 79 cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0x84); modehscx() 82 cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0xe4); modehscx() 85 cs->BC_Write_Reg(cs, hscx, HSCX_CCR1, modehscx() 87 cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0x8c); modehscx() 91 cs->BC_Write_Reg(cs, hscx, HSCX_CMDR, 0x41); modehscx() 92 cs->BC_Write_Reg(cs, hscx, HSCX_ISTA, 0x00); modehscx() 110 bcs->hw.hscx.count = 0; hscx_l2l1() 122 bcs->hw.hscx.count = 0; hscx_l2l1() 160 kfree(bcs->hw.hscx.rcvbuf); close_hscxstate() 161 bcs->hw.hscx.rcvbuf = NULL; close_hscxstate() 178 if (!(bcs->hw.hscx.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) { open_hscxstate() 180 "HiSax: No memory for hscx.rcvbuf\n"); open_hscxstate() 188 kfree(bcs->hw.hscx.rcvbuf); open_hscxstate() 189 bcs->hw.hscx.rcvbuf = NULL; open_hscxstate() 198 bcs->hw.hscx.rcvidx = 0; open_hscxstate() 250 cs->bcs[0].hw.hscx.hscx = 0; inithscx() 251 cs->bcs[1].hw.hscx.hscx = 1; inithscx() 252 cs->bcs[0].hw.hscx.tsaxr0 = 0x2f; inithscx() 253 cs->bcs[0].hw.hscx.tsaxr1 = 3; inithscx() 254 cs->bcs[1].hw.hscx.tsaxr0 = 0x2f; inithscx() 255 cs->bcs[1].hw.hscx.tsaxr1 = 3; inithscx()
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H A D | jade_irq.c | 51 if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) { jade_empty_fifo() 54 WriteJADECMDR(cs, bcs->hw.hscx.hscx, jade_HDLC_RCMD, jadeRCMD_RMC); jade_empty_fifo() 55 bcs->hw.hscx.rcvidx = 0; jade_empty_fifo() 58 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx; jade_empty_fifo() 59 bcs->hw.hscx.rcvidx += count; jade_empty_fifo() 60 READJADEFIFO(cs, bcs->hw.hscx.hscx, ptr, count); jade_empty_fifo() 61 WriteJADECMDR(cs, bcs->hw.hscx.hscx, jade_HDLC_RCMD, jadeRCMD_RMC); jade_empty_fifo() 66 bcs->hw.hscx.hscx ? 'B' : 'A', count); jade_empty_fifo() 95 waitforXFW(cs, bcs->hw.hscx.hscx); jade_fill_fifo() 99 bcs->hw.hscx.count += count; jade_fill_fifo() 100 WRITEJADEFIFO(cs, bcs->hw.hscx.hscx, ptr, count); jade_fill_fifo() 101 WriteJADECMDR(cs, bcs->hw.hscx.hscx, jade_HDLC_XCMD, more ? jadeXCMD_XF : (jadeXCMD_XF | jadeXCMD_XME)); jade_fill_fifo() 106 bcs->hw.hscx.hscx ? 'B' : 'A', count); jade_fill_fifo() 144 if ((count = bcs->hw.hscx.rcvidx - 1) > 0) { jade_interrupt() 150 memcpy(skb_put(skb, count), bcs->hw.hscx.rcvbuf, count); jade_interrupt() 155 bcs->hw.hscx.rcvidx = 0; jade_interrupt() 165 memcpy(skb_put(skb, fifo_size), bcs->hw.hscx.rcvbuf, fifo_size); jade_interrupt() 168 bcs->hw.hscx.rcvidx = 0; jade_interrupt() 182 bcs->ackcnt += bcs->hw.hscx.count; jade_interrupt() 187 bcs->hw.hscx.count = 0; jade_interrupt() 192 bcs->hw.hscx.count = 0; jade_interrupt() 222 skb_push(bcs->tx_skb, bcs->hw.hscx.count); jade_int_main() 223 bcs->tx_cnt += bcs->hw.hscx.count; jade_int_main() 224 bcs->hw.hscx.count = 0; jade_int_main() 226 WriteJADECMDR(cs, bcs->hw.hscx.hscx, jade_HDLC_XCMD, jadeXCMD_XRES); jade_int_main()
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H A D | avm_a1.c | 16 #include "hscx.h" 80 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument 82 return (readreg(cs->hw.avm.hscx[hscx], offset)); ReadHSCX() 86 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument 88 writereg(cs->hw.avm.hscx[hscx], offset, value); WriteHSCX() 95 #define READHSCX(cs, nr, reg) readreg(cs->hw.avm.hscx[nr], reg) 96 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.avm.hscx[nr], reg, data) 117 val = readreg(cs->hw.avm.hscx[1], HSCX_ISTA); avm_a1_interrupt() 127 writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0xFF); avm_a1_interrupt() 128 writereg(cs->hw.avm.hscx[1], HSCX_MASK, 0xFF); avm_a1_interrupt() 131 writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0x0); avm_a1_interrupt() 132 writereg(cs->hw.avm.hscx[1], HSCX_MASK, 0x0); avm_a1_interrupt() 146 release_region(cs->hw.avm.hscx[0] + 32, 32); release_ioregs() 150 release_region(cs->hw.avm.hscx[1] + 32, 32); release_ioregs() 193 cs->hw.avm.hscx[0] = card->para[1] + 0x400 - 0x20; setup_avm_a1() 194 cs->hw.avm.hscx[1] = card->para[1] + 0xc00 - 0x20; setup_avm_a1() 221 if (!request_region(cs->hw.avm.hscx[0] + 32, 32, "HiSax hscx A")) { setup_avm_a1() 223 "HiSax: AVM A1 hscx A ports %x-%x already in use\n", setup_avm_a1() 224 cs->hw.avm.hscx[0] + 32, setup_avm_a1() 225 cs->hw.avm.hscx[0] + 64); setup_avm_a1() 229 if (!request_region(cs->hw.avm.hscxfifo[0], 1, "HiSax hscx A fifo")) { setup_avm_a1() 231 "HiSax: AVM A1 hscx A fifo port %x already in use\n", setup_avm_a1() 236 if (!request_region(cs->hw.avm.hscx[1] + 32, 32, "HiSax hscx B")) { setup_avm_a1() 238 "HiSax: AVM A1 hscx B ports %x-%x already in use\n", setup_avm_a1() 239 cs->hw.avm.hscx[1] + 32, setup_avm_a1() 240 cs->hw.avm.hscx[1] + 64); setup_avm_a1() 244 if (!request_region(cs->hw.avm.hscxfifo[1], 1, "HiSax hscx B fifo")) { setup_avm_a1() 246 "HiSax: AVM A1 hscx B fifo port %x already in use\n", setup_avm_a1() 285 "HiSax: hscx A:0x%X/0x%X hscx B:0x%X/0x%X\n", setup_avm_a1() 286 cs->hw.avm.hscx[0] + 32, cs->hw.avm.hscxfifo[0], setup_avm_a1() 287 cs->hw.avm.hscx[1] + 32, cs->hw.avm.hscxfifo[1]); setup_avm_a1()
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H A D | teles3.c | 20 #include "hscx.h" 80 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument 82 return (readreg(cs->hw.teles3.hscx[hscx], offset)); ReadHSCX() 86 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument 88 writereg(cs->hw.teles3.hscx[hscx], offset, value); WriteHSCX() 95 #define READHSCX(cs, nr, reg) readreg(cs->hw.teles3.hscx[nr], reg) 96 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.hscx[nr], reg, data) 112 val = readreg(cs->hw.teles3.hscx[1], HSCX_ISTA); teles3_interrupt() 121 val = readreg(cs->hw.teles3.hscx[1], HSCX_ISTA); teles3_interrupt() 135 writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF); teles3_interrupt() 136 writereg(cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF); teles3_interrupt() 139 writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0x0); teles3_interrupt() 140 writereg(cs->hw.teles3.hscx[1], HSCX_MASK, 0x0); teles3_interrupt() 151 release_region(cs->hw.teles3.hscx[0] + 32, 32); release_ioregs() 153 release_region(cs->hw.teles3.hscx[1] + 32, 32); release_ioregs() 160 release_region(cs->hw.teles3.hscx[1], 96); release_io_teles3() 339 cs->hw.teles3.hscx[0] = cs->hw.teles3.cfg_reg - 0xc20; setup_teles3() 340 cs->hw.teles3.hscx[1] = cs->hw.teles3.cfg_reg - 0x820; setup_teles3() 343 cs->hw.teles3.hscx[0] = card->para[1] - 0x20; setup_teles3() 344 cs->hw.teles3.hscx[1] = card->para[1]; setup_teles3() 349 cs->hw.teles3.hscx[0] = card->para[1] - 32; setup_teles3() 350 cs->hw.teles3.hscx[1] = card->para[1]; setup_teles3() 354 cs->hw.teles3.hscx[0] = card->para[2] - 32; setup_teles3() 355 cs->hw.teles3.hscx[1] = card->para[2]; setup_teles3() 359 cs->hw.teles3.hscxfifo[0] = cs->hw.teles3.hscx[0] + 0x3e; setup_teles3() 360 cs->hw.teles3.hscxfifo[1] = cs->hw.teles3.hscx[1] + 0x3e; setup_teles3() 362 if (!request_region(cs->hw.teles3.hscx[1], 96, "HiSax Teles PCMCIA")) { setup_teles3() 366 cs->hw.teles3.hscx[1], setup_teles3() 367 cs->hw.teles3.hscx[1] + 96); setup_teles3() 407 if (!request_region(cs->hw.teles3.hscx[0] + 32, 32, "HiSax hscx A")) { setup_teles3() 409 "HiSax: %s hscx A ports %x-%x already in use\n", setup_teles3() 411 cs->hw.teles3.hscx[0] + 32, setup_teles3() 412 cs->hw.teles3.hscx[0] + 64); setup_teles3() 423 if (!request_region(cs->hw.teles3.hscx[1] + 32, 32, "HiSax hscx B")) { setup_teles3() 425 "HiSax: %s hscx B ports %x-%x already in use\n", setup_teles3() 427 cs->hw.teles3.hscx[1] + 32, setup_teles3() 428 cs->hw.teles3.hscx[1] + 64); setup_teles3() 472 "HiSax: hscx A:0x%X hscx B:0x%X\n", setup_teles3() 473 cs->hw.teles3.hscx[0] + 32, cs->hw.teles3.hscx[1] + 32); setup_teles3()
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H A D | s0box.c | 16 #include "hscx.h" 120 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument 122 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset)); ReadHSCX() 126 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument 128 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset, value); WriteHSCX() 135 #define READHSCX(cs, nr, reg) readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg) 136 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg, data) 152 val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_ISTA); s0box_interrupt() 161 val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_ISTA); s0box_interrupt() 175 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF); s0box_interrupt() 176 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF); s0box_interrupt() 179 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0x0); s0box_interrupt() 180 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_MASK, 0x0); s0box_interrupt() 224 cs->hw.teles3.hscx[0] = -0x20; setup_s0box() 225 cs->hw.teles3.hscx[1] = 0x0; setup_s0box() 228 cs->hw.teles3.hscxfifo[0] = cs->hw.teles3.hscx[0] + 0x3e; setup_s0box() 229 cs->hw.teles3.hscxfifo[1] = cs->hw.teles3.hscx[1] + 0x3e; setup_s0box() 240 printk(KERN_INFO "HiSax: hscx A:0x%x hscx B:0x%x\n", setup_s0box() 241 cs->hw.teles3.hscx[0], cs->hw.teles3.hscx[1]); setup_s0box()
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H A D | ipacx.c | 6 * Derived from hisax_isac.c, isac.c, hscx.c and others 47 static void bch_int(struct IsdnCardState *cs, u_char hscx); 52 static void bch_init(struct IsdnCardState *cs, int hscx); 460 bcs->hw.hscx.count = 0; bch_l2l1() 472 bcs->hw.hscx.count = 0; bch_l2l1() 511 u_char *ptr, hscx; bch_empty_fifo() local 516 hscx = bcs->hw.hscx.hscx; bch_empty_fifo() 521 if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) { bch_empty_fifo() 524 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC bch_empty_fifo() 525 bcs->hw.hscx.rcvidx = 0; bch_empty_fifo() 529 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx; bch_empty_fifo() 531 while (cnt--) *ptr++ = cs->BC_Read_Reg(cs, hscx, IPACX_RFIFOB); bch_empty_fifo() 532 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC bch_empty_fifo() 534 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx; bch_empty_fifo() 535 bcs->hw.hscx.rcvidx += count; bch_empty_fifo() 540 t += sprintf(t, "bch_empty_fifo() B-%d cnt %d", hscx, count); bch_empty_fifo() 554 u_char *ptr, *p, hscx; bch_fill_fifo() local 563 hscx = bcs->hw.hscx.hscx; bch_fill_fifo() 576 bcs->hw.hscx.count += count; bch_fill_fifo() 577 while (cnt--) cs->BC_Write_Reg(cs, hscx, IPACX_XFIFOB, *p++); bch_fill_fifo() 578 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, (more ? 0x08 : 0x0a)); bch_fill_fifo() 583 t += sprintf(t, "%s() B-%d cnt %d", __func__, hscx, count); bch_fill_fifo() 593 bch_int(struct IsdnCardState *cs, u_char hscx) bch_int() argument 601 bcs = cs->bcs + hscx; bch_int() 602 istab = cs->BC_Read_Reg(cs, hscx, IPACX_ISTAB); bch_int() 609 rstab = cs->BC_Read_Reg(cs, hscx, IPACX_RSTAB); bch_int() 613 debugl1(cs, "bch_int() B-%d: invalid frame", hscx); bch_int() 616 debugl1(cs, "bch_int() B-%d: RDO mode=%d", hscx, bcs->mode); bch_int() 619 debugl1(cs, "bch_int() B-%d: CRC error", hscx); bch_int() 620 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC bch_int() 623 count = cs->BC_Read_Reg(cs, hscx, IPACX_RBCLB) & (B_FIFO_SIZE - 1); bch_int() 626 if ((count = bcs->hw.hscx.rcvidx - 1) > 0) { bch_int() 632 memcpy(skb_put(skb, count), bcs->hw.hscx.rcvbuf, count); bch_int() 637 bcs->hw.hscx.rcvidx = 0; bch_int() 649 memcpy(skb_put(skb, B_FIFO_SIZE), bcs->hw.hscx.rcvbuf, B_FIFO_SIZE); bch_int() 652 bcs->hw.hscx.rcvidx = 0; bch_int() 659 debugl1(cs, "bch_int() B-%d: RFO error", hscx); bch_int() 660 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x40); // RRES bch_int() 673 bcs->ackcnt += bcs->hw.hscx.count; bch_int() 679 bcs->hw.hscx.count = 0; bch_int() 683 bcs->hw.hscx.count = 0; bch_int() 699 skb_push(bcs->tx_skb, bcs->hw.hscx.count); bch_int() 700 bcs->tx_cnt += bcs->hw.hscx.count; bch_int() 701 bcs->hw.hscx.count = 0; bch_int() 703 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x01); // XRES bch_int() 705 debugl1(cs, "bch_int() B-%d XDU error", hscx); bch_int() 716 int hscx = bcs->hw.hscx.hscx; bch_mode() local 720 debugl1(cs, "mode_bch() switch B-%d mode %d chan %d", hscx, mode, bc); bch_mode() 725 if (!hscx) bch_mode() 738 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC0); // rec off bch_mode() 739 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x30); // std adj. bch_mode() 740 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, 0xFF); // ints off bch_mode() 741 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments bch_mode() 744 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0x88); // ext transp mode bch_mode() 745 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x00); // xxx00000 bch_mode() 746 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments bch_mode() 747 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK); bch_mode() 750 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC8); // transp mode 0 bch_mode() 751 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x01); // idle=hdlc flags crc enabled bch_mode() 752 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments bch_mode() 753 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK); bch_mode() 765 kfree(bcs->hw.hscx.rcvbuf); bch_close_state() 766 bcs->hw.hscx.rcvbuf = NULL; bch_close_state() 785 if (!(bcs->hw.hscx.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) { bch_open_state() 787 "HiSax open_bchstate(): No memory for hscx.rcvbuf\n"); bch_open_state() 795 kfree(bcs->hw.hscx.rcvbuf); bch_open_state() 796 bcs->hw.hscx.rcvbuf = NULL; bch_open_state() 805 bcs->hw.hscx.rcvidx = 0; bch_open_state() 828 bch_init(struct IsdnCardState *cs, int hscx) bch_init() argument 830 cs->bcs[hscx].BC_SetStack = bch_setstack; bch_init() 831 cs->bcs[hscx].BC_Close = bch_close_state; bch_init() 832 cs->bcs[hscx].hw.hscx.hscx = hscx; bch_init() 833 cs->bcs[hscx].cs = cs; bch_init() 834 bch_mode(cs->bcs + hscx, 0, hscx); bch_init()
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H A D | diva.c | 21 #include "hscx.h" 180 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument 183 cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0))); ReadHSCX() 187 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument 190 cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX() 220 MemReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) MemReadHSCX() argument 222 return (memreadreg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0))); MemReadHSCX() 226 MemWriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) MemWriteHSCX() argument 228 memwritereg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0), value); MemWriteHSCX() 259 MemReadHSCX_IPACX(struct IsdnCardState *cs, int hscx, u_char offset) MemReadHSCX_IPACX() argument 262 (hscx ? IPACX_OFF_B2 : IPACX_OFF_B1))); MemReadHSCX_IPACX() 266 MemWriteHSCX_IPACX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) MemWriteHSCX_IPACX() argument 269 (hscx ? IPACX_OFF_B2 : IPACX_OFF_B1), value); MemWriteHSCX_IPACX() 277 cs->hw.diva.hscx, reg + (nr ? 0x40 : 0)) 279 cs->hw.diva.hscx, reg + (nr ? 0x40 : 0), data) 282 cs->hw.diva.hscx, (nr ? 0x40 : 0), ptr, cnt) 285 cs->hw.diva.hscx, (nr ? 0x40 : 0), ptr, cnt) 299 val = readreg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_ISTA + 0x40); diva_interrupt() 309 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0xFF); diva_interrupt() 310 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0xFF); diva_interrupt() 313 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0x0); diva_interrupt() 314 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0x0); diva_interrupt() 367 MemwaitforCEC(struct IsdnCardState *cs, int hscx) MemwaitforCEC() argument 371 while ((MemReadHSCX(cs, hscx, HSCX_STAR) & 0x04) && to) { MemwaitforCEC() 381 MemwaitforXFW(struct IsdnCardState *cs, int hscx) MemwaitforXFW() argument 385 while (((MemReadHSCX(cs, hscx, HSCX_STAR) & 0x44) != 0x40) && to) { MemwaitforXFW() 394 MemWriteHSCXCMDR(struct IsdnCardState *cs, int hscx, u_char data) MemWriteHSCXCMDR() argument 396 MemwaitforCEC(cs, hscx); MemWriteHSCXCMDR() 397 MemWriteHSCX(cs, hscx, HSCX_CMDR, data); MemWriteHSCXCMDR() 410 if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) { Memhscx_empty_fifo() 413 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80); Memhscx_empty_fifo() 414 bcs->hw.hscx.rcvidx = 0; Memhscx_empty_fifo() 417 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx; Memhscx_empty_fifo() 420 *ptr++ = memreadreg(cs->hw.diva.cfg_reg, bcs->hw.hscx.hscx ? 0x40 : 0); Memhscx_empty_fifo() 421 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80); Memhscx_empty_fifo() 422 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx; Memhscx_empty_fifo() 423 bcs->hw.hscx.rcvidx += count; Memhscx_empty_fifo() 428 bcs->hw.hscx.hscx ? 'B' : 'A', count); Memhscx_empty_fifo() 457 MemwaitforXFW(cs, bcs->hw.hscx.hscx); Memhscx_fill_fifo() 461 bcs->hw.hscx.count += count; Memhscx_fill_fifo() 463 memwritereg(cs->hw.diva.cfg_reg, bcs->hw.hscx.hscx ? 0x40 : 0, Memhscx_fill_fifo() 465 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, more ? 0x8 : 0xa); Memhscx_fill_fifo() 470 bcs->hw.hscx.hscx ? 'B' : 'A', count); Memhscx_fill_fifo() 477 Memhscx_interrupt(struct IsdnCardState *cs, u_char val, u_char hscx) Memhscx_interrupt() argument 480 struct BCState *bcs = cs->bcs + hscx; Memhscx_interrupt() 489 r = MemReadHSCX(cs, hscx, HSCX_RSTA); Memhscx_interrupt() 501 MemWriteHSCXCMDR(cs, hscx, 0x80); Memhscx_interrupt() 503 count = MemReadHSCX(cs, hscx, HSCX_RBCL) & ( Memhscx_interrupt() 508 if ((count = bcs->hw.hscx.rcvidx - 1) > 0) { Memhscx_interrupt() 514 memcpy(skb_put(skb, count), bcs->hw.hscx.rcvbuf, count); Memhscx_interrupt() 519 bcs->hw.hscx.rcvidx = 0; Memhscx_interrupt() 529 memcpy(skb_put(skb, fifo_size), bcs->hw.hscx.rcvbuf, fifo_size); Memhscx_interrupt() 532 bcs->hw.hscx.rcvidx = 0; Memhscx_interrupt() 546 bcs->ackcnt += bcs->hw.hscx.count; Memhscx_interrupt() 551 bcs->hw.hscx.count = 0; Memhscx_interrupt() 556 bcs->hw.hscx.count = 0; Memhscx_interrupt() 584 skb_push(bcs->tx_skb, bcs->hw.hscx.count); Memhscx_int_main() 585 bcs->tx_cnt += bcs->hw.hscx.count; Memhscx_int_main() 586 bcs->hw.hscx.count = 0; Memhscx_int_main() 588 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01); Memhscx_int_main() 611 skb_push(bcs->tx_skb, bcs->hw.hscx.count); Memhscx_int_main() 612 bcs->tx_cnt += bcs->hw.hscx.count; Memhscx_int_main() 613 bcs->hw.hscx.count = 0; Memhscx_int_main() 615 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01); Memhscx_int_main() 1017 cs->hw.diva.hscx = card->para[1] + DIVA_IPAC_DATA; setup_diva_isa() 1025 cs->hw.diva.hscx = card->para[1] + DIVA_HSCX_DATA; setup_diva_isa() 1109 cs->hw.diva.hscx = setup_diva_isapnp() 1122 cs->hw.diva.hscx = setup_diva_isapnp() 1217 cs->hw.diva.hscx = 0; setup_diva_pci() 1224 cs->hw.diva.hscx = cs->hw.diva.cfg_reg + DIVA_HSCX_DATA; setup_diva_pci()
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H A D | ix1_micro.c | 24 #include "hscx.h" 100 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument 103 cs->hw.ix1.hscx, offset + (hscx ? 0x40 : 0))); ReadHSCX() 107 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument 110 cs->hw.ix1.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX() 114 cs->hw.ix1.hscx, reg + (nr ? 0x40 : 0)) 116 cs->hw.ix1.hscx, reg + (nr ? 0x40 : 0), data) 119 cs->hw.ix1.hscx, (nr ? 0x40 : 0), ptr, cnt) 122 cs->hw.ix1.hscx, (nr ? 0x40 : 0), ptr, cnt) 134 val = readreg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_ISTA + 0x40); ix1micro_interrupt() 142 val = readreg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_ISTA + 0x40); ix1micro_interrupt() 154 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0xFF); ix1micro_interrupt() 155 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0xFF); ix1micro_interrupt() 158 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0); ix1micro_interrupt() 159 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0); ix1micro_interrupt() 283 cs->hw.ix1.hscx = card->para[1] + HSCX_DATA_OFFSET; setup_ix1micro()
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H A D | mic.c | 16 #include "hscx.h" 90 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument 93 cs->hw.mic.hscx, offset + (hscx ? 0x40 : 0))); ReadHSCX() 97 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument 100 cs->hw.mic.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX() 108 cs->hw.mic.hscx, reg + (nr ? 0x40 : 0)) 110 cs->hw.mic.hscx, reg + (nr ? 0x40 : 0), data) 113 cs->hw.mic.hscx, (nr ? 0x40 : 0), ptr, cnt) 116 cs->hw.mic.hscx, (nr ? 0x40 : 0), ptr, cnt) 128 val = readreg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_ISTA + 0x40); mic_interrupt() 136 val = readreg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_ISTA + 0x40); mic_interrupt() 148 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK, 0xFF); mic_interrupt() 149 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK + 0x40, 0xFF); mic_interrupt() 152 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK, 0x0); mic_interrupt() 153 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK + 0x40, 0x0); mic_interrupt() 206 cs->hw.mic.hscx = cs->hw.mic.cfg_reg + MIC_HSCX; setup_mic()
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H A D | saphir.c | 18 #include "hscx.h" 92 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument 94 return (readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, ReadHSCX() 95 offset + (hscx ? 0x40 : 0))); ReadHSCX() 99 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument 101 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, WriteHSCX() 102 offset + (hscx ? 0x40 : 0), value); WriteHSCX() 106 cs->hw.saphir.hscx, reg + (nr ? 0x40 : 0)) 108 cs->hw.saphir.hscx, reg + (nr ? 0x40 : 0), data) 111 cs->hw.saphir.hscx, (nr ? 0x40 : 0), ptr, cnt) 114 cs->hw.saphir.hscx, (nr ? 0x40 : 0), ptr, cnt) 126 val = readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_ISTA + 0x40); saphir_interrupt() 134 val = readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_ISTA + 0x40); saphir_interrupt() 151 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0xFF); saphir_interrupt() 152 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0xFF); saphir_interrupt() 155 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0); saphir_interrupt() 156 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0); saphir_interrupt() 256 cs->hw.saphir.hscx = card->para[1] + HSCX_DATA; setup_saphir()
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H A D | jade.c | 3 * JADE stuff (derived from original hscx.c) 16 #include "hscx.h" 81 int jade = bcs->hw.hscx.hscx; modejade() 145 bcs->hw.hscx.count = 0; jade_l2l1() 157 bcs->hw.hscx.count = 0; jade_l2l1() 195 kfree(bcs->hw.hscx.rcvbuf); close_jadestate() 196 bcs->hw.hscx.rcvbuf = NULL; close_jadestate() 213 if (!(bcs->hw.hscx.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) { open_jadestate() 215 "HiSax: No memory for hscx.rcvbuf\n"); open_jadestate() 223 kfree(bcs->hw.hscx.rcvbuf); open_jadestate() 224 bcs->hw.hscx.rcvbuf = NULL; open_jadestate() 233 bcs->hw.hscx.rcvidx = 0; open_jadestate() 281 cs->bcs[0].hw.hscx.hscx = 0; initjade() 282 cs->bcs[1].hw.hscx.hscx = 1; initjade()
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H A D | gazel.c | 17 #include "hscx.h" 35 #define INT_HSCX_EN 0x1 /* 1 = enable IT hscx */ 36 #define INT_HSCX 0x4 /* 1 = IT hscx en cours */ 169 ReadHSCXfifo(struct IsdnCardState *cs, int hscx, u_char *data, int size) ReadHSCXfifo() argument 174 read_fifo(cs->hw.gazel.hscxfifo[hscx], data, size); ReadHSCXfifo() 178 read_fifo_ipac(cs->hw.gazel.ipac, hscx * 0x40, data, size); ReadHSCXfifo() 184 WriteHSCXfifo(struct IsdnCardState *cs, int hscx, u_char *data, int size) WriteHSCXfifo() argument 189 write_fifo(cs->hw.gazel.hscxfifo[hscx], data, size); WriteHSCXfifo() 193 write_fifo_ipac(cs->hw.gazel.ipac, hscx * 0x40, data, size); WriteHSCXfifo() 199 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument 207 return (readreg(cs->hw.gazel.hscx[hscx], off2)); ReadHSCX() 210 return (readreg_ipac(cs->hw.gazel.ipac, hscx * 0x40 + off2)); ReadHSCX() 216 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument 224 writereg(cs->hw.gazel.hscx[hscx], off2, value); WriteHSCX() 228 writereg_ipac(cs->hw.gazel.ipac, hscx * 0x40 + off2, value); WriteHSCX() 327 release_region(i + cs->hw.gazel.hscx[0], 16); release_io_gazel() 328 release_region(0xC000 + cs->hw.gazel.hscx[0], 1); release_io_gazel() 332 release_region(cs->hw.gazel.hscx[0], 0x100); release_io_gazel() 420 cs->bcs[i].hw.hscx.tsaxr0 = 0x1f; Gazel_card_msg() 421 cs->bcs[i].hw.hscx.tsaxr1 = 0x23; Gazel_card_msg() 439 base = cs->hw.gazel.hscx[0]; reserve_regions() 455 if (!request_region(adr = cs->hw.gazel.hscx[0], len = 0x100, "gazel")) reserve_regions() 458 release_region(cs->hw.gazel.hscx[0], 0x100); reserve_regions() 502 cs->hw.gazel.hscx[0] = card->para[1]; setup_gazelisa() 503 cs->hw.gazel.hscx[1] = card->para[1] + 0x4000; setup_gazelisa() 506 cs->hw.gazel.hscxfifo[0] = cs->hw.gazel.hscx[0]; setup_gazelisa() 507 cs->hw.gazel.hscxfifo[1] = cs->hw.gazel.hscx[1]; setup_gazelisa() 517 "Gazel: hscx A:0x%X hscx B:0x%X\n", setup_gazelisa() 518 cs->hw.gazel.hscx[0], cs->hw.gazel.hscx[1]); setup_gazelisa() 587 cs->hw.gazel.hscx[0] = pci_ioaddr1; setup_gazelpci() 588 cs->hw.gazel.hscx[1] = pci_ioaddr1 + 0x40; setup_gazelpci() 590 cs->hw.gazel.hscxfifo[0] = cs->hw.gazel.hscx[0]; setup_gazelpci() 591 cs->hw.gazel.hscxfifo[1] = cs->hw.gazel.hscx[1]; setup_gazelpci() 604 "Gazel: hscx A:0x%X hscx B:0x%X\n", setup_gazelpci() 605 cs->hw.gazel.hscx[0], cs->hw.gazel.hscx[1]); setup_gazelpci()
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H A D | niccy.c | 19 #include "hscx.h" 98 static u_char ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument 101 cs->hw.niccy.hscx, offset + (hscx ? 0x40 : 0)); ReadHSCX() 104 static void WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, WriteHSCX() argument 108 cs->hw.niccy.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX() 112 cs->hw.niccy.hscx, reg + (nr ? 0x40 : 0)) 114 cs->hw.niccy.hscx, reg + (nr ? 0x40 : 0), data) 117 cs->hw.niccy.hscx, (nr ? 0x40 : 0), ptr, cnt) 120 cs->hw.niccy.hscx, (nr ? 0x40 : 0), ptr, cnt) 140 val = readreg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, niccy_interrupt() 149 val = readreg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, niccy_interrupt() 162 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK, 0xFF); niccy_interrupt() 163 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK + 0x40, niccy_interrupt() 167 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK, 0); niccy_interrupt() 168 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK + 0x40, 0); niccy_interrupt() 279 cs->hw.niccy.hscx = card->para[1] + HSCX_PNP; setup_niccy() 337 cs->hw.niccy.hscx = pci_ioaddr + HSCX_PCI_DATA; setup_niccy()
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H A D | sportster.c | 18 #include "hscx.h" 78 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument 80 return (bytein(calc_off(cs->hw.spt.hscx[hscx], offset))); ReadHSCX() 84 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument 86 byteout(calc_off(cs->hw.spt.hscx[hscx], offset), value); WriteHSCX() 93 #define READHSCX(cs, nr, reg) bytein(calc_off(cs->hw.spt.hscx[nr], reg)) 94 #define WRITEHSCX(cs, nr, reg, data) byteout(calc_off(cs->hw.spt.hscx[nr], reg), data) 95 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.spt.hscx[nr], ptr, cnt) 96 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.spt.hscx[nr], ptr, cnt) 225 cs->hw.spt.hscx[0] = cs->hw.spt.cfg_reg + SPORTSTER_HSCXA; setup_sportster() 226 cs->hw.spt.hscx[1] = cs->hw.spt.cfg_reg + SPORTSTER_HSCXB; setup_sportster()
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H A D | telespci.c | 18 #include "hscx.h" 77 readhscx(void __iomem *adr, int hscx, u_char off) readhscx() argument 83 writel(WRITE_ADDR_HSCX | ((hscx ? 0x40 : 0) + off), adr + 0x200); readhscx() 93 writehscx(void __iomem *adr, int hscx, u_char off, u_char data) writehscx() argument 99 writel(WRITE_ADDR_HSCX | ((hscx ? 0x40 : 0) + off), adr + 0x200); writehscx() 143 read_fifo_hscx(void __iomem *adr, int hscx, u_char *data, int size) read_fifo_hscx() argument 152 writel(WRITE_ADDR_HSCX | (hscx ? 0x5F : 0x1F), adr + 0x200); read_fifo_hscx() 161 write_fifo_hscx(void __iomem *adr, int hscx, u_char *data, int size) write_fifo_hscx() argument 170 writel(WRITE_ADDR_HSCX | (hscx ? 0x5F : 0x1F), adr + 0x200); write_fifo_hscx() 205 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument 207 return (readhscx(cs->hw.teles0.membase, hscx, offset)); ReadHSCX() 211 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument 213 writehscx(cs->hw.teles0.membase, hscx, offset, value); WriteHSCX()
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H A D | asuscom.c | 20 #include "hscx.h" 126 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument 129 cs->hw.asus.hscx, offset + (hscx ? 0x40 : 0))); ReadHSCX() 133 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument 136 cs->hw.asus.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX() 144 cs->hw.asus.hscx, reg + (nr ? 0x40 : 0)) 146 cs->hw.asus.hscx, reg + (nr ? 0x40 : 0), data) 149 cs->hw.asus.hscx, (nr ? 0x40 : 0), ptr, cnt) 152 cs->hw.asus.hscx, (nr ? 0x40 : 0), ptr, cnt) 164 val = readreg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_ISTA + 0x40); asuscom_interrupt() 172 val = readreg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_ISTA + 0x40); asuscom_interrupt() 184 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK, 0xFF); asuscom_interrupt() 185 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK + 0x40, 0xFF); asuscom_interrupt() 188 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK, 0x0); asuscom_interrupt() 189 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK + 0x40, 0x0); asuscom_interrupt() 207 val = readreg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_ISTA + 0x40); asuscom_interrupt_ipac() 394 cs->hw.asus.hscx = cs->hw.asus.cfg_reg + ASUS_IPAC_DATA; setup_asuscom() 406 cs->hw.asus.hscx = cs->hw.asus.cfg_reg + ASUS_HSCX; setup_asuscom()
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H A D | teles0.c | 22 #include "hscx.h" 44 readhscx(void __iomem *adr, int hscx, u_char off) readhscx() argument 46 return readb(adr + (hscx ? 0x1c0 : 0x180) + readhscx() 51 writehscx(void __iomem *adr, int hscx, u_char off, u_char data) writehscx() argument 53 writeb(data, adr + (hscx ? 0x1c0 : 0x180) + writehscx() 77 read_fifo_hscx(void __iomem *adr, int hscx, u_char *data, int size) read_fifo_hscx() argument 80 register u_char __iomem *ad = adr + (hscx ? 0x1c0 : 0x180); read_fifo_hscx() 86 write_fifo_hscx(void __iomem *adr, int hscx, u_char *data, int size) write_fifo_hscx() argument 89 register u_char __iomem *ad = adr + (hscx ? 0x1c0 : 0x180); write_fifo_hscx() 122 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument 124 return (readhscx(cs->hw.teles0.membase, hscx, offset)); ReadHSCX() 128 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument 130 writehscx(cs->hw.teles0.membase, hscx, offset, value); WriteHSCX()
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H A D | avm_a1p.c | 19 #include "hscx.h" 95 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument 101 HSCX_REG_OFFSET + hscx * HSCX_CH_DIFF + offset); ReadHSCX() 107 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument 111 HSCX_REG_OFFSET + hscx * HSCX_CH_DIFF + offset); WriteHSCX() 116 ReadHSCXfifo(struct IsdnCardState *cs, int hscx, u_char *data, int size) ReadHSCXfifo() argument 119 HSCX_FIFO_OFFSET + hscx * HSCX_CH_DIFF); ReadHSCXfifo() 124 WriteHSCXfifo(struct IsdnCardState *cs, int hscx, u_char *data, int size) WriteHSCXfifo() argument 127 HSCX_FIFO_OFFSET + hscx * HSCX_CH_DIFF); WriteHSCXfifo()
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H A D | sedlbauer.c | 45 #include "hscx.h" 202 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument 205 cs->hw.sedl.hscx, offset + (hscx ? 0x40 : 0))); ReadHSCX() 209 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument 212 cs->hw.sedl.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX() 225 return (readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, offset)); ReadISAR() 228 return (bytein(cs->hw.sedl.hscx)); ReadISAR() 235 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, offset, value); WriteISAR() 239 byteout(cs->hw.sedl.hscx, value); WriteISAR() 248 cs->hw.sedl.hscx, reg + (nr ? 0x40 : 0)) 250 cs->hw.sedl.hscx, reg + (nr ? 0x40 : 0), data) 253 cs->hw.sedl.hscx, (nr ? 0x40 : 0), ptr, cnt) 256 cs->hw.sedl.hscx, (nr ? 0x40 : 0), ptr, cnt) 276 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_ISTA + 0x40); sedlbauer_interrupt() 284 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_ISTA + 0x40); sedlbauer_interrupt() 296 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK, 0xFF); sedlbauer_interrupt() 297 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK + 0x40, 0xFF); sedlbauer_interrupt() 300 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK, 0x0); sedlbauer_interrupt() 301 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK + 0x40, 0x0); sedlbauer_interrupt() 319 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_ISTA + 0x40); sedlbauer_interrupt_ipac() 362 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, ISAR_IRQBIT); sedlbauer_interrupt_isar() 370 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, ISAR_IRQBIT); sedlbauer_interrupt_isar() 386 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, ISAR_IRQBIT, 0); sedlbauer_interrupt_isar() 389 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, ISAR_IRQBIT, ISAR_IRQMSK); sedlbauer_interrupt_isar() 457 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, Sedl_card_msg() 462 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, Sedl_card_msg() 478 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, Sedl_card_msg() 782 cs->hw.sedl.hscx = cs->hw.sedl.cfg_reg + SEDL_IPAC_PCI_IPAC; setup_sedlbauer() 786 cs->hw.sedl.hscx = cs->hw.sedl.cfg_reg + SEDL_IPAC_ANY_IPAC; setup_sedlbauer() 808 cs->hw.sedl.hscx = cs->hw.sedl.cfg_reg + setup_sedlbauer() 815 cs->hw.sedl.hscx = cs->hw.sedl.cfg_reg + setup_sedlbauer() 850 cs->hw.sedl.hscx = cs->hw.sedl.cfg_reg + SEDL_HSCX_PCMCIA_HSCX; setup_sedlbauer() 857 cs->hw.sedl.hscx = cs->hw.sedl.cfg_reg + SEDL_HSCX_ISA_HSCX; setup_sedlbauer()
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H A D | hscx.h | 1 /* $Id: hscx.h,v 1.8.2.2 2004/01/12 22:52:26 keil Exp $
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H A D | bkm_a8.c | 18 #include "hscx.h" 103 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument 105 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0))); ReadHSCX() 109 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument 111 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value); WriteHSCX() 405 /* For isac and hscx data path */ setup_sct_quadro()
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H A D | elsa.c | 27 #include "hscx.h" 224 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument 227 cs->hw.elsa.hscx, offset + (hscx ? 0x40 : 0))); ReadHSCX() 231 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument 234 cs->hw.elsa.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX() 271 cs->hw.elsa.hscx, reg + (nr ? 0x40 : 0)) 273 cs->hw.elsa.hscx, reg + (nr ? 0x40 : 0), data) 276 cs->hw.elsa.hscx, (nr ? 0x40 : 0), ptr, cnt) 279 cs->hw.elsa.hscx, (nr ? 0x40 : 0), ptr, cnt) 307 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_ISTA + 0x40); elsa_interrupt() 317 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_ISTA + 0x40); elsa_interrupt() 333 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK, 0xFF); elsa_interrupt() 334 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK + 0x40, 0xFF); elsa_interrupt() 355 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK, 0x0); elsa_interrupt() 356 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK + 0x40, 0x0); elsa_interrupt() 392 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_ISTA + 0x40); elsa_interrupt_ipac() 866 cs->hw.elsa.hscx = cs->hw.elsa.base + ELSA_HSCX; setup_elsa_isa() 985 cs->hw.elsa.hscx = cs->hw.elsa.base + ELSA_HSCX; setup_elsa_isapnp() 1010 cs->hw.elsa.hscx = cs->hw.elsa.base + 2; setup_elsa_pcmcia() 1016 cs->hw.elsa.hscx = cs->hw.elsa.base + ELSA_HSCX; setup_elsa_pcmcia() 1074 cs->hw.elsa.hscx = cs->hw.elsa.base + 1; setup_elsa_pci()
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H A D | hisax.h | 365 int hscx; member in struct:hscx_hw 523 struct hscx_hw hscx; member in union:BCState::__anon5290 560 unsigned int hscx; member in struct:elsa_hw 584 signed int hscx[2]; member in struct:teles3_hw 598 unsigned int hscx[2]; member in struct:avm_hw 610 unsigned int hscx; member in struct:ix1_hw 620 unsigned int hscx; member in struct:diva_hw 631 unsigned int hscx; member in struct:asus_hw 651 unsigned int hscx; member in struct:sedl_hw 663 unsigned int hscx[2]; member in struct:spt_hw 671 unsigned int hscx; member in struct:mic_hw 772 unsigned int hscx; member in struct:saphir_hw 795 signed int hscx[2]; member in struct:gazel_hw
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H A D | elsa_ser.c | 291 bcs->ackcnt += bcs->hw.hscx.count; modem_fill() 300 bcs->hw.hscx.count = 0; modem_fill() 431 if (bcs->hw.hscx.rcvbuf) { close_elsastate() 433 kfree(bcs->hw.hscx.rcvbuf); close_elsastate() 434 bcs->hw.hscx.rcvbuf = NULL; close_elsastate() 561 bcs->hw.hscx.count = 0; modem_l2l1() 599 bcs->hw.hscx.rcvbuf = bcs->cs->hw.elsa.rcvbuf; setstack_elsa() 606 bcs->hw.hscx.rcvidx = 0; setstack_elsa()
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H A D | bkm_a4t.c | 17 #include "hscx.h"
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H A D | netjet.c | 20 #include "hscx.h"
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/linux-4.1.27/drivers/isdn/hardware/mISDN/ |
H A D | mISDNipac.c | 939 hscx_empty_fifo(struct hscx_hw *hscx, u8 count) hscx_empty_fifo() argument 944 pr_debug("%s: B%1d %d\n", hscx->ip->name, hscx->bch.nr, count); hscx_empty_fifo() 945 if (test_bit(FLG_RX_OFF, &hscx->bch.Flags)) { hscx_empty_fifo() 946 hscx->bch.dropcnt += count; hscx_empty_fifo() 947 hscx_cmdr(hscx, 0x80); /* RMC */ hscx_empty_fifo() 950 maxlen = bchannel_get_rxbuf(&hscx->bch, count); hscx_empty_fifo() 952 hscx_cmdr(hscx, 0x80); /* RMC */ hscx_empty_fifo() 953 if (hscx->bch.rx_skb) hscx_empty_fifo() 954 skb_trim(hscx->bch.rx_skb, 0); hscx_empty_fifo() 956 hscx->ip->name, hscx->bch.nr, count); hscx_empty_fifo() 959 p = skb_put(hscx->bch.rx_skb, count); hscx_empty_fifo() 961 if (hscx->ip->type & IPAC_TYPE_IPACX) hscx_empty_fifo() 962 hscx->ip->read_fifo(hscx->ip->hw, hscx_empty_fifo() 963 hscx->off + IPACX_RFIFOB, p, count); hscx_empty_fifo() 965 hscx->ip->read_fifo(hscx->ip->hw, hscx_empty_fifo() 966 hscx->off, p, count); hscx_empty_fifo() 968 hscx_cmdr(hscx, 0x80); /* RMC */ hscx_empty_fifo() 970 if (hscx->bch.debug & DEBUG_HW_BFIFO) { hscx_empty_fifo() 971 snprintf(hscx->log, 64, "B%1d-recv %s %d ", hscx_empty_fifo() 972 hscx->bch.nr, hscx->ip->name, count); hscx_empty_fifo() 973 print_hex_dump_bytes(hscx->log, DUMP_PREFIX_OFFSET, p, count); hscx_empty_fifo() 978 hscx_fill_fifo(struct hscx_hw *hscx) hscx_fill_fifo() argument 983 if (!hscx->bch.tx_skb) { hscx_fill_fifo() 984 if (!test_bit(FLG_TX_EMPTY, &hscx->bch.Flags)) hscx_fill_fifo() 986 count = hscx->fifo_size; hscx_fill_fifo() 988 p = hscx->log; hscx_fill_fifo() 989 memset(p, hscx->bch.fill[0], count); hscx_fill_fifo() 991 count = hscx->bch.tx_skb->len - hscx->bch.tx_idx; hscx_fill_fifo() 994 p = hscx->bch.tx_skb->data + hscx->bch.tx_idx; hscx_fill_fifo() 996 more = test_bit(FLG_TRANSPARENT, &hscx->bch.Flags) ? 1 : 0; hscx_fill_fifo() 997 if (count > hscx->fifo_size) { hscx_fill_fifo() 998 count = hscx->fifo_size; hscx_fill_fifo() 1001 pr_debug("%s: B%1d %d/%d/%d\n", hscx->ip->name, hscx->bch.nr, hscx_fill_fifo() 1002 count, hscx->bch.tx_idx, hscx->bch.tx_skb->len); hscx_fill_fifo() 1003 hscx->bch.tx_idx += count; hscx_fill_fifo() 1005 if (hscx->ip->type & IPAC_TYPE_IPACX) hscx_fill_fifo() 1006 hscx->ip->write_fifo(hscx->ip->hw, hscx_fill_fifo() 1007 hscx->off + IPACX_XFIFOB, p, count); hscx_fill_fifo() 1009 waitforXFW(hscx); hscx_fill_fifo() 1010 hscx->ip->write_fifo(hscx->ip->hw, hscx_fill_fifo() 1011 hscx->off, p, count); hscx_fill_fifo() 1013 hscx_cmdr(hscx, more ? 0x08 : 0x0a); hscx_fill_fifo() 1015 if (hscx->bch.tx_skb && (hscx->bch.debug & DEBUG_HW_BFIFO)) { hscx_fill_fifo() 1016 snprintf(hscx->log, 64, "B%1d-send %s %d ", hscx_fill_fifo() 1017 hscx->bch.nr, hscx->ip->name, count); hscx_fill_fifo() 1018 print_hex_dump_bytes(hscx->log, DUMP_PREFIX_OFFSET, p, count); hscx_fill_fifo() 1108 ipac_irq(&hx->ip->hscx[0], ista); ipac_irq() 1176 ipac_irq(&ipac->hscx[0], ista); mISDNipac_irq() 1178 ipac_irq(&ipac->hscx[1], ista); mISDNipac_irq() 1197 ipac_irq(&ipac->hscx[0], ista); mISDNipac_irq() 1199 ipac_irq(&ipac->hscx[1], ista); mISDNipac_irq() 1204 ista = ReadIPAC(ipac, IPAC_ISTAB + ipac->hscx[1].off); mISDNipac_irq() 1207 ipac_irq(&ipac->hscx[1], ista); mISDNipac_irq() 1230 hscx_mode(struct hscx_hw *hscx, u32 bprotocol) hscx_mode() argument 1232 pr_debug("%s: HSCX %c protocol %x-->%x ch %d\n", hscx->ip->name, hscx_mode() 1233 '@' + hscx->bch.nr, hscx->bch.state, bprotocol, hscx->bch.nr); hscx_mode() 1234 if (hscx->ip->type & IPAC_TYPE_IPACX) { hscx_mode() 1235 if (hscx->bch.nr & 1) { /* B1 and ICA */ hscx_mode() 1236 WriteIPAC(hscx->ip, ISACX_BCHA_TSDP_BC1, 0x80); hscx_mode() 1237 WriteIPAC(hscx->ip, ISACX_BCHA_CR, 0x88); hscx_mode() 1239 WriteIPAC(hscx->ip, ISACX_BCHB_TSDP_BC1, 0x81); hscx_mode() 1240 WriteIPAC(hscx->ip, ISACX_BCHB_CR, 0x88); hscx_mode() 1244 WriteHSCX(hscx, IPACX_MODEB, 0xC0); /* rec off */ hscx_mode() 1245 WriteHSCX(hscx, IPACX_EXMB, 0x30); /* std adj. */ hscx_mode() 1246 WriteHSCX(hscx, IPACX_MASKB, 0xFF); /* ints off */ hscx_mode() 1247 hscx_cmdr(hscx, 0x41); hscx_mode() 1248 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags); hscx_mode() 1249 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags); hscx_mode() 1252 WriteHSCX(hscx, IPACX_MODEB, 0x88); /* ex trans */ hscx_mode() 1253 WriteHSCX(hscx, IPACX_EXMB, 0x00); /* trans */ hscx_mode() 1254 hscx_cmdr(hscx, 0x41); hscx_mode() 1255 WriteHSCX(hscx, IPACX_MASKB, IPACX_B_ON); hscx_mode() 1256 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags); hscx_mode() 1259 WriteHSCX(hscx, IPACX_MODEB, 0xC0); /* trans */ hscx_mode() 1260 WriteHSCX(hscx, IPACX_EXMB, 0x00); /* hdlc,crc */ hscx_mode() 1261 hscx_cmdr(hscx, 0x41); hscx_mode() 1262 WriteHSCX(hscx, IPACX_MASKB, IPACX_B_ON); hscx_mode() 1263 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags); hscx_mode() 1266 pr_info("%s: protocol not known %x\n", hscx->ip->name, hscx_mode() 1270 } else if (hscx->ip->type & IPAC_TYPE_IPAC) { /* IPAC */ hscx_mode() 1271 WriteHSCX(hscx, IPAC_CCR1, 0x82); hscx_mode() 1272 WriteHSCX(hscx, IPAC_CCR2, 0x30); hscx_mode() 1273 WriteHSCX(hscx, IPAC_XCCR, 0x07); hscx_mode() 1274 WriteHSCX(hscx, IPAC_RCCR, 0x07); hscx_mode() 1275 WriteHSCX(hscx, IPAC_TSAX, hscx->slot); hscx_mode() 1276 WriteHSCX(hscx, IPAC_TSAR, hscx->slot); hscx_mode() 1279 WriteHSCX(hscx, IPAC_TSAX, 0x1F); hscx_mode() 1280 WriteHSCX(hscx, IPAC_TSAR, 0x1F); hscx_mode() 1281 WriteHSCX(hscx, IPAC_MODEB, 0x84); hscx_mode() 1282 WriteHSCX(hscx, IPAC_CCR1, 0x82); hscx_mode() 1283 WriteHSCX(hscx, IPAC_MASKB, 0xFF); /* ints off */ hscx_mode() 1284 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags); hscx_mode() 1285 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags); hscx_mode() 1288 WriteHSCX(hscx, IPAC_MODEB, 0xe4); /* ex trans */ hscx_mode() 1289 WriteHSCX(hscx, IPAC_CCR1, 0x82); hscx_mode() 1290 hscx_cmdr(hscx, 0x41); hscx_mode() 1291 WriteHSCX(hscx, IPAC_MASKB, 0); hscx_mode() 1292 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags); hscx_mode() 1295 WriteHSCX(hscx, IPAC_MODEB, 0x8c); hscx_mode() 1296 WriteHSCX(hscx, IPAC_CCR1, 0x8a); hscx_mode() 1297 hscx_cmdr(hscx, 0x41); hscx_mode() 1298 WriteHSCX(hscx, IPAC_MASKB, 0); hscx_mode() 1299 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags); hscx_mode() 1302 pr_info("%s: protocol not known %x\n", hscx->ip->name, hscx_mode() 1306 } else if (hscx->ip->type & IPAC_TYPE_HSCX) { /* HSCX */ hscx_mode() 1307 WriteHSCX(hscx, IPAC_CCR1, 0x85); hscx_mode() 1308 WriteHSCX(hscx, IPAC_CCR2, 0x30); hscx_mode() 1309 WriteHSCX(hscx, IPAC_XCCR, 0x07); hscx_mode() 1310 WriteHSCX(hscx, IPAC_RCCR, 0x07); hscx_mode() 1311 WriteHSCX(hscx, IPAC_TSAX, hscx->slot); hscx_mode() 1312 WriteHSCX(hscx, IPAC_TSAR, hscx->slot); hscx_mode() 1315 WriteHSCX(hscx, IPAC_TSAX, 0x1F); hscx_mode() 1316 WriteHSCX(hscx, IPAC_TSAR, 0x1F); hscx_mode() 1317 WriteHSCX(hscx, IPAC_MODEB, 0x84); hscx_mode() 1318 WriteHSCX(hscx, IPAC_CCR1, 0x85); hscx_mode() 1319 WriteHSCX(hscx, IPAC_MASKB, 0xFF); /* ints off */ hscx_mode() 1320 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags); hscx_mode() 1321 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags); hscx_mode() 1324 WriteHSCX(hscx, IPAC_MODEB, 0xe4); /* ex trans */ hscx_mode() 1325 WriteHSCX(hscx, IPAC_CCR1, 0x85); hscx_mode() 1326 hscx_cmdr(hscx, 0x41); hscx_mode() 1327 WriteHSCX(hscx, IPAC_MASKB, 0); hscx_mode() 1328 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags); hscx_mode() 1331 WriteHSCX(hscx, IPAC_MODEB, 0x8c); hscx_mode() 1332 WriteHSCX(hscx, IPAC_CCR1, 0x8d); hscx_mode() 1333 hscx_cmdr(hscx, 0x41); hscx_mode() 1334 WriteHSCX(hscx, IPAC_MASKB, 0); hscx_mode() 1335 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags); hscx_mode() 1338 pr_info("%s: protocol not known %x\n", hscx->ip->name, hscx_mode() 1344 hscx->bch.state = bprotocol; hscx_mode() 1476 hscx_init(&ipac->hscx[0]); ipac_init() 1477 hscx_init(&ipac->hscx[1]); ipac_init() 1480 hscx_init(&ipac->hscx[0]); ipac_init() 1481 hscx_init(&ipac->hscx[1]); ipac_init() 1489 if (ipac->hscx[0].bch.debug & DEBUG_HW) ipac_init() 1505 bch = &ipac->hscx[rq->adr.channel - 1].bch; open_bchannel() 1591 ipac->hscx[0].off = 0; mISDNipac_init() 1592 ipac->hscx[1].off = 0x40; mISDNipac_init() 1593 ipac->hscx[0].fifo_size = 32; mISDNipac_init() 1594 ipac->hscx[1].fifo_size = 32; mISDNipac_init() 1597 ipac->hscx[0].off = 0; mISDNipac_init() 1598 ipac->hscx[1].off = 0x40; mISDNipac_init() 1599 ipac->hscx[0].fifo_size = 64; mISDNipac_init() 1600 ipac->hscx[1].fifo_size = 64; mISDNipac_init() 1603 ipac->hscx[0].off = IPACX_OFF_ICA; mISDNipac_init() 1604 ipac->hscx[1].off = IPACX_OFF_ICB; mISDNipac_init() 1605 ipac->hscx[0].fifo_size = 64; mISDNipac_init() 1606 ipac->hscx[1].fifo_size = 64; mISDNipac_init() 1615 ipac->hscx[i].bch.nr = i + 1; mISDNipac_init() 1617 list_add(&ipac->hscx[i].bch.ch.list, mISDNipac_init() 1619 mISDN_initbchannel(&ipac->hscx[i].bch, MAX_DATA_MEM, mISDNipac_init() 1620 ipac->hscx[i].fifo_size); mISDNipac_init() 1621 ipac->hscx[i].bch.ch.nr = i + 1; mISDNipac_init() 1622 ipac->hscx[i].bch.ch.send = &hscx_l2l1; mISDNipac_init() 1623 ipac->hscx[i].bch.ch.ctrl = hscx_bctrl; mISDNipac_init() 1624 ipac->hscx[i].bch.hw = hw; mISDNipac_init() 1625 ipac->hscx[i].ip = ipac; mISDNipac_init() 1628 ipac->hscx[i].slot = (i == 0) ? 0x2f : 0x03; mISDNipac_init()
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H A D | mISDNinfineon.c | 117 struct _ioaddr hscx; member in struct:inf_hw 242 card->ipac.hscx[0].bch.debug = debug; _set_debug() 243 card->ipac.hscx[1].bch.debug = debug; _set_debug() 273 IOFUNC_IO(IPAC, inf_hw, hscx.a.io) 275 IOFUNC_IND(IPAC, inf_hw, hscx.a.io) 277 IOFUNC_MEMIO(IPAC, inf_hw, u32, hscx.a.p) 566 hw->ipac.hscx[0].slot = 0x1f; reset_inf() 567 hw->ipac.hscx[1].slot = 0x23; reset_inf() 732 hw->hscx.mode = hw->cfg.mode; setup_io() 733 hw->hscx.a.io.ale = (u32)hw->cfg.start + DIVA_HSCX_ALE; setup_io() 734 hw->hscx.a.io.port = (u32)hw->cfg.start + DIVA_HSCX_PORT; setup_io() 741 hw->hscx.mode = hw->addr.mode; setup_io() 742 hw->hscx.a.p = hw->addr.p; setup_io() 748 hw->hscx.mode = hw->addr.mode; setup_io() 749 hw->hscx.a.p = hw->addr.p; setup_io() 758 hw->hscx.mode = hw->cfg.mode; setup_io() 759 hw->hscx.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE; setup_io() 760 hw->hscx.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT; setup_io() 774 hw->hscx.a.io.ale = (u32)hw->addr.start; setup_io() 775 hw->hscx.a.io.port = (u32)hw->addr.start + 1; setup_io() 776 hw->hscx.mode = hw->addr.mode; setup_io() 783 hw->hscx.mode = hw->addr.mode; setup_io() 784 hw->hscx.a.io.ale = (u32)hw->addr.start + NICCY_HSCX_ALE; setup_io() 785 hw->hscx.a.io.port = (u32)hw->addr.start + NICCY_HSCX_PORT; setup_io() 793 hw->hscx.a.io.ale = hw->isac.a.io.ale; setup_io() 794 hw->hscx.a.io.port = hw->isac.a.io.port; setup_io() 795 hw->hscx.mode = hw->addr.mode; setup_io() 803 hw->hscx.a.io.ale = hw->isac.a.io.ale; setup_io() 804 hw->hscx.a.io.port = hw->isac.a.io.port; setup_io() 805 hw->hscx.mode = hw->addr.mode; setup_io() 813 hw->hscx.a.io.ale = hw->isac.a.io.ale; setup_io() 814 hw->hscx.a.io.port = hw->isac.a.io.port; setup_io() 815 hw->hscx.mode = hw->addr.mode; setup_io() 823 hw->hscx.a.io.ale = hw->isac.a.io.ale; setup_io() 824 hw->hscx.a.io.port = hw->isac.a.io.port; setup_io() 825 hw->hscx.mode = hw->addr.mode; setup_io() 832 hw->hscx.mode = hw->addr.mode; setup_io() 833 hw->hscx.a.io.port = hw->isac.a.io.port; setup_io() 841 hw->hscx.mode = hw->addr.mode; setup_io() 842 hw->hscx.a.io.ale = hw->isac.a.io.ale; setup_io() 843 hw->hscx.a.io.port = hw->isac.a.io.port; setup_io()
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H A D | ipac.h | 70 struct hscx_hw hscx[2]; member in struct:ipac_hw
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