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Searched refs:hccr (Results 1 – 10 of 10) sorted by relevance

/linux-4.1.27/drivers/scsi/qla2xxx/
Dqla_dbg.c149 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT); in qla27xx_dump_mpi_ram()
166 WRT_REG_DWORD(&reg->hccr, in qla27xx_dump_mpi_ram()
168 RD_REG_DWORD(&reg->hccr); in qla27xx_dump_mpi_ram()
173 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT); in qla27xx_dump_mpi_ram()
174 RD_REG_DWORD(&reg->hccr); in qla27xx_dump_mpi_ram()
227 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT); in qla24xx_dump_ram()
243 WRT_REG_DWORD(&reg->hccr, in qla24xx_dump_ram()
245 RD_REG_DWORD(&reg->hccr); in qla24xx_dump_ram()
250 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT); in qla24xx_dump_ram()
251 RD_REG_DWORD(&reg->hccr); in qla24xx_dump_ram()
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Dqla_isr.c39 uint16_t hccr; in qla2100_intr_handler() local
58 hccr = RD_REG_WORD(&reg->hccr); in qla2100_intr_handler()
59 if (qla2x00_check_reg16_for_disconnect(vha, hccr)) in qla2100_intr_handler()
61 if (hccr & HCCR_RISC_PAUSE) { in qla2100_intr_handler()
70 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC); in qla2100_intr_handler()
71 RD_REG_WORD(&reg->hccr); in qla2100_intr_handler()
80 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT); in qla2100_intr_handler()
81 RD_REG_WORD(&reg->hccr); in qla2100_intr_handler()
105 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT); in qla2100_intr_handler()
106 RD_REG_WORD(&reg->hccr); in qla2100_intr_handler()
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Dqla_init.c806 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC); in qla2300_pci_config()
808 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0) in qla2300_pci_config()
829 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC); in qla2300_pci_config()
831 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0) in qla2300_pci_config()
993 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC); in qla2x00_reset_chip()
996 if ((RD_REG_WORD(&reg->hccr) & in qla2x00_reset_chip()
1002 RD_REG_WORD(&reg->hccr); /* PCI Posting. */ in qla2x00_reset_chip()
1044 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC); in qla2x00_reset_chip()
1045 RD_REG_WORD(&reg->hccr); /* PCI Posting. */ in qla2x00_reset_chip()
1048 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC); in qla2x00_reset_chip()
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Dqla_dbg.h15 uint16_t hccr; member
39 uint16_t hccr; member
Dqla_mbx.c169 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT); in qla2x00_mailbox_command()
171 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT); in qla2x00_mailbox_command()
199 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT); in qla2x00_mailbox_command()
201 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT); in qla2x00_mailbox_command()
4640 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT); in qla81xx_write_mpi_register()
4654 WRT_REG_DWORD(&reg->hccr, in qla81xx_write_mpi_register()
4656 RD_REG_DWORD(&reg->hccr); in qla81xx_write_mpi_register()
Dqla_sup.c2255 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC); in qla2x00_suspend_hba()
2256 RD_REG_WORD(&reg->hccr); in qla2x00_suspend_hba()
2259 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0) in qla2x00_suspend_hba()
Dqla_iocb.c473 RD_REG_DWORD_RELAXED(&ha->iobase->isp24.hccr); in qla2x00_start_iocbs()
1569 RD_REG_DWORD_RELAXED(&ha->iobase->isp24.hccr); in qla24xx_start_scsi()
1769 RD_REG_DWORD_RELAXED(&ha->iobase->isp24.hccr); in qla24xx_dif_start_scsi()
Dqla_fw.h1003 uint32_t hccr; /* Host command & control register. */ member
Dqla_def.h538 uint16_t hccr; /* Host command & control register. */ member
Dqla_os.c5444 stat = RD_REG_DWORD(&reg->hccr); in qla2xxx_pci_mmio_enabled()