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Searched refs:gpu_offset (Results 1 – 17 of 17) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
Devergreen_cs.c1169 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1241 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1253 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1265 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1277 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1301 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1321 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1524 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1541 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1582 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
[all …]
Dr600_cs.c1023 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1085 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1087 track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset; in r600_cs_check_reg()
1106 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1215 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1246 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1282 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1285 track->cb_color_bo_mc[tmp] = reloc->gpu_offset; in r600_cs_check_reg()
1296 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1298 track->db_bo_mc = reloc->gpu_offset; in r600_cs_check_reg()
[all …]
Dr200.c191 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
204 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
228 ib[idx] = tmp + ((u32)reloc->gpu_offset); in r200_packet0_check()
230 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
274 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
368 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
Dr300.c651 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
664 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
693 ((idx_value & ~31) + (u32)reloc->gpu_offset); in r300_packet0_check()
702 tmp = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
1063 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
1108 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
1173 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r300_packet3_check()
Dr100.c1280 tmp += (((u32)reloc->gpu_offset) >> 10); in r100_reloc_pitch_offset()
1331 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1343 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1357 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1598 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1611 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1632 ib[idx] = tmp + ((u32)reloc->gpu_offset); in r100_packet0_check()
1634 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1652 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1670 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
[all …]
Dradeon_object.c574 lobj->gpu_offset = radeon_bo_gpu_offset(bo); in radeon_bo_list_validate()
579 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj); in radeon_bo_list_validate()
Dradeon_cs.c858 (*cs_reloc)->gpu_offset = in radeon_cs_packet_next_reloc()
860 (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0]; in radeon_cs_packet_next_reloc()
Dradeon_ttm.c143 man->gpu_offset = rdev->mc.gtt_start; in radeon_init_mem_type()
165 man->gpu_offset = rdev->mc.vram_start; in radeon_init_mem_type()
Dradeon_vce.c471 start = reloc->gpu_offset; in radeon_vce_cs_reloc()
Dradeon_uvd.c548 start = reloc->gpu_offset; in radeon_uvd_cs_reloc()
Dradeon.h460 uint64_t gpu_offset; member
/linux-4.1.27/drivers/gpu/drm/vmwgfx/
Dvmwgfx_buffer.c728 man->gpu_offset = 0; in vmw_init_mem_type()
741 man->gpu_offset = 0; in vmw_init_mem_type()
/linux-4.1.27/include/drm/ttm/
Dttm_bo_driver.h280 uint64_t gpu_offset; /* GPU address space is independent of CPU word size */ member
/linux-4.1.27/drivers/gpu/drm/i915/
Di915_gem.c446 const char *gpu_vaddr, int gpu_offset, in __copy_to_user_swizzled() argument
452 int cacheline_end = ALIGN(gpu_offset + 1, 64); in __copy_to_user_swizzled()
453 int this_length = min(cacheline_end - gpu_offset, length); in __copy_to_user_swizzled()
454 int swizzled_gpu_offset = gpu_offset ^ 64; in __copy_to_user_swizzled()
463 gpu_offset += this_length; in __copy_to_user_swizzled()
471 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, in __copy_from_user_swizzled() argument
478 int cacheline_end = ALIGN(gpu_offset + 1, 64); in __copy_from_user_swizzled()
479 int this_length = min(cacheline_end - gpu_offset, length); in __copy_from_user_swizzled()
480 int swizzled_gpu_offset = gpu_offset ^ 64; in __copy_from_user_swizzled()
489 gpu_offset += this_length; in __copy_from_user_swizzled()
/linux-4.1.27/drivers/gpu/drm/qxl/
Dqxl_ttm.c174 man->gpu_offset = 0; in qxl_init_mem_type()
Dqxl_cmd.c520 …_create.data |= (new_mem->start << PAGE_SHIFT) + surf->tbo.bdev->man[new_mem->mem_type].gpu_offset; in qxl_hw_surface_alloc()
/linux-4.1.27/drivers/gpu/drm/ttm/
Dttm_bo.c77 pr_err(" gpu_offset: 0x%08llX\n", man->gpu_offset); in ttm_mem_type_debug()
365 bdev->man[bo->mem.mem_type].gpu_offset; in ttm_bo_handle_move_mem()