Searched refs:gated (Results 1 - 97 of 97) sorted by relevance

/linux-4.1.27/drivers/cpuidle/
H A Dcpuidle-cps.c22 STATE_CLOCK_GATED, /* Core clock gated */
23 STATE_POWER_GATED, /* Core power gated */
90 .name = "clock-gated",
91 .desc = "core clock gated",
98 .name = "power-gated",
99 .desc = "core power gated",
/linux-4.1.27/arch/mips/include/asm/
H A Dpm-cps.h28 CPS_PM_CLOCK_GATED, /* Core clock gated */
29 CPS_PM_POWER_GATED, /* Core power gated */
/linux-4.1.27/drivers/gpu/drm/radeon/
H A Dvce_v2_0.c34 static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated) vce_v2_0_set_sw_cg() argument
38 if (gated) { vce_v2_0_set_sw_cg()
69 static void vce_v2_0_set_dyn_cg(struct radeon_device *rdev, bool gated) vce_v2_0_set_dyn_cg() argument
75 if (gated) { vce_v2_0_set_dyn_cg()
94 if (gated) vce_v2_0_set_dyn_cg()
/linux-4.1.27/include/linux/pinctrl/
H A Dpinctrl-state.h14 * but not fully sleeping - some power may be on but clocks gated for
/linux-4.1.27/arch/arm/mach-s3c64xx/
H A Dcpuidle.c52 .desc = "System active, ARM gated",
/linux-4.1.27/sound/pci/hda/
H A Dhda_jack.c168 /* If a jack is gated by this one update it. */ jack_detect_update()
170 struct hda_jack_tbl *gated = jack_detect_update() local
172 if (gated) { jack_detect_update()
173 gated->jack_dirty = 1; jack_detect_update()
174 jack_detect_update(codec, gated); jack_detect_update()
298 * @gated_nid: gated pin NID
301 * Indicates the gated jack is only valid when the gating jack is plugged.
306 struct hda_jack_tbl *gated = snd_hda_jack_tbl_new(codec, gated_nid); snd_hda_jack_set_gating_jack() local
309 if (!gated || !gating) snd_hda_jack_set_gating_jack()
312 gated->gating_jack = gating_nid; snd_hda_jack_set_gating_jack()
573 struct hda_jack_tbl *gated = call_jack_callback() local
575 if (gated) { call_jack_callback()
576 for (cb = gated->callback; cb; cb = cb->next) call_jack_callback()
H A Dhda_jack.h41 hda_nid_t gated_jack; /* gated is dependent on this jack */
/linux-4.1.27/arch/arm/mach-tegra/
H A Dplatsmp.c53 * power-gated via the flow controller). This will have no tegra20_boot_secondary()
106 * The power status of the cold boot CPU is power gated as tegra30_boot_secondary()
108 * be un-gated by un-toggling the power gate register tegra30_boot_secondary()
H A Dcpuidle-tegra114.c79 .desc = "CPU power gated",
H A Dcpuidle-tegra30.c59 .desc = "CPU power gated",
H A Dcpuidle-tegra20.c64 .desc = "CPU power gated",
H A Dsleep-tegra30.S49 #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
220 wfeeq @ CPU should be power gated here
696 wfi /* CPU should be power gated here */
H A Dreset-handler.S265 wfi @ CPU should be power gated here
H A Dsleep-tegra20.S485 wfe /* CPU should be power gated here */
/linux-4.1.27/arch/arm/mach-omap2/
H A Dclkt2xxx_dpll.c28 * stop when its downstream clocks are gated. No return value.
H A Dmcbsp.c32 * Sidetone needs non-gated ICLK and sidetone autoidle is broken.
H A Dserial.c208 pr_info("%s used as console in debug mode: uart%d clocks will not be gated", omap_serial_early_init()
H A Ddpll3xxx.c648 * clocks are gated. No return value.
H A Domap_hwmod_44xx_data.c1779 * is in used otherwise vital clocks will be gated which
/linux-4.1.27/drivers/mmc/host/
H A Dtoshsd.h26 #define SD_PCICFG_EXTGATECLK1 0xf0 /* Could be used for gated clock */
27 #define SD_PCICFG_EXTGATECLK2 0xf1 /* Could be used for gated clock */
/linux-4.1.27/drivers/clk/
H A Dclk-gpio-gate.c9 * Gpio gated clock implementation
22 * DOC: basic gpio gated clock which can be enabled and disabled
H A Dclk-gate.c140 pr_err("%s: could not allocate gated clk\n", __func__); clk_register_gate()
H A Dclk-mb86s7x.c44 int gated; member in struct:hack_rate
H A Dclk-nomadik.c293 * The Nomadik SRC clocks are gated, but not in the sense that
H A Dclk-vt8500.c257 pr_err("%s: enable-bit property required for gated clock\n", vtwm_device_clk_init()
H A Dclk.c1037 * @clk: the clk being gated
1676 /* some clocks must be gated to change parent */ clk_calc_new_rates()
1679 pr_debug("%s: %s not gated but wants to reparent\n", clk_calc_new_rates()
/linux-4.1.27/drivers/media/dvb-frontends/
H A Dlgs8gxx.h54 /* transport stream clock gated by ts_valid */
H A Dlgs8gxx_priv.h66 #define TS_CLK_GATED 0x00 /* MPEG clock gated */
H A Ddib3000mc.c169 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock dib3000mc_set_output_mode()
H A Ddib7000m.c160 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock dib7000m_set_output_mode()
H A Ddib8000.c415 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock dib8000_set_output_mode()
/linux-4.1.27/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-socfpga.c240 * This causes the phy clock to be gated. The enet controller is socfpga_dwmac_init()
241 * resumed before the phy, so the clock is still gated "off" when socfpga_dwmac_init()
249 * Note that the phy clock is also gated when the phy is isolated. socfpga_dwmac_init()
/linux-4.1.27/drivers/clk/hisilicon/
H A Dclkgate-separated.c111 pr_err("%s: fail to allocate separated gated clk\n", __func__); hisi_register_clkgate_sep()
/linux-4.1.27/drivers/clk/qcom/
H A Dclk-branch.c80 /* Skip checking halt bit if the clock is in hardware gated mode */ clk_branch_wait()
/linux-4.1.27/include/sound/
H A Dsoc-dai.h44 * DAI bit clocks can be be gated (disabled) when the DAI is not
48 #define SND_SOC_DAIFMT_GATED (0 << 4) /* clock is gated */
/linux-4.1.27/arch/arm/mach-lpc32xx/
H A Dpm.c34 * SYSCLK is gated off and the CPU and system clocks are halted.
/linux-4.1.27/arch/arm/mach-mvebu/
H A Dkirkwood.c107 /* ensure port clock is not gated to not hang CPU */ kirkwood_dt_eth_fixup()
/linux-4.1.27/drivers/video/fbdev/
H A Dpxa168fb.h278 #define CFG_GATED_ENA(gated) ((gated) << 21)
H A Dpxa168fb.c334 * Configure default bits: vsync triggers DMA, gated clock set_dma_control1()
/linux-4.1.27/arch/arm/include/asm/
H A Dmcpm.h44 * should be gated. A gated CPU is held in a WFE loop until its vector
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8188ee/
H A Dpwrseq.h213 /*CCK and OFDM are disabled,and clock are gated*/}, \
/linux-4.1.27/drivers/staging/rtl8723au/include/
H A DHal8723PwrSeq.h94 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},/*CCK and OFDM are disabled, and clock are gated*/ \
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8723ae/
H A Dpwrseq.h227 /*CCK and OFDM are disabled,and clock are gated*/ \
/linux-4.1.27/drivers/clk/sunxi/
H A Dclk-factors.c200 /* Add a gate if this factor clock can be gated */ sunxi_factors_register()
H A Dclk-sunxi.c1175 /* If this leaf clock can be gated, create a gate */ sunxi_divs_clk_setup()
/linux-4.1.27/drivers/mmc/core/
H A Dhost.c134 pr_debug("%s: gated MCI clock\n", mmc_hostname(host)); mmc_host_clk_gate_delayed()
179 * mmc_host_may_gate_card - check if this card may be gated
H A Dcore.c1062 * We should previously have gated the clock, so the clock shall mmc_ungate_clock()
1080 * We've been given a new frequency while the clock is gated, mmc_set_ungated()
1540 * During a signal voltage level switch, the clock must be gated mmc_set_signal_voltage()
1556 /* Keep clock gated for at least 5 ms */ mmc_set_signal_voltage()
/linux-4.1.27/drivers/misc/mei/
H A Dmei_dev.h417 * @MEI_PG_OFF: device is not power gated - it is active
418 * @MEI_PG_ON: device is power gated - it is in lower power state
/linux-4.1.27/drivers/scsi/
H A Dg_NCR5380.c578 printk("53C400r: no 53C80 gated irq after transfer"); NCR5380_pread()
679 printk(KERN_ERR "53C400w: no 53C80 gated irq after transfer (last block)\n"); NCR5380_pwrite()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8821ae/
H A Dpwrseq.h270 /*CCK and OFDM are disabled,and clock are gated,and RF closed*/}, \
624 /*CCK and OFDM are disabled,and clock are gated*/}, \
/linux-4.1.27/drivers/clk/bcm/
H A Dclk-kona.h115 * of auto-gated clocks can be read from the gate status bit.
139 * HW means this gate can be auto-gated
H A Dclk-kona.c354 /* Determine whether a clock is gated. CCU lock must be held. */
371 /* Determine whether a clock is gated. */
/linux-4.1.27/arch/arm/mach-davinci/
H A Ddm355.c133 /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
165 /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192ee/
H A Dpwrseq.h229 /*CCK and OFDM are disabled,and clock are gated*/ \
/linux-4.1.27/drivers/staging/rtl8188eu/include/
H A Dpwrseq.h255 /*CCK and OFDM are disabled,and clock are gated*/ \
/linux-4.1.27/arch/mips/kernel/
H A Dsmp-cps.c411 * Wait for the core to enter a powered down or clock gated cps_cpu_die()
/linux-4.1.27/sound/soc/intel/common/
H A Dsst-dsp-priv.h233 * power gated.
/linux-4.1.27/include/linux/
H A Dclk-provider.h25 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
26 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
528 * struct clk_gpio_gate - gpio gated clock
/linux-4.1.27/drivers/media/i2c/
H A Dsaa711x_regs.h384 "I port I/O enable output clock and gated"},
/linux-4.1.27/drivers/net/phy/
H A Dmdio_bus.c449 * MDIO bus driver and clock gated at this point. mdio_bus_phy_may_suspend()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8723be/
H A Dpwrseq.h312 /*CCK and OFDM are disabled,and clock are gated*/ \
/linux-4.1.27/drivers/clk/zynq/
H A Dclkc.c514 /* One gated clock for all APER clocks. */ zynq_clk_setup()
/linux-4.1.27/drivers/gpu/ipu-v3/
H A Dipu-csi.c350 * MIPI CSI-2 requires non gated clock mode, all other fill_csi_bus_cfg()
/linux-4.1.27/arch/arm/plat-orion/
H A Dcommon.c39 Kirkwood has gated clocks for some of its peripherals, so creates
/linux-4.1.27/include/linux/mmc/
H A Dhost.h294 bool clk_gated; /* clock gated */
/linux-4.1.27/drivers/media/platform/soc_camera/
H A Dmx3_camera.c472 /* We use only gated clock synchronisation mode so far */ mx3_camera_activate()
1073 * So far only gated clock mode is supported. Add a line mx3_camera_set_bus_param()
/linux-4.1.27/drivers/staging/comedi/drivers/
H A Damplc_pci224.c814 /* Make sure Z2-0 is gated on. */ pci224_ao_start_pacer()
817 /* Make sure Z2-2 is gated on. */ pci224_ao_start_pacer()
H A Dcb_pcidas.c51 start_arg == 0 => gated trigger (level high)
52 start_arg == CR_INVERT => gated trigger (level low)
H A Damplc_pci230.c1926 * Conversion timer CT2 needs to be gated by pci230_ai_start()
1932 * Conversion timer CT2 needs to be gated on pci230_ai_start()
1975 * gated on to start counting. pci230_ai_start()
H A Ds626.c462 * still gated and we have not finished transmitting the stream. s626_send_dac()
/linux-4.1.27/arch/arm/mach-exynos/
H A Dpmu.c845 * bridge are gated. Thus, when ISP power is gated, LPI exynos5420_pmu_init()
/linux-4.1.27/drivers/usb/gadget/udc/
H A Dat91_udc.c54 * (and the transceiver) to stay gated off until they're necessary, saving
55 * power. During USB suspend, the 48 MHz clock is gated off in hardware;
56 * it may also be gated off by software during some Linux sleep states.
/linux-4.1.27/drivers/net/wireless/ath/ath5k/
H A Dreg.h78 #define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (Disable dynamic clock) */
622 #define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated */
623 #define AR5K_QCU_MISC_FRSHED_TIM_GT 3 /* TIMT gated */
624 #define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /* Beacon sent gated */
/linux-4.1.27/drivers/scsi/ufs/
H A Dufshcd.h487 /* Returns true if clocks can be gated. Otherwise false */ ufshcd_is_clkgating_allowed()
H A Dufshcd.c556 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
/linux-4.1.27/drivers/soc/tegra/
H A Dpmc.c44 #define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */
/linux-4.1.27/drivers/staging/media/cxd2099/
H A Dcxd2099.c338 /* TOSTRT = 8, Mode B (gated clock), falling Edge, init()
/linux-4.1.27/arch/powerpc/perf/
H A Dpower8-pmu.c31 /* All L1 D cache load references counted at finish, gated by reject */
H A Dcore-book3s.c638 * The logic is the same for EBB, except that the exception is gated by pmao_restore_workaround()
/linux-4.1.27/arch/arm/common/
H A DbL_switcher.c188 * to come online, but leave it gated in our entry vector code. bL_switch_to()
/linux-4.1.27/net/ipv4/
H A Dip_gre.c107 all that we could make. Even if it is your gated who injected
H A Ddevinet.c393 netlink listeners. It is not true: look, gated sees __inet_del_ifa()
/linux-4.1.27/drivers/net/ethernet/altera/
H A Daltera_tse_main.c1132 /* Note that reset_mac will fail if the clocks are gated by the PHY tse_open()
1241 /* Note that reset_mac will fail if the clocks are gated by the PHY tse_shutdown()
/linux-4.1.27/drivers/gpio/
H A Dgpio-omap.c436 /* Module is enabled, clocks are not gated */ omap_enable_gpio_module()
461 /* Module is disabled, clocks are gated */ omap_disable_gpio_module()
/linux-4.1.27/drivers/video/fbdev/mmp/hw/
H A Dmmp_ctrl.h518 #define CFG_GATED_ENA(gated) ((gated)<<21)
/linux-4.1.27/sound/soc/codecs/
H A Dab8500-codec.c2086 case SND_SOC_DAIFMT_GATED: /* clock is gated */ ab8500_codec_set_dai_clock_gate()
2087 dev_dbg(codec->dev, "%s: IF0 Clock is gated.\n", ab8500_codec_set_dai_clock_gate()
H A Dwm8995.c1895 /* Enable any gated AIF clocks */ wm8995_set_fll()
/linux-4.1.27/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c634 * enforced a specific MCLK divider while the clock was gated mpc512x_clk_setup_mclk()
/linux-4.1.27/arch/cris/arch-v10/drivers/
H A Dsync_serial.c829 clk_mode, gated); sync_serial_ioctl_unlocked()
/linux-4.1.27/drivers/media/pci/saa7134/
H A Dsaa7134-dvb.c993 * special case: lnb supply is connected to the gated i2c
/linux-4.1.27/drivers/staging/rtl8723au/hal/
H A Drtl8723a_hal_init.c1336 i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK _ResetDigitalProcedure1_92C()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192cu/
H A Dhw.c1139 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK _ResetDigitalProcedure1()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192de/
H A Dhw.c726 /* and PCIe gated clock function is enabled. */ _rtl92de_init_mac()
H A Dphy.c3089 /* g. SYS_CLKR 0x08[11] = 0 gated MAC clock */ _rtl92d_phy_set_rfsleep()
/linux-4.1.27/drivers/net/wireless/b43/
H A Dphy_n.h718 #define B43_NPHY_FINERX2_CGC_DECGC 0x0008 /* Decode gated clocks */
/linux-4.1.27/drivers/net/ethernet/marvell/
H A Dmv643xx_eth.c3071 /* Kirkwood resets some registers on gated clocks. Especially mv643xx_eth_probe()
/linux-4.1.27/drivers/net/ethernet/intel/igb/
H A Digb_main.c3571 * queue because it's gated by the VMOLR.RLPML. igb_rlpml_set()

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