| /linux-4.1.27/drivers/gpu/drm/radeon/ |
| D | radeon_clocks.c | 38 uint32_t fb_div, ref_div, post_div, sclk; in radeon_legacy_get_engine_clock() local
40 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); in radeon_legacy_get_engine_clock()
41 fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK; in radeon_legacy_get_engine_clock()
42 fb_div <<= 1; in radeon_legacy_get_engine_clock()
43 fb_div *= spll->reference_freq; in radeon_legacy_get_engine_clock()
51 sclk = fb_div / ref_div; in radeon_legacy_get_engine_clock()
68 uint32_t fb_div, ref_div, post_div, mclk; in radeon_legacy_get_memory_clock() local
70 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); in radeon_legacy_get_memory_clock()
71 fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK; in radeon_legacy_get_memory_clock()
72 fb_div <<= 1; in radeon_legacy_get_memory_clock()
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| D | radeon_display.c | 899 unsigned *fb_div, unsigned *ref_div) in avivo_get_fb_ref_div() argument
906 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in avivo_get_fb_ref_div()
909 if (*fb_div > fb_div_max) { in avivo_get_fb_ref_div()
910 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); in avivo_get_fb_ref_div()
911 *fb_div = fb_div_max; in avivo_get_fb_ref_div()
939 unsigned fb_div_min, fb_div_max, fb_div; in radeon_compute_pll_avivo() local
1019 ref_div_max, &fb_div, &ref_div); in radeon_compute_pll_avivo()
1020 diff = abs(target_clock - (pll->reference_freq * fb_div) / in radeon_compute_pll_avivo()
1034 &fb_div, &ref_div); in radeon_compute_pll_avivo()
1038 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); in radeon_compute_pll_avivo()
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| D | rs780_dpm.c | 87 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div); in rs780_initialize_dpm_power_state()
405 static void rs780_force_fbdiv(struct radeon_device *rdev, u32 fb_div) in rs780_force_fbdiv() argument
414 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div), in rs780_force_fbdiv()
416 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div), in rs780_force_fbdiv()
459 rs780_force_fbdiv(rdev, max_dividers.fb_div); in rs780_set_engine_clock_scaling()
461 if (max_dividers.fb_div > min_dividers.fb_div) { in rs780_set_engine_clock_scaling()
463 MIN_FEEDBACK_DIV(min_dividers.fb_div) | in rs780_set_engine_clock_scaling()
464 MAX_FEEDBACK_DIV(max_dividers.fb_div), in rs780_set_engine_clock_scaling()
1047 rs780_force_fbdiv(rdev, dividers.fb_div); in rs780_dpm_force_performance_level()
1054 rs780_force_fbdiv(rdev, dividers.fb_div); in rs780_dpm_force_performance_level()
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| D | radeon_uvd.c | 929 uint64_t fb_div = (uint64_t)vco_freq * fb_factor; in radeon_uvd_calc_upll_dividers() local
932 do_div(fb_div, ref_freq); in radeon_uvd_calc_upll_dividers()
935 if (fb_div > fb_mask) in radeon_uvd_calc_upll_dividers()
938 fb_div &= fb_mask; in radeon_uvd_calc_upll_dividers()
957 *optimal_fb_div = fb_div; in radeon_uvd_calc_upll_dividers()
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| D | atombios_crtc.c | 821 u32 fb_div, in atombios_crtc_program_pll() argument
848 args.v1.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
858 args.v2.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
868 args.v3.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
885 args.v5.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
914 args.v6.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
1063 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in atombios_crtc_set_pll() local
1095 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
1098 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
1101 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
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| D | rv730_dpm.c | 160 mpll_func_cntl_3 |= MPLL_FB_DIV(dividers.fb_div); in rv730_populate_mclk_value()
174 u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000); in rv730_populate_mclk_value()
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| D | rv770.c | 49 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks() local
69 &fb_div, &vclk_div, &dclk_div); in rv770_set_uvd_clocks()
73 fb_div |= 1; in rv770_set_uvd_clocks()
103 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), in rv770_set_uvd_clocks()
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| D | radeon_mode.h | 595 u32 fb_div; member
620 u32 fb_div; member
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| D | radeon_legacy_crtc.c | 263 uint16_t fb_div) in radeon_compute_pll_gain() argument
270 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; in radeon_compute_pll_gain()
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| D | r600.c | 152 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; in r600_set_uvd_clocks() local
181 &fb_div, &vclk_div, &dclk_div); in r600_set_uvd_clocks()
186 fb_div >>= 1; in r600_set_uvd_clocks()
188 fb_div |= 1; in r600_set_uvd_clocks()
204 UPLL_FB_DIV(fb_div) | in r600_set_uvd_clocks()
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| D | ni_dpm.c | 2096 u32 fb_div; in ni_init_smc_spll_table() local
2117 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in ni_init_smc_spll_table()
2121 fb_div &= ~0x00001FFF; in ni_init_smc_spll_table()
2122 fb_div >>= 1; in ni_init_smc_spll_table()
2140 …tmp = ((fb_div << SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MAS… in ni_init_smc_spll_table()
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| D | si_dpm.c | 2849 u32 fb_div, p_div; in si_init_smc_spll_table() local
2869 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in si_init_smc_spll_table()
2873 fb_div &= ~0x00001FFF; in si_init_smc_spll_table()
2874 fb_div >>= 1; in si_init_smc_spll_table()
2879 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) in si_init_smc_spll_table()
2889 …tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MAS… in si_init_smc_spll_table()
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| D | rv6xx_dpm.c | 530 return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) / in rv6xx_calculate_vco_frequency()
608 rv6xx_memory_clock_entry_set_feedback_divider(rdev, entry, dividers.fb_div); in rv6xx_program_mclk_stepping_entry()
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| D | evergreen.c | 1118 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in evergreen_set_uvd_clocks() local
1137 &fb_div, &vclk_div, &dclk_div); in evergreen_set_uvd_clocks()
1164 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); in evergreen_set_uvd_clocks()
1169 if (fb_div < 307200) in evergreen_set_uvd_clocks()
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| D | si.c | 7275 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in si_set_uvd_clocks() local
7293 &fb_div, &vclk_div, &dclk_div); in si_set_uvd_clocks()
7322 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); in si_set_uvd_clocks()
7327 if (fb_div < 307200) in si_set_uvd_clocks()
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| D | radeon_atombios.c | 2849 dividers->fb_div = args.v1.ucFbDiv; in radeon_atom_get_clock_dividers()
2863 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); in radeon_atom_get_clock_dividers()
2870 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; in radeon_atom_get_clock_dividers()
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| D | ci_dpm.c | 3151 fbdiv = dividers.fb_div & 0x3FFFFFF; in ci_calculate_sclk_params()
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| /linux-4.1.27/drivers/video/fbdev/aty/ |
| D | radeon_base.c | 1430 int fb_div, pll_output_freq = 0; in radeon_calc_pll_regs() local
1519 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq, in radeon_calc_pll_regs()
1522 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16); in radeon_calc_pll_regs()
1525 pr_debug("fb_div = 0x%x\n", fb_div); in radeon_calc_pll_regs()
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