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Searched refs:en_bit (Results 1 – 7 of 7) sorted by relevance

/linux-4.1.27/drivers/clk/bcm/
Dclk-kona.h132 u32 en_bit; /* 0: disable; 1: enable */ member
163 .en_bit = (_en_bit), \
175 .en_bit = (_en_bit), \
186 .en_bit = (_en_bit), \
197 .en_bit = (_en_bit), \
213 u32 en_bit; /* bit used to enable hysteresis */ member
222 .en_bit = (_en_bit), \
Dclk-kona-setup.c262 if (!bit_posn_valid(gate->en_bit, "gate enable", clock_name)) in gate_valid()
280 if (!bit_posn_valid(hyst->en_bit, "hysteresis enable", clock_name)) in hyst_valid()
Dclk-kona.c422 mask = (u32)1 << gate->en_bit; in __gate_commit()
535 mask = (u32)1 << hyst->en_bit; in hyst_init()
/linux-4.1.27/drivers/mfd/
Drc5t583.c89 unsigned int en_bit; in __rc5t583_set_ext_pwrreq1_control() local
97 en_bit = deepsleep_data[id].ds_pos_bit; in __rc5t583_set_ext_pwrreq1_control()
98 slot_bit = en_bit + 1; in __rc5t583_set_ext_pwrreq1_control()
106 sleepseq_val &= ~(0xF << en_bit); in __rc5t583_set_ext_pwrreq1_control()
107 sleepseq_val |= BIT(en_bit); in __rc5t583_set_ext_pwrreq1_control()
/linux-4.1.27/drivers/clk/
Dclk-vt8500.c34 int en_bit; member
93 en_val |= BIT(cdev->en_bit); in vt8500_dclk_enable()
109 en_val &= ~BIT(cdev->en_bit); in vt8500_dclk_disable()
118 u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit)); in vt8500_dclk_is_enabled()
255 rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit); in vtwm_device_clk_init()
Dclk-u300.c440 u8 en_bit; member
549 val &= BIT(sclk->en_bit); in syscon_clk_is_enabled()
696 void __iomem *en_reg, u8 en_bit, in syscon_clk_register() argument
721 sclk->en_bit = en_bit; in syscon_clk_register()
/linux-4.1.27/drivers/regulator/
Dltc3589.c199 #define LTC3589_REG(_name, _ops, en_bit, dtv1_reg, dtv_mask, go_bit) \ argument
216 .enable_reg = (en_bit) ? LTC3589_OVEN : 0, \
217 .enable_mask = (en_bit), \