Searched refs:eRFPath (Results 1 - 14 of 14) sorted by relevance

/linux-4.1.27/drivers/staging/rtl8192u/
H A Dr8190_rtl8256.c28 u8 eRFPath; PHY_SetRF8256Bandwidth() local
31 /* for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; PHY_SetRF8256Bandwidth()
32 * eRFPath++) PHY_SetRF8256Bandwidth()
34 for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) { PHY_SetRF8256Bandwidth()
35 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) PHY_SetRF8256Bandwidth()
44 (RF90_RADIO_PATH_E)eRFPath, PHY_SetRF8256Bandwidth()
47 (RF90_RADIO_PATH_E)eRFPath, PHY_SetRF8256Bandwidth()
50 (RF90_RADIO_PATH_E)eRFPath, PHY_SetRF8256Bandwidth()
53 (RF90_RADIO_PATH_E)eRFPath, PHY_SetRF8256Bandwidth()
61 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); /* phy para:3ba */ PHY_SetRF8256Bandwidth()
62 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3df); PHY_SetRF8256Bandwidth()
63 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0a1); PHY_SetRF8256Bandwidth()
67 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x59b); PHY_SetRF8256Bandwidth()
69 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab); PHY_SetRF8256Bandwidth()
107 u8 eRFPath; phy_RF8256_Config_ParaFile() local
116 for (eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < priv->NumTotalRFPath; eRFPath++) { phy_RF8256_Config_ParaFile()
117 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) phy_RF8256_Config_ParaFile()
120 pPhyReg = &priv->PHYRegDef[eRFPath]; phy_RF8256_Config_ParaFile()
123 * pHalData->RfReg0Value[eRFPath] = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rGlobalCtrl, bMaskDWord); phy_RF8256_Config_ParaFile()
126 switch (eRFPath) { phy_RF8256_Config_ParaFile()
147 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf); phy_RF8256_Config_ParaFile()
152 if (rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath)) { phy_RF8256_Config_ParaFile()
153 RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath); phy_RF8256_Config_ParaFile()
160 switch (eRFPath) { phy_RF8256_Config_ParaFile()
163 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath); phy_RF8256_Config_ParaFile()
164 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); phy_RF8256_Config_ParaFile()
165 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); phy_RF8256_Config_ParaFile()
171 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath); phy_RF8256_Config_ParaFile()
172 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); phy_RF8256_Config_ParaFile()
173 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); phy_RF8256_Config_ParaFile()
179 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath); phy_RF8256_Config_ParaFile()
180 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); phy_RF8256_Config_ParaFile()
181 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); phy_RF8256_Config_ParaFile()
187 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath); phy_RF8256_Config_ParaFile()
188 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); phy_RF8256_Config_ParaFile()
189 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); phy_RF8256_Config_ParaFile()
196 switch (eRFPath) { phy_RF8256_Config_ParaFile()
208 RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!", eRFPath); phy_RF8256_Config_ParaFile()
H A Dr819xU_phy.h60 extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath);
66 RF90_RADIO_PATH_E eRFPath, u32 reg_addr, u32 bitmask, u32 data);
68 RF90_RADIO_PATH_E eRFPath, u32 reg_addr, u32 bitmask);
72 HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
79 RF90_RADIO_PATH_E eRFPath);
H A Dr819xU_phy.c59 * u32 eRFPath
63 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath) rtl8192_phy_CheckIsLegalRFPath() argument
71 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) rtl8192_phy_CheckIsLegalRFPath()
73 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) rtl8192_phy_CheckIsLegalRFPath()
125 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
129 RF90_RADIO_PATH_E eRFPath, u32 offset,
135 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
147 RF90_RADIO_PATH_E eRFPath, u32 offset) rtl8192_phy_RFSerialRead()
152 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; rtl8192_phy_RFSerialRead()
161 priv->RfReg0Value[eRFPath] |= 0x140; rtl8192_phy_RFSerialRead()
165 priv->RfReg0Value[eRFPath]<<16); rtl8192_phy_RFSerialRead()
169 priv->RfReg0Value[eRFPath] |= 0x100; rtl8192_phy_RFSerialRead()
170 priv->RfReg0Value[eRFPath] &= (~0x40); rtl8192_phy_RFSerialRead()
174 priv->RfReg0Value[eRFPath]<<16); rtl8192_phy_RFSerialRead()
202 priv->RfReg0Value[eRFPath] &= 0xebf; rtl8192_phy_RFSerialRead()
205 priv->RfReg0Value[eRFPath] << 16); rtl8192_phy_RFSerialRead()
214 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
232 RF90_RADIO_PATH_E eRFPath, u32 offset, rtl8192_phy_RFSerialWrite()
237 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; rtl8192_phy_RFSerialWrite()
243 priv->RfReg0Value[eRFPath] |= 0x140; rtl8192_phy_RFSerialWrite()
246 priv->RfReg0Value[eRFPath] << 16); rtl8192_phy_RFSerialWrite()
249 priv->RfReg0Value[eRFPath] |= 0x100; rtl8192_phy_RFSerialWrite()
250 priv->RfReg0Value[eRFPath] &= (~0x40); rtl8192_phy_RFSerialWrite()
253 priv->RfReg0Value[eRFPath]<<16); rtl8192_phy_RFSerialWrite()
272 priv->RfReg0Value[eRFPath] = data; rtl8192_phy_RFSerialWrite()
277 priv->RfReg0Value[eRFPath] &= 0xebf; rtl8192_phy_RFSerialWrite()
280 priv->RfReg0Value[eRFPath] << 16); rtl8192_phy_RFSerialWrite()
288 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
296 void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, rtl8192_phy_SetRFReg() argument
302 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) rtl8192_phy_SetRFReg()
308 reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr); rtl8192_phy_SetRFReg()
313 phy_FwRFSerialWrite(dev, eRFPath, reg_addr, reg); rtl8192_phy_SetRFReg()
315 phy_FwRFSerialWrite(dev, eRFPath, reg_addr, data); rtl8192_phy_SetRFReg()
323 reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr); rtl8192_phy_SetRFReg()
328 rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, reg); rtl8192_phy_SetRFReg()
330 rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, data); rtl8192_phy_SetRFReg()
344 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, rtl8192_phy_QueryRFReg() argument
351 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) rtl8192_phy_QueryRFReg()
354 reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr); rtl8192_phy_QueryRFReg()
357 reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr); rtl8192_phy_QueryRFReg()
368 * RF90_RADIO_PATH_E eRFPath
374 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, phy_FwRFSerialRead() argument
390 data |= ((eRFPath&0x3)<<20); phy_FwRFSerialRead()
428 * RF90_RADIO_PATH_E eRFPath
436 RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data) phy_FwRFSerialWrite()
450 data |= ((eRFPath&0x3)<<20); phy_FwRFSerialWrite()
699 * RF90_RADIO_PATH_E eRFPath //only used when checkblock is
706 RF90_RADIO_PATH_E eRFPath) rtl8192_phy_checkBBAndRF()
737 rtl8192_phy_SetRFReg(dev, eRFPath, rtl8192_phy_checkBBAndRF()
743 reg = rtl8192_phy_QueryRFReg(dev, eRFPath, rtl8192_phy_checkBBAndRF()
970 * RF90_RADIO_PATH_E eRFPath
976 RF90_RADIO_PATH_E eRFPath) rtl8192_phy_ConfigRFWithHeaderFile()
981 switch (eRFPath) { rtl8192_phy_ConfigRFWithHeaderFile()
989 rtl8192_phy_SetRFReg(dev, eRFPath, rtl8192_phy_ConfigRFWithHeaderFile()
1004 rtl8192_phy_SetRFReg(dev, eRFPath, rtl8192_phy_ConfigRFWithHeaderFile()
1019 rtl8192_phy_SetRFReg(dev, eRFPath, rtl8192_phy_ConfigRFWithHeaderFile()
1034 rtl8192_phy_SetRFReg(dev, eRFPath, rtl8192_phy_ConfigRFWithHeaderFile()
1274 u8 eRFPath; rtl8192_phy_SwChnlStepByStep() local
1390 for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) { rtl8192_phy_SwChnlStepByStep()
1392 (RF90_RADIO_PATH_E)eRFPath, rtl8192_phy_SwChnlStepByStep()
146 rtl8192_phy_RFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, u32 offset) rtl8192_phy_RFSerialRead() argument
231 rtl8192_phy_RFSerialWrite(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data) rtl8192_phy_RFSerialWrite() argument
435 phy_FwRFSerialWrite(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data) phy_FwRFSerialWrite() argument
705 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath) rtl8192_phy_checkBBAndRF() argument
975 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, RF90_RADIO_PATH_E eRFPath) rtl8192_phy_ConfigRFWithHeaderFile() argument
H A Dr8192U_core.c2769 for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) rtl8192_adapter_start()
2770 PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0); rtl8192_adapter_start()
2783 for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) rtl8192_adapter_start()
2784 PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0); rtl8192_adapter_start()
/linux-4.1.27/drivers/staging/rtl8192e/rtl8192e/
H A Dr8190P_rtl8256.c28 u8 eRFPath; PHY_SetRF8256Bandwidth() local
31 for (eRFPath = 0; eRFPath < priv->NumTotalRFPath; eRFPath++) { PHY_SetRF8256Bandwidth()
32 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) PHY_SetRF8256Bandwidth()
40 (enum rf90_radio_path)eRFPath, PHY_SetRF8256Bandwidth()
43 (enum rf90_radio_path)eRFPath, PHY_SetRF8256Bandwidth()
46 (enum rf90_radio_path)eRFPath, PHY_SetRF8256Bandwidth()
59 (enum rf90_radio_path)eRFPath, PHY_SetRF8256Bandwidth()
62 (enum rf90_radio_path)eRFPath, PHY_SetRF8256Bandwidth()
65 (enum rf90_radio_path)eRFPath, PHY_SetRF8256Bandwidth()
96 u8 eRFPath; phy_RF8256_Config_ParaFile() local
106 for (eRFPath = (enum rf90_radio_path)RF90_PATH_A; phy_RF8256_Config_ParaFile()
107 eRFPath < priv->NumTotalRFPath; eRFPath++) { phy_RF8256_Config_ParaFile()
108 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) phy_RF8256_Config_ParaFile()
111 pPhyReg = &priv->PHYRegDef[eRFPath]; phy_RF8256_Config_ParaFile()
114 switch (eRFPath) { phy_RF8256_Config_ParaFile()
136 rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path) eRFPath, 0x0, phy_RF8256_Config_ParaFile()
140 (enum rf90_radio_path)eRFPath); phy_RF8256_Config_ParaFile()
144 eRFPath); phy_RF8256_Config_ParaFile()
150 switch (eRFPath) { phy_RF8256_Config_ParaFile()
155 (enum rf90_radio_path)eRFPath); phy_RF8256_Config_ParaFile()
157 (enum rf90_radio_path)eRFPath, phy_RF8256_Config_ParaFile()
162 eRFPath, RegOffSetToBeCheck, phy_RF8256_Config_ParaFile()
171 (enum rf90_radio_path)eRFPath); phy_RF8256_Config_ParaFile()
173 (enum rf90_radio_path)eRFPath, phy_RF8256_Config_ParaFile()
178 eRFPath, RegOffSetToBeCheck, phy_RF8256_Config_ParaFile()
187 (enum rf90_radio_path)eRFPath); phy_RF8256_Config_ParaFile()
189 (enum rf90_radio_path)eRFPath, phy_RF8256_Config_ParaFile()
194 eRFPath, RegOffSetToBeCheck, phy_RF8256_Config_ParaFile()
203 (enum rf90_radio_path)eRFPath); phy_RF8256_Config_ParaFile()
205 (enum rf90_radio_path)eRFPath, phy_RF8256_Config_ParaFile()
209 eRFPath, RegOffSetToBeCheck, phy_RF8256_Config_ParaFile()
216 switch (eRFPath) { phy_RF8256_Config_ParaFile()
232 eRFPath); phy_RF8256_Config_ParaFile()
H A Dr8192E_phy.c50 enum rf90_radio_path eRFPath,
53 enum rf90_radio_path eRFPath,
67 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath) rtl8192_phy_CheckIsLegalRFPath() argument
75 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) rtl8192_phy_CheckIsLegalRFPath()
77 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) rtl8192_phy_CheckIsLegalRFPath()
110 enum rf90_radio_path eRFPath, u32 Offset) rtl8192_phy_RFSerialRead()
115 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; rtl8192_phy_RFSerialRead()
122 priv->RfReg0Value[eRFPath] |= 0x140; rtl8192_phy_RFSerialRead()
125 (priv->RfReg0Value[eRFPath]<<16)); rtl8192_phy_RFSerialRead()
128 priv->RfReg0Value[eRFPath] |= 0x100; rtl8192_phy_RFSerialRead()
129 priv->RfReg0Value[eRFPath] &= (~0x40); rtl8192_phy_RFSerialRead()
132 (priv->RfReg0Value[eRFPath]<<16)); rtl8192_phy_RFSerialRead()
153 priv->RfReg0Value[eRFPath] &= 0xebf; rtl8192_phy_RFSerialRead()
156 (priv->RfReg0Value[eRFPath] << 16)); rtl8192_phy_RFSerialRead()
167 enum rf90_radio_path eRFPath, u32 Offset, rtl8192_phy_RFSerialWrite()
172 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; rtl8192_phy_RFSerialWrite()
179 priv->RfReg0Value[eRFPath] |= 0x140; rtl8192_phy_RFSerialWrite()
182 (priv->RfReg0Value[eRFPath] << 16)); rtl8192_phy_RFSerialWrite()
185 priv->RfReg0Value[eRFPath] |= 0x100; rtl8192_phy_RFSerialWrite()
186 priv->RfReg0Value[eRFPath] &= (~0x40); rtl8192_phy_RFSerialWrite()
189 (priv->RfReg0Value[eRFPath] << 16)); rtl8192_phy_RFSerialWrite()
204 priv->RfReg0Value[eRFPath] = Data; rtl8192_phy_RFSerialWrite()
208 priv->RfReg0Value[eRFPath] &= 0xebf; rtl8192_phy_RFSerialWrite()
213 (priv->RfReg0Value[eRFPath] << 16)); rtl8192_phy_RFSerialWrite()
219 void rtl8192_phy_SetRFReg(struct net_device *dev, enum rf90_radio_path eRFPath, rtl8192_phy_SetRFReg() argument
225 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) rtl8192_phy_SetRFReg()
233 Original_Value = phy_FwRFSerialRead(dev, eRFPath, rtl8192_phy_SetRFReg()
239 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value); rtl8192_phy_SetRFReg()
241 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data); rtl8192_phy_SetRFReg()
246 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, rtl8192_phy_SetRFReg()
252 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, rtl8192_phy_SetRFReg()
255 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data); rtl8192_phy_SetRFReg()
259 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, enum rf90_radio_path eRFPath, rtl8192_phy_QueryRFReg() argument
265 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) rtl8192_phy_QueryRFReg()
271 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); rtl8192_phy_QueryRFReg()
274 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, rtl8192_phy_QueryRFReg()
284 enum rf90_radio_path eRFPath, u32 Offset) phy_FwRFSerialRead()
290 Data |= ((eRFPath & 0x3) << 20); phy_FwRFSerialRead()
310 enum rf90_radio_path eRFPath, phy_FwRFSerialWrite()
316 Data |= ((eRFPath & 0x3) << 20); phy_FwRFSerialWrite()
494 enum rf90_radio_path eRFPath) rtl8192_phy_checkBBAndRF()
523 rtl8192_phy_SetRFReg(dev, eRFPath, rtl8192_phy_checkBBAndRF()
527 dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, rtl8192_phy_checkBBAndRF()
723 enum rf90_radio_path eRFPath) rtl8192_phy_ConfigRFWithHeaderFile()
728 switch (eRFPath) { rtl8192_phy_ConfigRFWithHeaderFile()
735 rtl8192_phy_SetRFReg(dev, eRFPath, rtl8192_phy_ConfigRFWithHeaderFile()
748 rtl8192_phy_SetRFReg(dev, eRFPath, rtl8192_phy_ConfigRFWithHeaderFile()
761 rtl8192_phy_SetRFReg(dev, eRFPath, rtl8192_phy_ConfigRFWithHeaderFile()
774 rtl8192_phy_SetRFReg(dev, eRFPath, rtl8192_phy_ConfigRFWithHeaderFile()
848 u8 eRFPath; rtl8192_phy_SwChnlStepByStep() local
962 for (eRFPath = 0; eRFPath < rtl8192_phy_SwChnlStepByStep()
963 priv->NumTotalRFPath; eRFPath++) rtl8192_phy_SwChnlStepByStep()
965 (enum rf90_radio_path)eRFPath, rtl8192_phy_SwChnlStepByStep()
109 rtl8192_phy_RFSerialRead(struct net_device *dev, enum rf90_radio_path eRFPath, u32 Offset) rtl8192_phy_RFSerialRead() argument
166 rtl8192_phy_RFSerialWrite(struct net_device *dev, enum rf90_radio_path eRFPath, u32 Offset, u32 Data) rtl8192_phy_RFSerialWrite() argument
283 phy_FwRFSerialRead(struct net_device *dev, enum rf90_radio_path eRFPath, u32 Offset) phy_FwRFSerialRead() argument
309 phy_FwRFSerialWrite(struct net_device *dev, enum rf90_radio_path eRFPath, u32 Offset, u32 Data) phy_FwRFSerialWrite() argument
492 rtl8192_phy_checkBBAndRF(struct net_device *dev, enum hw90_block CheckBlock, enum rf90_radio_path eRFPath) rtl8192_phy_checkBBAndRF() argument
722 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, enum rf90_radio_path eRFPath) rtl8192_phy_ConfigRFWithHeaderFile() argument
H A Dr8192E_phy.h77 u32 eRFPath);
83 enum rf90_radio_path eRFPath,
86 enum rf90_radio_path eRFPath,
92 enum rf90_radio_path eRFPath);
99 enum rf90_radio_path eRFPath);
/linux-4.1.27/drivers/staging/rtl8723au/hal/
H A Dodm_interface.c28 enum RF_RADIO_PATH eRFPath, ODM_SetRFReg()
36 PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data); ODM_SetRFReg()
41 enum RF_RADIO_PATH eRFPath, ODM_GetRFReg()
48 return PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask); ODM_GetRFReg()
26 ODM_SetRFReg( struct dm_odm_t *pDM_Odm, enum RF_RADIO_PATH eRFPath, u32 RegAddr, u32 BitMask, u32 Data ) ODM_SetRFReg() argument
39 ODM_GetRFReg( struct dm_odm_t *pDM_Odm, enum RF_RADIO_PATH eRFPath, u32 RegAddr, u32 BitMask ) ODM_GetRFReg() argument
H A Drtl8723a_phycfg.c146 * enum RF_RADIO_PATH eRFPath, Radio path of A/B/C/D
160 phy_RFSerialRead(struct rtw_adapter *Adapter, enum RF_RADIO_PATH eRFPath, phy_RFSerialRead() argument
165 struct bb_reg_define *pPhyReg = &pHalData->PHYRegDef[eRFPath]; phy_RFSerialRead()
191 if (eRFPath == RF_PATH_A) phy_RFSerialRead()
210 if (eRFPath == RF_PATH_A) phy_RFSerialRead()
214 else if (eRFPath == RF_PATH_B) phy_RFSerialRead()
230 /* DBG_8723A("RFR-%d Addr[0x%x]= 0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue); */ phy_RFSerialRead()
242 * enum RF_RADIO_PATH eRFPath, Radio path of A/B/C/D
280 phy_RFSerialWrite(struct rtw_adapter *Adapter, enum RF_RADIO_PATH eRFPath, phy_RFSerialWrite() argument
285 struct bb_reg_define *pPhyReg = &pHalData->PHYRegDef[eRFPath]; phy_RFSerialWrite()
301 /* PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data); */ phy_RFSerialWrite()
328 * enum RF_RADIO_PATH eRFPath, Radio path of A/B/C/D
341 PHY_QueryRFReg(struct rtw_adapter *Adapter, enum RF_RADIO_PATH eRFPath, PHY_QueryRFReg() argument
349 Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr); PHY_QueryRFReg()
364 * enum RF_RADIO_PATH eRFPath, Radio path of A/B/C/D
378 PHY_SetRFReg(struct rtw_adapter *Adapter, enum RF_RADIO_PATH eRFPath, PHY_SetRFReg() argument
387 Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr); PHY_SetRFReg()
392 phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data); PHY_SetRFReg()
940 enum RF_RADIO_PATH eRFPath; _PHY_SwChnl8723A() local
951 for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) { _PHY_SwChnl8723A()
952 pHalData->RfRegChnlVal[eRFPath] = _PHY_SwChnl8723A()
953 (pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2; _PHY_SwChnl8723A()
954 PHY_SetRFReg(Adapter, eRFPath, param1, _PHY_SwChnl8723A()
955 bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]); _PHY_SwChnl8723A()
H A Drtl8723a_rf6052.c430 u8 eRFPath; phy_RF6052_Config_ParaFile() local
438 for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) { phy_RF6052_Config_ParaFile()
440 pPhyReg = &pHalData->PHYRegDef[eRFPath]; phy_RF6052_Config_ParaFile()
443 switch (eRFPath) { phy_RF6052_Config_ParaFile()
472 switch (eRFPath) { phy_RF6052_Config_ParaFile()
481 switch (eRFPath) { phy_RF6052_Config_ParaFile()
/linux-4.1.27/drivers/staging/rtl8723au/include/
H A Dodm_interface.h57 void ODM_SetRFReg(struct dm_odm_t *pDM_Odm, enum RF_RADIO_PATH eRFPath,
59 u32 ODM_GetRFReg(struct dm_odm_t *pDM_Odm, enum RF_RADIO_PATH eRFPath,
H A DHal8723APhyCfg.h115 enum RF_RADIO_PATH eRFPath, u32 RegAddr,
118 enum RF_RADIO_PATH eRFPath, u32 RegAddr,
/linux-4.1.27/drivers/staging/rtl8188eu/include/
H A Dhal_intf.h217 enum rf_radio_path eRFPath, u32 RegAddr,
220 enum rf_radio_path eRFPath, u32 RegAddr,
301 u32 rtw_hal_read_rfreg(struct adapter *padapter, enum rf_radio_path eRFPath,
304 enum rf_radio_path eRFPath, u32 RegAddr,
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192cu/
H A Dhw.c1069 u8 eRFPath = 0, value8 = 0; _DisableRFAFEAndResetBB() local
1071 rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0); _DisableRFAFEAndResetBB()

Completed in 406 milliseconds