| H A D | ci_dpm.c | 432 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; ci_populate_bapm_parameters_in_dpm_table() local
440 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; ci_populate_bapm_parameters_in_dpm_table()
441 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; ci_populate_bapm_parameters_in_dpm_table()
443 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; ci_populate_bapm_parameters_in_dpm_table()
444 dpm_table->GpuTjMax = ci_populate_bapm_parameters_in_dpm_table()
446 dpm_table->GpuTjHyst = 8; ci_populate_bapm_parameters_in_dpm_table()
448 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; ci_populate_bapm_parameters_in_dpm_table()
451 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); ci_populate_bapm_parameters_in_dpm_table()
452 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); ci_populate_bapm_parameters_in_dpm_table()
454 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); ci_populate_bapm_parameters_in_dpm_table()
455 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0); ci_populate_bapm_parameters_in_dpm_table()
458 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient); ci_populate_bapm_parameters_in_dpm_table()
465 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1); ci_populate_bapm_parameters_in_dpm_table()
466 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2); ci_populate_bapm_parameters_in_dpm_table()
2525 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { ci_do_program_memory_timing_parameters()
2526 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { ci_do_program_memory_timing_parameters()
2528 pi->dpm_table.sclk_table.dpm_levels[i].value, ci_do_program_memory_timing_parameters()
2529 pi->dpm_table.mclk_table.dpm_levels[j].value, ci_do_program_memory_timing_parameters()
2580 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table) ci_get_dpm_level_enable_mask_value() argument
2585 for (i = dpm_table->count; i > 0; i--) { ci_get_dpm_level_enable_mask_value()
2587 if (dpm_table->dpm_levels[i-1].enabled) ci_get_dpm_level_enable_mask_value()
2600 struct ci_dpm_table *dpm_table = &pi->dpm_table; ci_populate_smc_link_level() local
2603 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) { ci_populate_smc_link_level()
2605 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; ci_populate_smc_link_level()
2607 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); ci_populate_smc_link_level()
2613 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; ci_populate_smc_link_level()
2615 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); ci_populate_smc_link_level()
3249 struct ci_dpm_table *dpm_table = &pi->dpm_table; ci_populate_all_graphic_levels() local
3259 for (i = 0; i < dpm_table->sclk_table.count; i++) { ci_populate_all_graphic_levels()
3261 dpm_table->sclk_table.dpm_levels[i].value, ci_populate_all_graphic_levels()
3268 if (i == (dpm_table->sclk_table.count - 1)) ci_populate_all_graphic_levels()
3274 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; ci_populate_all_graphic_levels()
3276 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); ci_populate_all_graphic_levels()
3296 struct ci_dpm_table *dpm_table = &pi->dpm_table; ci_populate_all_memory_levels() local
3306 for (i = 0; i < dpm_table->mclk_table.count; i++) { ci_populate_all_memory_levels()
3307 if (dpm_table->mclk_table.dpm_levels[i].value == 0) ci_populate_all_memory_levels()
3310 dpm_table->mclk_table.dpm_levels[i].value, ci_populate_all_memory_levels()
3318 if ((dpm_table->mclk_table.count >= 2) && ci_populate_all_memory_levels()
3328 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; ci_populate_all_memory_levels()
3330 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); ci_populate_all_memory_levels()
3332 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = ci_populate_all_memory_levels()
3345 struct ci_single_dpm_table* dpm_table, ci_reset_single_dpm_table()
3350 dpm_table->count = count; ci_reset_single_dpm_table()
3352 dpm_table->dpm_levels[i].enabled = false; ci_reset_single_dpm_table()
3355 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table, ci_setup_pcie_table_entry() argument
3358 dpm_table->dpm_levels[index].value = pcie_gen; ci_setup_pcie_table_entry()
3359 dpm_table->dpm_levels[index].param1 = pcie_lanes; ci_setup_pcie_table_entry()
3360 dpm_table->dpm_levels[index].enabled = true; ci_setup_pcie_table_entry()
3379 &pi->dpm_table.pcie_speed_table, ci_setup_default_pcie_tables()
3383 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, ci_setup_default_pcie_tables()
3387 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, ci_setup_default_pcie_tables()
3390 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, ci_setup_default_pcie_tables()
3393 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, ci_setup_default_pcie_tables()
3396 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, ci_setup_default_pcie_tables()
3399 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, ci_setup_default_pcie_tables()
3402 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, ci_setup_default_pcie_tables()
3406 pi->dpm_table.pcie_speed_table.count = 6; ci_setup_default_pcie_tables()
3431 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); ci_setup_default_dpm_tables()
3434 &pi->dpm_table.sclk_table, ci_setup_default_dpm_tables()
3437 &pi->dpm_table.mclk_table, ci_setup_default_dpm_tables()
3440 &pi->dpm_table.vddc_table, ci_setup_default_dpm_tables()
3443 &pi->dpm_table.vddci_table, ci_setup_default_dpm_tables()
3446 &pi->dpm_table.mvdd_table, ci_setup_default_dpm_tables()
3449 pi->dpm_table.sclk_table.count = 0; ci_setup_default_dpm_tables()
3452 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != ci_setup_default_dpm_tables()
3454 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = ci_setup_default_dpm_tables()
3456 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = ci_setup_default_dpm_tables()
3458 pi->dpm_table.sclk_table.count++; ci_setup_default_dpm_tables()
3462 pi->dpm_table.mclk_table.count = 0; ci_setup_default_dpm_tables()
3465 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != ci_setup_default_dpm_tables()
3467 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = ci_setup_default_dpm_tables()
3469 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = ci_setup_default_dpm_tables()
3471 pi->dpm_table.mclk_table.count++; ci_setup_default_dpm_tables()
3476 pi->dpm_table.vddc_table.dpm_levels[i].value = ci_setup_default_dpm_tables()
3478 pi->dpm_table.vddc_table.dpm_levels[i].param1 = ci_setup_default_dpm_tables()
3480 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; ci_setup_default_dpm_tables()
3482 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; ci_setup_default_dpm_tables()
3487 pi->dpm_table.vddci_table.dpm_levels[i].value = ci_setup_default_dpm_tables()
3489 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; ci_setup_default_dpm_tables()
3491 pi->dpm_table.vddci_table.count = allowed_mclk_table->count; ci_setup_default_dpm_tables()
3497 pi->dpm_table.mvdd_table.dpm_levels[i].value = ci_setup_default_dpm_tables()
3499 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; ci_setup_default_dpm_tables()
3501 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; ci_setup_default_dpm_tables()
3599 ret = ci_find_boot_level(&pi->dpm_table.sclk_table, ci_init_smc_table()
3603 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, ci_init_smc_table()
3636 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; ci_init_smc_table()
3674 struct ci_single_dpm_table *dpm_table, ci_trim_single_dpm_states()
3679 for (i = 0; i < dpm_table->count; i++) { ci_trim_single_dpm_states()
3680 if ((dpm_table->dpm_levels[i].value < low_limit) || ci_trim_single_dpm_states()
3681 (dpm_table->dpm_levels[i].value > high_limit)) ci_trim_single_dpm_states()
3682 dpm_table->dpm_levels[i].enabled = false; ci_trim_single_dpm_states()
3684 dpm_table->dpm_levels[i].enabled = true; ci_trim_single_dpm_states()
3693 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; ci_trim_pcie_dpm_states()
3735 &pi->dpm_table.sclk_table, ci_trim_dpm_states()
3740 &pi->dpm_table.mclk_table, ci_trim_dpm_states()
3830 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; ci_find_dpm_states_clocks_in_dpm_table()
3832 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; ci_find_dpm_states_clocks_in_dpm_table()
3871 struct ci_dpm_table *dpm_table = &pi->dpm_table; ci_populate_and_upload_sclk_mclk_dpm_levels() local
3878 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk; ci_populate_and_upload_sclk_mclk_dpm_levels()
3881 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk; ci_populate_and_upload_sclk_mclk_dpm_levels()
4146 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); ci_generate_dpm_level_enable_mask()
4148 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); ci_generate_dpm_level_enable_mask()
4156 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); ci_generate_dpm_level_enable_mask()
4711 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) ci_convert_mc_reg_table_to_smc()
4713 pi->dpm_table.mclk_table.dpm_levels[i].value, ci_convert_mc_reg_table_to_smc()
4752 pi->dpm_table.mclk_table.count, ci_update_and_upload_mc_reg_table()
5642 SMU7_Discrete_DpmTable *dpm_table; ci_dpm_init() local
5778 dpm_table = &pi->smc_state_table; ci_dpm_init()
5782 dpm_table->VRHotGpio = gpio.shift; ci_dpm_init()
5785 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN; ci_dpm_init()
5791 dpm_table->AcDcGpio = gpio.shift; ci_dpm_init()
5794 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN; ci_dpm_init()
3344 ci_reset_single_dpm_table(struct radeon_device *rdev, struct ci_single_dpm_table* dpm_table, u32 count) ci_reset_single_dpm_table() argument
3673 ci_trim_single_dpm_states(struct radeon_device *rdev, struct ci_single_dpm_table *dpm_table, u32 low_limit, u32 high_limit) ci_trim_single_dpm_states() argument
|